/* SPDX-License-Identifier: GPL-2.0 */ #ifndef LINUX_SSB_REGS_H_ #define LINUX_SSB_REGS_H_ /* SiliconBackplane Address Map. * All regions may not exist on all chips. */ #define SSB_SDRAM_BASE … #define SSB_PCI_MEM … #define SSB_PCI_CFG … #define SSB_SDRAM_SWAPPED … #define SSB_ENUM_BASE … #define SSB_ENUM_LIMIT … #define SSB_FLASH2 … #define SSB_FLASH2_SZ … #define SSB_EXTIF_BASE … #define SSB_FLASH1 … #define SSB_FLASH1_SZ … #define SSB_PCI_DMA … #define SSB_PCI_DMA_SZ … #define SSB_PCIE_DMA_L32 … #define SSB_PCIE_DMA_H32 … #define SSB_EUART … #define SSB_LED … /* Enumeration space constants */ #define SSB_CORE_SIZE … #define SSB_MAX_NR_CORES … /* mips address */ #define SSB_EJTAG … /* SSB PCI config space registers. */ #define SSB_PMCSR … #define SSB_PE … #define SSB_BAR0_WIN … #define SSB_BAR1_WIN … #define SSB_SPROMCTL … #define SSB_SPROMCTL_WE … #define SSB_BAR1_CONTROL … #define SSB_PCI_IRQS … #define SSB_PCI_IRQMASK … #define SSB_BACKPLANE_IRQS … #define SSB_GPIO_IN … #define SSB_GPIO_OUT … #define SSB_GPIO_OUT_ENABLE … #define SSB_GPIO_SCS … #define SSB_GPIO_HWRAD … #define SSB_GPIO_XTAL … #define SSB_GPIO_PLL … #define SSB_BAR0_MAX_RETRIES … /* Silicon backplane configuration register definitions */ #define SSB_IPSFLAG … #define SSB_IPSFLAG_IRQ1 … #define SSB_IPSFLAG_IRQ1_SHIFT … #define SSB_IPSFLAG_IRQ2 … #define SSB_IPSFLAG_IRQ2_SHIFT … #define SSB_IPSFLAG_IRQ3 … #define SSB_IPSFLAG_IRQ3_SHIFT … #define SSB_IPSFLAG_IRQ4 … #define SSB_IPSFLAG_IRQ4_SHIFT … #define SSB_TPSFLAG … #define SSB_TPSFLAG_BPFLAG … #define SSB_TPSFLAG_ALWAYSIRQ … #define SSB_TMERRLOGA … #define SSB_TMERRLOG … #define SSB_ADMATCH3 … #define SSB_ADMATCH2 … #define SSB_ADMATCH1 … #define SSB_IMSTATE … #define SSB_IMSTATE_PC … #define SSB_IMSTATE_AP_MASK … #define SSB_IMSTATE_AP_BOTH … #define SSB_IMSTATE_AP_TS … #define SSB_IMSTATE_AP_TK … #define SSB_IMSTATE_AP_RSV … #define SSB_IMSTATE_IBE … #define SSB_IMSTATE_TO … #define SSB_IMSTATE_BUSY … #define SSB_IMSTATE_REJECT … #define SSB_INTVEC … #define SSB_INTVEC_PCI … #define SSB_INTVEC_ENET0 … #define SSB_INTVEC_ILINE20 … #define SSB_INTVEC_CODEC … #define SSB_INTVEC_USB … #define SSB_INTVEC_EXTIF … #define SSB_INTVEC_ENET1 … #define SSB_TMSLOW … #define SSB_TMSLOW_RESET … #define SSB_TMSLOW_REJECT … #define SSB_TMSLOW_REJECT_23 … #define SSB_TMSLOW_CLOCK … #define SSB_TMSLOW_FGC … #define SSB_TMSLOW_PE … #define SSB_TMSLOW_BE … #define SSB_TMSHIGH … #define SSB_TMSHIGH_SERR … #define SSB_TMSHIGH_INT … #define SSB_TMSHIGH_BUSY … #define SSB_TMSHIGH_TO … #define SSB_TMSHIGH_COREFL … #define SSB_TMSHIGH_COREFL_SHIFT … #define SSB_TMSHIGH_DMA64 … #define SSB_TMSHIGH_GCR … #define SSB_TMSHIGH_BISTF … #define SSB_TMSHIGH_BISTD … #define SSB_BWA0 … #define SSB_IMCFGLO … #define SSB_IMCFGLO_SERTO … #define SSB_IMCFGLO_REQTO … #define SSB_IMCFGLO_REQTO_SHIFT … #define SSB_IMCFGLO_CONNID … #define SSB_IMCFGLO_CONNID_SHIFT … #define SSB_IMCFGHI … #define SSB_ADMATCH0 … #define SSB_TMCFGLO … #define SSB_TMCFGHI … #define SSB_BCONFIG … #define SSB_BSTATE … #define SSB_ACTCFG … #define SSB_FLAGST … #define SSB_IDLOW … #define SSB_IDLOW_CFGSP … #define SSB_IDLOW_ADDRNGE … #define SSB_IDLOW_ADDRNGE_SHIFT … #define SSB_IDLOW_SYNC … #define SSB_IDLOW_INITIATOR … #define SSB_IDLOW_MIBL … #define SSB_IDLOW_MIBL_SHIFT … #define SSB_IDLOW_MABL … #define SSB_IDLOW_MABL_SHIFT … #define SSB_IDLOW_TIF … #define SSB_IDLOW_CCW … #define SSB_IDLOW_CCW_SHIFT … #define SSB_IDLOW_TPT … #define SSB_IDLOW_TPT_SHIFT … #define SSB_IDLOW_INITP … #define SSB_IDLOW_INITP_SHIFT … #define SSB_IDLOW_SSBREV … #define SSB_IDLOW_SSBREV_22 … #define SSB_IDLOW_SSBREV_23 … #define SSB_IDLOW_SSBREV_24 … #define SSB_IDLOW_SSBREV_25 … #define SSB_IDLOW_SSBREV_26 … #define SSB_IDLOW_SSBREV_27 … #define SSB_IDHIGH … #define SSB_IDHIGH_RCLO … #define SSB_IDHIGH_CC … #define SSB_IDHIGH_CC_SHIFT … #define SSB_IDHIGH_RCHI … #define SSB_IDHIGH_RCHI_SHIFT … #define SSB_IDHIGH_VC … #define SSB_IDHIGH_VC_SHIFT … /* SPROM shadow area. If not otherwise noted, fields are * two bytes wide. Note that the SPROM can _only_ be read * in two-byte quantities. */ #define SSB_SPROMSIZE_WORDS … #define SSB_SPROMSIZE_BYTES … #define SSB_SPROMSIZE_WORDS_R123 … #define SSB_SPROMSIZE_WORDS_R4 … #define SSB_SPROMSIZE_BYTES_R123 … #define SSB_SPROMSIZE_BYTES_R4 … #define SSB_SPROMSIZE_WORDS_R10 … #define SSB_SPROMSIZE_WORDS_R11 … #define SSB_SPROM_BASE1 … #define SSB_SPROM_BASE31 … #define SSB_SPROM_REVISION … #define SSB_SPROM_REVISION_REV … #define SSB_SPROM_REVISION_CRC … #define SSB_SPROM_REVISION_CRC_SHIFT … /* SPROM Revision 1 */ #define SSB_SPROM1_SPID … #define SSB_SPROM1_SVID … #define SSB_SPROM1_PID … #define SSB_SPROM1_IL0MAC … #define SSB_SPROM1_ET0MAC … #define SSB_SPROM1_ET1MAC … #define SSB_SPROM1_ETHPHY … #define SSB_SPROM1_ETHPHY_ET0A … #define SSB_SPROM1_ETHPHY_ET1A … #define SSB_SPROM1_ETHPHY_ET1A_SHIFT … #define SSB_SPROM1_ETHPHY_ET0M … #define SSB_SPROM1_ETHPHY_ET1M … #define SSB_SPROM1_BINF … #define SSB_SPROM1_BINF_BREV … #define SSB_SPROM1_BINF_CCODE … #define SSB_SPROM1_BINF_CCODE_SHIFT … #define SSB_SPROM1_BINF_ANTBG … #define SSB_SPROM1_BINF_ANTBG_SHIFT … #define SSB_SPROM1_BINF_ANTA … #define SSB_SPROM1_BINF_ANTA_SHIFT … #define SSB_SPROM1_PA0B0 … #define SSB_SPROM1_PA0B1 … #define SSB_SPROM1_PA0B2 … #define SSB_SPROM1_GPIOA … #define SSB_SPROM1_GPIOA_P0 … #define SSB_SPROM1_GPIOA_P1 … #define SSB_SPROM1_GPIOA_P1_SHIFT … #define SSB_SPROM1_GPIOB … #define SSB_SPROM1_GPIOB_P2 … #define SSB_SPROM1_GPIOB_P3 … #define SSB_SPROM1_GPIOB_P3_SHIFT … #define SSB_SPROM1_MAXPWR … #define SSB_SPROM1_MAXPWR_BG … #define SSB_SPROM1_MAXPWR_A … #define SSB_SPROM1_MAXPWR_A_SHIFT … #define SSB_SPROM1_PA1B0 … #define SSB_SPROM1_PA1B1 … #define SSB_SPROM1_PA1B2 … #define SSB_SPROM1_ITSSI … #define SSB_SPROM1_ITSSI_BG … #define SSB_SPROM1_ITSSI_A … #define SSB_SPROM1_ITSSI_A_SHIFT … #define SSB_SPROM1_BFLLO … #define SSB_SPROM1_AGAIN … #define SSB_SPROM1_AGAIN_BG … #define SSB_SPROM1_AGAIN_BG_SHIFT … #define SSB_SPROM1_AGAIN_A … #define SSB_SPROM1_AGAIN_A_SHIFT … #define SSB_SPROM1_CCODE … /* SPROM Revision 2 (inherits from rev 1) */ #define SSB_SPROM2_BFLHI … #define SSB_SPROM2_MAXP_A … #define SSB_SPROM2_MAXP_A_HI … #define SSB_SPROM2_MAXP_A_LO … #define SSB_SPROM2_MAXP_A_LO_SHIFT … #define SSB_SPROM2_PA1LOB0 … #define SSB_SPROM2_PA1LOB1 … #define SSB_SPROM2_PA1LOB2 … #define SSB_SPROM2_PA1HIB0 … #define SSB_SPROM2_PA1HIB1 … #define SSB_SPROM2_PA1HIB2 … #define SSB_SPROM2_OPO … #define SSB_SPROM2_OPO_VALUE … #define SSB_SPROM2_OPO_UNUSED … #define SSB_SPROM2_CCODE … /* SPROM Revision 3 (inherits most data from rev 2) */ #define SSB_SPROM3_OFDMAPO … #define SSB_SPROM3_OFDMALPO … #define SSB_SPROM3_OFDMAHPO … #define SSB_SPROM3_GPIOLDC … #define SSB_SPROM3_GPIOLDC_OFF … #define SSB_SPROM3_GPIOLDC_OFF_SHIFT … #define SSB_SPROM3_GPIOLDC_ON … #define SSB_SPROM3_GPIOLDC_ON_SHIFT … #define SSB_SPROM3_IL0MAC … #define SSB_SPROM3_CCKPO … #define SSB_SPROM3_CCKPO_1M … #define SSB_SPROM3_CCKPO_2M … #define SSB_SPROM3_CCKPO_2M_SHIFT … #define SSB_SPROM3_CCKPO_55M … #define SSB_SPROM3_CCKPO_55M_SHIFT … #define SSB_SPROM3_CCKPO_11M … #define SSB_SPROM3_CCKPO_11M_SHIFT … #define SSB_SPROM3_OFDMGPO … /* SPROM Revision 4 */ #define SSB_SPROM4_BOARDREV … #define SSB_SPROM4_BFLLO … #define SSB_SPROM4_BFLHI … #define SSB_SPROM4_BFL2LO … #define SSB_SPROM4_BFL2HI … #define SSB_SPROM4_IL0MAC … #define SSB_SPROM4_CCODE … #define SSB_SPROM4_GPIOA … #define SSB_SPROM4_GPIOA_P0 … #define SSB_SPROM4_GPIOA_P1 … #define SSB_SPROM4_GPIOA_P1_SHIFT … #define SSB_SPROM4_GPIOB … #define SSB_SPROM4_GPIOB_P2 … #define SSB_SPROM4_GPIOB_P3 … #define SSB_SPROM4_GPIOB_P3_SHIFT … #define SSB_SPROM4_ETHPHY … #define SSB_SPROM4_ETHPHY_ET0A … #define SSB_SPROM4_ETHPHY_ET1A … #define SSB_SPROM4_ETHPHY_ET1A_SHIFT … #define SSB_SPROM4_ETHPHY_ET0M … #define SSB_SPROM4_ETHPHY_ET1M … #define SSB_SPROM4_ANTAVAIL … #define SSB_SPROM4_ANTAVAIL_BG … #define SSB_SPROM4_ANTAVAIL_BG_SHIFT … #define SSB_SPROM4_ANTAVAIL_A … #define SSB_SPROM4_ANTAVAIL_A_SHIFT … #define SSB_SPROM4_AGAIN01 … #define SSB_SPROM4_AGAIN0 … #define SSB_SPROM4_AGAIN0_SHIFT … #define SSB_SPROM4_AGAIN1 … #define SSB_SPROM4_AGAIN1_SHIFT … #define SSB_SPROM4_AGAIN23 … #define SSB_SPROM4_AGAIN2 … #define SSB_SPROM4_AGAIN2_SHIFT … #define SSB_SPROM4_AGAIN3 … #define SSB_SPROM4_AGAIN3_SHIFT … #define SSB_SPROM4_TXPID2G01 … #define SSB_SPROM4_TXPID2G0 … #define SSB_SPROM4_TXPID2G0_SHIFT … #define SSB_SPROM4_TXPID2G1 … #define SSB_SPROM4_TXPID2G1_SHIFT … #define SSB_SPROM4_TXPID2G23 … #define SSB_SPROM4_TXPID2G2 … #define SSB_SPROM4_TXPID2G2_SHIFT … #define SSB_SPROM4_TXPID2G3 … #define SSB_SPROM4_TXPID2G3_SHIFT … #define SSB_SPROM4_TXPID5G01 … #define SSB_SPROM4_TXPID5G0 … #define SSB_SPROM4_TXPID5G0_SHIFT … #define SSB_SPROM4_TXPID5G1 … #define SSB_SPROM4_TXPID5G1_SHIFT … #define SSB_SPROM4_TXPID5G23 … #define SSB_SPROM4_TXPID5G2 … #define SSB_SPROM4_TXPID5G2_SHIFT … #define SSB_SPROM4_TXPID5G3 … #define SSB_SPROM4_TXPID5G3_SHIFT … #define SSB_SPROM4_TXPID5GL01 … #define SSB_SPROM4_TXPID5GL0 … #define SSB_SPROM4_TXPID5GL0_SHIFT … #define SSB_SPROM4_TXPID5GL1 … #define SSB_SPROM4_TXPID5GL1_SHIFT … #define SSB_SPROM4_TXPID5GL23 … #define SSB_SPROM4_TXPID5GL2 … #define SSB_SPROM4_TXPID5GL2_SHIFT … #define SSB_SPROM4_TXPID5GL3 … #define SSB_SPROM4_TXPID5GL3_SHIFT … #define SSB_SPROM4_TXPID5GH01 … #define SSB_SPROM4_TXPID5GH0 … #define SSB_SPROM4_TXPID5GH0_SHIFT … #define SSB_SPROM4_TXPID5GH1 … #define SSB_SPROM4_TXPID5GH1_SHIFT … #define SSB_SPROM4_TXPID5GH23 … #define SSB_SPROM4_TXPID5GH2 … #define SSB_SPROM4_TXPID5GH2_SHIFT … #define SSB_SPROM4_TXPID5GH3 … #define SSB_SPROM4_TXPID5GH3_SHIFT … /* There are 4 blocks with power info sharing the same layout */ #define SSB_SPROM4_PWR_INFO_CORE0 … #define SSB_SPROM4_PWR_INFO_CORE1 … #define SSB_SPROM4_PWR_INFO_CORE2 … #define SSB_SPROM4_PWR_INFO_CORE3 … #define SSB_SPROM4_2G_MAXP_ITSSI … #define SSB_SPROM4_2G_MAXP … #define SSB_SPROM4_2G_ITSSI … #define SSB_SPROM4_2G_ITSSI_SHIFT … #define SSB_SPROM4_2G_PA_0 … #define SSB_SPROM4_2G_PA_1 … #define SSB_SPROM4_2G_PA_2 … #define SSB_SPROM4_2G_PA_3 … #define SSB_SPROM4_5G_MAXP_ITSSI … #define SSB_SPROM4_5G_MAXP … #define SSB_SPROM4_5G_ITSSI … #define SSB_SPROM4_5G_ITSSI_SHIFT … #define SSB_SPROM4_5GHL_MAXP … #define SSB_SPROM4_5GH_MAXP … #define SSB_SPROM4_5GL_MAXP … #define SSB_SPROM4_5GL_MAXP_SHIFT … #define SSB_SPROM4_5G_PA_0 … #define SSB_SPROM4_5G_PA_1 … #define SSB_SPROM4_5G_PA_2 … #define SSB_SPROM4_5G_PA_3 … #define SSB_SPROM4_5GL_PA_0 … #define SSB_SPROM4_5GL_PA_1 … #define SSB_SPROM4_5GL_PA_2 … #define SSB_SPROM4_5GL_PA_3 … #define SSB_SPROM4_5GH_PA_0 … #define SSB_SPROM4_5GH_PA_1 … #define SSB_SPROM4_5GH_PA_2 … #define SSB_SPROM4_5GH_PA_3 … /* TODO: Make it deprecated */ #define SSB_SPROM4_MAXP_BG … #define SSB_SPROM4_MAXP_BG_MASK … #define SSB_SPROM4_ITSSI_BG … #define SSB_SPROM4_ITSSI_BG_SHIFT … #define SSB_SPROM4_MAXP_A … #define SSB_SPROM4_MAXP_A_MASK … #define SSB_SPROM4_ITSSI_A … #define SSB_SPROM4_ITSSI_A_SHIFT … #define SSB_SPROM4_PA0B0 … #define SSB_SPROM4_PA0B1 … #define SSB_SPROM4_PA0B2 … #define SSB_SPROM4_PA1B0 … #define SSB_SPROM4_PA1B1 … #define SSB_SPROM4_PA1B2 … /* SPROM Revision 5 (inherits most data from rev 4) */ #define SSB_SPROM5_CCODE … #define SSB_SPROM5_BFLLO … #define SSB_SPROM5_BFLHI … #define SSB_SPROM5_BFL2LO … #define SSB_SPROM5_BFL2HI … #define SSB_SPROM5_IL0MAC … #define SSB_SPROM5_GPIOA … #define SSB_SPROM5_GPIOA_P0 … #define SSB_SPROM5_GPIOA_P1 … #define SSB_SPROM5_GPIOA_P1_SHIFT … #define SSB_SPROM5_GPIOB … #define SSB_SPROM5_GPIOB_P2 … #define SSB_SPROM5_GPIOB_P3 … #define SSB_SPROM5_GPIOB_P3_SHIFT … /* SPROM Revision 8 */ #define SSB_SPROM8_BOARDREV … #define SSB_SPROM8_BFLLO … #define SSB_SPROM8_BFLHI … #define SSB_SPROM8_BFL2LO … #define SSB_SPROM8_BFL2HI … #define SSB_SPROM8_IL0MAC … #define SSB_SPROM8_CCODE … #define SSB_SPROM8_GPIOA … #define SSB_SPROM8_GPIOA_P0 … #define SSB_SPROM8_GPIOA_P1 … #define SSB_SPROM8_GPIOA_P1_SHIFT … #define SSB_SPROM8_GPIOB … #define SSB_SPROM8_GPIOB_P2 … #define SSB_SPROM8_GPIOB_P3 … #define SSB_SPROM8_GPIOB_P3_SHIFT … #define SSB_SPROM8_LEDDC … #define SSB_SPROM8_LEDDC_ON … #define SSB_SPROM8_LEDDC_ON_SHIFT … #define SSB_SPROM8_LEDDC_OFF … #define SSB_SPROM8_LEDDC_OFF_SHIFT … #define SSB_SPROM8_ANTAVAIL … #define SSB_SPROM8_ANTAVAIL_A … #define SSB_SPROM8_ANTAVAIL_A_SHIFT … #define SSB_SPROM8_ANTAVAIL_BG … #define SSB_SPROM8_ANTAVAIL_BG_SHIFT … #define SSB_SPROM8_AGAIN01 … #define SSB_SPROM8_AGAIN0 … #define SSB_SPROM8_AGAIN0_SHIFT … #define SSB_SPROM8_AGAIN1 … #define SSB_SPROM8_AGAIN1_SHIFT … #define SSB_SPROM8_AGAIN23 … #define SSB_SPROM8_AGAIN2 … #define SSB_SPROM8_AGAIN2_SHIFT … #define SSB_SPROM8_AGAIN3 … #define SSB_SPROM8_AGAIN3_SHIFT … #define SSB_SPROM8_TXRXC … #define SSB_SPROM8_TXRXC_TXCHAIN … #define SSB_SPROM8_TXRXC_TXCHAIN_SHIFT … #define SSB_SPROM8_TXRXC_RXCHAIN … #define SSB_SPROM8_TXRXC_RXCHAIN_SHIFT … #define SSB_SPROM8_TXRXC_SWITCH … #define SSB_SPROM8_TXRXC_SWITCH_SHIFT … #define SSB_SPROM8_RSSIPARM2G … #define SSB_SPROM8_RSSISMF2G … #define SSB_SPROM8_RSSISMC2G … #define SSB_SPROM8_RSSISMC2G_SHIFT … #define SSB_SPROM8_RSSISAV2G … #define SSB_SPROM8_RSSISAV2G_SHIFT … #define SSB_SPROM8_BXA2G … #define SSB_SPROM8_BXA2G_SHIFT … #define SSB_SPROM8_RSSIPARM5G … #define SSB_SPROM8_RSSISMF5G … #define SSB_SPROM8_RSSISMC5G … #define SSB_SPROM8_RSSISMC5G_SHIFT … #define SSB_SPROM8_RSSISAV5G … #define SSB_SPROM8_RSSISAV5G_SHIFT … #define SSB_SPROM8_BXA5G … #define SSB_SPROM8_BXA5G_SHIFT … #define SSB_SPROM8_TRI25G … #define SSB_SPROM8_TRI2G … #define SSB_SPROM8_TRI5G … #define SSB_SPROM8_TRI5G_SHIFT … #define SSB_SPROM8_TRI5GHL … #define SSB_SPROM8_TRI5GL … #define SSB_SPROM8_TRI5GH … #define SSB_SPROM8_TRI5GH_SHIFT … #define SSB_SPROM8_RXPO … #define SSB_SPROM8_RXPO2G … #define SSB_SPROM8_RXPO2G_SHIFT … #define SSB_SPROM8_RXPO5G … #define SSB_SPROM8_RXPO5G_SHIFT … #define SSB_SPROM8_FEM2G … #define SSB_SPROM8_FEM5G … #define SSB_SROM8_FEM_TSSIPOS … #define SSB_SROM8_FEM_TSSIPOS_SHIFT … #define SSB_SROM8_FEM_EXTPA_GAIN … #define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT … #define SSB_SROM8_FEM_PDET_RANGE … #define SSB_SROM8_FEM_PDET_RANGE_SHIFT … #define SSB_SROM8_FEM_TR_ISO … #define SSB_SROM8_FEM_TR_ISO_SHIFT … #define SSB_SROM8_FEM_ANTSWLUT … #define SSB_SROM8_FEM_ANTSWLUT_SHIFT … #define SSB_SPROM8_THERMAL … #define SSB_SPROM8_THERMAL_OFFSET … #define SSB_SPROM8_THERMAL_OFFSET_SHIFT … #define SSB_SPROM8_THERMAL_TRESH … #define SSB_SPROM8_THERMAL_TRESH_SHIFT … /* Temp sense related entries */ #define SSB_SPROM8_RAWTS … #define SSB_SPROM8_RAWTS_RAWTEMP … #define SSB_SPROM8_RAWTS_RAWTEMP_SHIFT … #define SSB_SPROM8_RAWTS_MEASPOWER … #define SSB_SPROM8_RAWTS_MEASPOWER_SHIFT … #define SSB_SPROM8_OPT_CORRX … #define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE … #define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT … #define SSB_SPROM8_OPT_CORRX_TEMPCORRX … #define SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT … #define SSB_SPROM8_OPT_CORRX_TEMP_OPTION … #define SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT … /* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */ #define SSB_SPROM8_HWIQ_IQSWP … #define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR … #define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT … #define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP … #define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT … #define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL … #define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT … #define SSB_SPROM8_TEMPDELTA … #define SSB_SPROM8_TEMPDELTA_PHYCAL … #define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT … #define SSB_SPROM8_TEMPDELTA_PERIOD … #define SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT … #define SSB_SPROM8_TEMPDELTA_HYSTERESIS … #define SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT … /* There are 4 blocks with power info sharing the same layout */ #define SSB_SROM8_PWR_INFO_CORE0 … #define SSB_SROM8_PWR_INFO_CORE1 … #define SSB_SROM8_PWR_INFO_CORE2 … #define SSB_SROM8_PWR_INFO_CORE3 … #define SSB_SROM8_2G_MAXP_ITSSI … #define SSB_SPROM8_2G_MAXP … #define SSB_SPROM8_2G_ITSSI … #define SSB_SPROM8_2G_ITSSI_SHIFT … #define SSB_SROM8_2G_PA_0 … #define SSB_SROM8_2G_PA_1 … #define SSB_SROM8_2G_PA_2 … #define SSB_SROM8_5G_MAXP_ITSSI … #define SSB_SPROM8_5G_MAXP … #define SSB_SPROM8_5G_ITSSI … #define SSB_SPROM8_5G_ITSSI_SHIFT … #define SSB_SPROM8_5GHL_MAXP … #define SSB_SPROM8_5GH_MAXP … #define SSB_SPROM8_5GL_MAXP … #define SSB_SPROM8_5GL_MAXP_SHIFT … #define SSB_SROM8_5G_PA_0 … #define SSB_SROM8_5G_PA_1 … #define SSB_SROM8_5G_PA_2 … #define SSB_SROM8_5GL_PA_0 … #define SSB_SROM8_5GL_PA_1 … #define SSB_SROM8_5GL_PA_2 … #define SSB_SROM8_5GH_PA_0 … #define SSB_SROM8_5GH_PA_1 … #define SSB_SROM8_5GH_PA_2 … /* TODO: Make it deprecated */ #define SSB_SPROM8_MAXP_BG … #define SSB_SPROM8_MAXP_BG_MASK … #define SSB_SPROM8_ITSSI_BG … #define SSB_SPROM8_ITSSI_BG_SHIFT … #define SSB_SPROM8_PA0B0 … #define SSB_SPROM8_PA0B1 … #define SSB_SPROM8_PA0B2 … #define SSB_SPROM8_MAXP_A … #define SSB_SPROM8_MAXP_A_MASK … #define SSB_SPROM8_ITSSI_A … #define SSB_SPROM8_ITSSI_A_SHIFT … #define SSB_SPROM8_MAXP_AHL … #define SSB_SPROM8_MAXP_AH_MASK … #define SSB_SPROM8_MAXP_AL_MASK … #define SSB_SPROM8_MAXP_AL_SHIFT … #define SSB_SPROM8_PA1B0 … #define SSB_SPROM8_PA1B1 … #define SSB_SPROM8_PA1B2 … #define SSB_SPROM8_PA1LOB0 … #define SSB_SPROM8_PA1LOB1 … #define SSB_SPROM8_PA1LOB2 … #define SSB_SPROM8_PA1HIB0 … #define SSB_SPROM8_PA1HIB1 … #define SSB_SPROM8_PA1HIB2 … #define SSB_SPROM8_CCK2GPO … #define SSB_SPROM8_OFDM2GPO … #define SSB_SPROM8_OFDM5GPO … #define SSB_SPROM8_OFDM5GLPO … #define SSB_SPROM8_OFDM5GHPO … #define SSB_SPROM8_2G_MCSPO … #define SSB_SPROM8_5G_MCSPO … #define SSB_SPROM8_5GL_MCSPO … #define SSB_SPROM8_5GH_MCSPO … #define SSB_SPROM8_CDDPO … #define SSB_SPROM8_STBCPO … #define SSB_SPROM8_BW40PO … #define SSB_SPROM8_BWDUPPO … /* Values for boardflags_lo read from SPROM */ #define SSB_BFL_BTCOEXIST … #define SSB_BFL_PACTRL … #define SSB_BFL_AIRLINEMODE … #define SSB_BFL_RSSI … #define SSB_BFL_ENETSPI … #define SSB_BFL_XTAL_NOSLOW … #define SSB_BFL_CCKHIPWR … #define SSB_BFL_ENETADM … #define SSB_BFL_ENETVLAN … #define SSB_BFL_AFTERBURNER … #define SSB_BFL_NOPCI … #define SSB_BFL_FEM … #define SSB_BFL_EXTLNA … #define SSB_BFL_HGPA … #define SSB_BFL_BTCMOD … #define SSB_BFL_ALTIQ … /* Values for boardflags_hi read from SPROM */ #define SSB_BFH_NOPA … #define SSB_BFH_RSSIINV … #define SSB_BFH_PAREF … #define SSB_BFH_3TSWITCH … #define SSB_BFH_PHASESHIFT … #define SSB_BFH_BUCKBOOST … #define SSB_BFH_FEM_BT … /* Values for boardflags2_lo read from SPROM */ #define SSB_BFL2_RXBB_INT_REG_DIS … #define SSB_BFL2_APLL_WAR … #define SSB_BFL2_TXPWRCTRL_EN … #define SSB_BFL2_2X4_DIV … #define SSB_BFL2_5G_PWRGAIN … #define SSB_BFL2_PCIEWAR_OVR … #define SSB_BFL2_CAESERS_BRD … #define SSB_BFL2_BTC3WIRE … #define SSB_BFL2_SKWRKFEM_BRD … #define SSB_BFL2_SPUR_WAR … #define SSB_BFL2_GPLL_WAR … /* Values for SSB_SPROM1_BINF_CCODE */ enum { … }; /* Address-Match values and masks (SSB_ADMATCHxxx) */ #define SSB_ADM_TYPE … #define SSB_ADM_TYPE0 … #define SSB_ADM_TYPE1 … #define SSB_ADM_TYPE2 … #define SSB_ADM_AD64 … #define SSB_ADM_SZ0 … #define SSB_ADM_SZ0_SHIFT … #define SSB_ADM_SZ1 … #define SSB_ADM_SZ1_SHIFT … #define SSB_ADM_SZ2 … #define SSB_ADM_SZ2_SHIFT … #define SSB_ADM_EN … #define SSB_ADM_NEG … #define SSB_ADM_BASE0 … #define SSB_ADM_BASE0_SHIFT … #define SSB_ADM_BASE1 … #define SSB_ADM_BASE1_SHIFT … #define SSB_ADM_BASE2 … #define SSB_ADM_BASE2_SHIFT … #endif /* LINUX_SSB_REGS_H_ */
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