/* * Copyright (C) 2020 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _mmhub_2_3_0_OFFSET_HEADER #define _mmhub_2_3_0_OFFSET_HEADER // addressBlock: mmhub_dagbdec // base address: 0x68000 #define mmDAGB0_RDCLI0 … #define mmDAGB0_RDCLI0_BASE_IDX … #define mmDAGB0_RDCLI1 … #define mmDAGB0_RDCLI1_BASE_IDX … #define mmDAGB0_RDCLI2 … #define mmDAGB0_RDCLI2_BASE_IDX … #define mmDAGB0_RDCLI3 … #define mmDAGB0_RDCLI3_BASE_IDX … #define mmDAGB0_RDCLI4 … #define mmDAGB0_RDCLI4_BASE_IDX … #define mmDAGB0_RDCLI5 … #define mmDAGB0_RDCLI5_BASE_IDX … #define mmDAGB0_RDCLI6 … #define mmDAGB0_RDCLI6_BASE_IDX … #define mmDAGB0_RDCLI7 … #define mmDAGB0_RDCLI7_BASE_IDX … #define mmDAGB0_RDCLI8 … #define mmDAGB0_RDCLI8_BASE_IDX … #define mmDAGB0_RDCLI9 … #define mmDAGB0_RDCLI9_BASE_IDX … #define mmDAGB0_RDCLI10 … #define mmDAGB0_RDCLI10_BASE_IDX … #define mmDAGB0_RDCLI11 … #define mmDAGB0_RDCLI11_BASE_IDX … #define mmDAGB0_RDCLI12 … #define mmDAGB0_RDCLI12_BASE_IDX … #define mmDAGB0_RDCLI13 … #define mmDAGB0_RDCLI13_BASE_IDX … #define mmDAGB0_RDCLI14 … #define mmDAGB0_RDCLI14_BASE_IDX … #define mmDAGB0_RDCLI15 … #define mmDAGB0_RDCLI15_BASE_IDX … #define mmDAGB0_RDCLI16 … #define mmDAGB0_RDCLI16_BASE_IDX … #define mmDAGB0_RDCLI17 … #define mmDAGB0_RDCLI17_BASE_IDX … #define mmDAGB0_RDCLI18 … #define mmDAGB0_RDCLI18_BASE_IDX … #define mmDAGB0_RDCLI19 … #define mmDAGB0_RDCLI19_BASE_IDX … #define mmDAGB0_RDCLI20 … #define mmDAGB0_RDCLI20_BASE_IDX … #define mmDAGB0_RDCLI21 … #define mmDAGB0_RDCLI21_BASE_IDX … #define mmDAGB0_RDCLI22 … #define mmDAGB0_RDCLI22_BASE_IDX … #define mmDAGB0_RDCLI23 … #define mmDAGB0_RDCLI23_BASE_IDX … #define mmDAGB0_RDCLI24 … #define mmDAGB0_RDCLI24_BASE_IDX … #define mmDAGB0_RDCLI25 … #define mmDAGB0_RDCLI25_BASE_IDX … #define mmDAGB0_RDCLI26 … #define mmDAGB0_RDCLI26_BASE_IDX … #define mmDAGB0_RDCLI27 … #define mmDAGB0_RDCLI27_BASE_IDX … #define mmDAGB0_RDCLI28 … #define mmDAGB0_RDCLI28_BASE_IDX … #define mmDAGB0_RDCLI29 … #define mmDAGB0_RDCLI29_BASE_IDX … #define mmDAGB0_RDCLI30 … #define mmDAGB0_RDCLI30_BASE_IDX … #define mmDAGB0_RD_CNTL … #define mmDAGB0_RD_CNTL_BASE_IDX … #define mmDAGB0_RD_GMI_CNTL … #define mmDAGB0_RD_GMI_CNTL_BASE_IDX … #define mmDAGB0_RD_ADDR_DAGB … #define mmDAGB0_RD_ADDR_DAGB_BASE_IDX … #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST … #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB0_RD_CGTT_CLK_CTRL … #define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL … #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL … #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 … #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 … #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2 … #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX … #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 … #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX … #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST3 … #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST3_BASE_IDX … #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3 … #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3_BASE_IDX … #define mmDAGB0_RD_VC0_CNTL … #define mmDAGB0_RD_VC0_CNTL_BASE_IDX … #define mmDAGB0_RD_VC1_CNTL … #define mmDAGB0_RD_VC1_CNTL_BASE_IDX … #define mmDAGB0_RD_VC2_CNTL … #define mmDAGB0_RD_VC2_CNTL_BASE_IDX … #define mmDAGB0_RD_VC3_CNTL … #define mmDAGB0_RD_VC3_CNTL_BASE_IDX … #define mmDAGB0_RD_VC4_CNTL … #define mmDAGB0_RD_VC4_CNTL_BASE_IDX … #define mmDAGB0_RD_VC5_CNTL … #define mmDAGB0_RD_VC5_CNTL_BASE_IDX … #define mmDAGB0_RD_VC6_CNTL … #define mmDAGB0_RD_VC6_CNTL_BASE_IDX … #define mmDAGB0_RD_VC7_CNTL … #define mmDAGB0_RD_VC7_CNTL_BASE_IDX … #define mmDAGB0_RD_CNTL_MISC … #define mmDAGB0_RD_CNTL_MISC_BASE_IDX … #define mmDAGB0_RD_TLB_CREDIT … #define mmDAGB0_RD_TLB_CREDIT_BASE_IDX … #define mmDAGB0_RD_RDRET_CREDIT_CNTL … #define mmDAGB0_RD_RDRET_CREDIT_CNTL_BASE_IDX … #define mmDAGB0_RD_RDRET_CREDIT_CNTL2 … #define mmDAGB0_RD_RDRET_CREDIT_CNTL2_BASE_IDX … #define mmDAGB0_RDCLI_ASK_PENDING … #define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX … #define mmDAGB0_RDCLI_GO_PENDING … #define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX … #define mmDAGB0_RDCLI_GBLSEND_PENDING … #define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB0_RDCLI_TLB_PENDING … #define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX … #define mmDAGB0_RDCLI_OARB_PENDING … #define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX … #define mmDAGB0_RDCLI_OSD_PENDING … #define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX … #define mmDAGB0_WRCLI0 … #define mmDAGB0_WRCLI0_BASE_IDX … #define mmDAGB0_WRCLI1 … #define mmDAGB0_WRCLI1_BASE_IDX … #define mmDAGB0_WRCLI2 … #define mmDAGB0_WRCLI2_BASE_IDX … #define mmDAGB0_WRCLI3 … #define mmDAGB0_WRCLI3_BASE_IDX … #define mmDAGB0_WRCLI4 … #define mmDAGB0_WRCLI4_BASE_IDX … #define mmDAGB0_WRCLI5 … #define mmDAGB0_WRCLI5_BASE_IDX … #define mmDAGB0_WRCLI6 … #define mmDAGB0_WRCLI6_BASE_IDX … #define mmDAGB0_WRCLI7 … #define mmDAGB0_WRCLI7_BASE_IDX … #define mmDAGB0_WRCLI8 … #define mmDAGB0_WRCLI8_BASE_IDX … #define mmDAGB0_WRCLI9 … #define mmDAGB0_WRCLI9_BASE_IDX … #define mmDAGB0_WRCLI10 … #define mmDAGB0_WRCLI10_BASE_IDX … #define mmDAGB0_WRCLI11 … #define mmDAGB0_WRCLI11_BASE_IDX … #define mmDAGB0_WRCLI12 … #define mmDAGB0_WRCLI12_BASE_IDX … #define mmDAGB0_WRCLI13 … #define mmDAGB0_WRCLI13_BASE_IDX … #define mmDAGB0_WRCLI14 … #define mmDAGB0_WRCLI14_BASE_IDX … #define mmDAGB0_WRCLI15 … #define mmDAGB0_WRCLI15_BASE_IDX … #define mmDAGB0_WRCLI16 … #define mmDAGB0_WRCLI16_BASE_IDX … #define mmDAGB0_WRCLI17 … #define mmDAGB0_WRCLI17_BASE_IDX … #define mmDAGB0_WRCLI18 … #define mmDAGB0_WRCLI18_BASE_IDX … #define mmDAGB0_WRCLI19 … #define mmDAGB0_WRCLI19_BASE_IDX … #define mmDAGB0_WRCLI20 … #define mmDAGB0_WRCLI20_BASE_IDX … #define mmDAGB0_WRCLI21 … #define mmDAGB0_WRCLI21_BASE_IDX … #define mmDAGB0_WRCLI22 … #define mmDAGB0_WRCLI22_BASE_IDX … #define mmDAGB0_WRCLI23 … #define mmDAGB0_WRCLI23_BASE_IDX … #define mmDAGB0_WRCLI24 … #define mmDAGB0_WRCLI24_BASE_IDX … #define mmDAGB0_WRCLI25 … #define mmDAGB0_WRCLI25_BASE_IDX … #define mmDAGB0_WRCLI26 … #define mmDAGB0_WRCLI26_BASE_IDX … #define mmDAGB0_WRCLI27 … #define mmDAGB0_WRCLI27_BASE_IDX … #define mmDAGB0_WRCLI28 … #define mmDAGB0_WRCLI28_BASE_IDX … #define mmDAGB0_WRCLI29 … #define mmDAGB0_WRCLI29_BASE_IDX … #define mmDAGB0_WRCLI30 … #define mmDAGB0_WRCLI30_BASE_IDX … #define mmDAGB0_WR_CNTL … #define mmDAGB0_WR_CNTL_BASE_IDX … #define mmDAGB0_WR_GMI_CNTL … #define mmDAGB0_WR_GMI_CNTL_BASE_IDX … #define mmDAGB0_WR_ADDR_DAGB … #define mmDAGB0_WR_ADDR_DAGB_BASE_IDX … #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST … #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER … #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define mmDAGB0_WR_CGTT_CLK_CTRL … #define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL … #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL … #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX … #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 … #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 … #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 … #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 … #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2 … #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX … #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 … #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX … #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST3 … #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST3_BASE_IDX … #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3 … #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3_BASE_IDX … #define mmDAGB0_WR_DATA_DAGB … #define mmDAGB0_WR_DATA_DAGB_BASE_IDX … #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 … #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX … #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 … #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX … #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 … #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX … #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 … #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX … #define mmDAGB0_WR_DATA_DAGB_MAX_BURST2 … #define mmDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX … #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2 … #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX … #define mmDAGB0_WR_DATA_DAGB_MAX_BURST3 … #define mmDAGB0_WR_DATA_DAGB_MAX_BURST3_BASE_IDX … #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3 … #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3_BASE_IDX … #define mmDAGB0_WR_VC0_CNTL … #define mmDAGB0_WR_VC0_CNTL_BASE_IDX … #define mmDAGB0_WR_VC1_CNTL … #define mmDAGB0_WR_VC1_CNTL_BASE_IDX … #define mmDAGB0_WR_VC2_CNTL … #define mmDAGB0_WR_VC2_CNTL_BASE_IDX … #define mmDAGB0_WR_VC3_CNTL … #define mmDAGB0_WR_VC3_CNTL_BASE_IDX … #define mmDAGB0_WR_VC4_CNTL … #define mmDAGB0_WR_VC4_CNTL_BASE_IDX … #define mmDAGB0_WR_VC5_CNTL … #define mmDAGB0_WR_VC5_CNTL_BASE_IDX … #define mmDAGB0_WR_VC6_CNTL … #define mmDAGB0_WR_VC6_CNTL_BASE_IDX … #define mmDAGB0_WR_VC7_CNTL … #define mmDAGB0_WR_VC7_CNTL_BASE_IDX … #define mmDAGB0_WR_CNTL_MISC … #define mmDAGB0_WR_CNTL_MISC_BASE_IDX … #define mmDAGB0_WR_TLB_CREDIT … #define mmDAGB0_WR_TLB_CREDIT_BASE_IDX … #define mmDAGB0_WR_DATA_CREDIT … #define mmDAGB0_WR_DATA_CREDIT_BASE_IDX … #define mmDAGB0_WR_MISC_CREDIT … #define mmDAGB0_WR_MISC_CREDIT_BASE_IDX … #define mmDAGB0_WR_OSD_CREDIT_CNTL1 … #define mmDAGB0_WR_OSD_CREDIT_CNTL1_BASE_IDX … #define mmDAGB0_WR_OSD_CREDIT_CNTL2 … #define mmDAGB0_WR_OSD_CREDIT_CNTL2_BASE_IDX … #define mmDAGB0_WR_DATA_FIFO_CREDIT_CNTL1 … #define mmDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX … #define mmDAGB0_WR_DATA_FIFO_CREDIT_CNTL2 … #define mmDAGB0_WR_DATA_FIFO_CREDIT_CNTL2_BASE_IDX … #define mmDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 … #define mmDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX … #define mmDAGB0_WRCLI_ASK_PENDING … #define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_GO_PENDING … #define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_GBLSEND_PENDING … #define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_TLB_PENDING … #define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_OARB_PENDING … #define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_OSD_PENDING … #define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_DBUS_ASK_PENDING … #define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_DBUS_GO_PENDING … #define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX … #define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE … #define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX … #define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE … #define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX … #define mmDAGB0_DAGB_DLY … #define mmDAGB0_DAGB_DLY_BASE_IDX … #define mmDAGB0_CNTL_MISC … #define mmDAGB0_CNTL_MISC_BASE_IDX … #define mmDAGB0_CNTL_MISC2 … #define mmDAGB0_CNTL_MISC2_BASE_IDX … #define mmDAGB0_FIFO_EMPTY … #define mmDAGB0_FIFO_EMPTY_BASE_IDX … #define mmDAGB0_FIFO_FULL … #define mmDAGB0_FIFO_FULL_BASE_IDX … #define mmDAGB0_WR_CREDITS_FULL … #define mmDAGB0_WR_CREDITS_FULL_BASE_IDX … #define mmDAGB0_RD_CREDITS_FULL … #define mmDAGB0_RD_CREDITS_FULL_BASE_IDX … #define mmDAGB0_PERFCOUNTER_LO … #define mmDAGB0_PERFCOUNTER_LO_BASE_IDX … #define mmDAGB0_PERFCOUNTER_HI … #define mmDAGB0_PERFCOUNTER_HI_BASE_IDX … #define mmDAGB0_PERFCOUNTER0_CFG … #define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX … #define mmDAGB0_PERFCOUNTER1_CFG … #define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX … #define mmDAGB0_PERFCOUNTER2_CFG … #define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX … #define mmDAGB0_PERFCOUNTER_RSLT_CNTL … #define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmDAGB0_RESERVE0 … #define mmDAGB0_RESERVE0_BASE_IDX … #define mmDAGB0_RESERVE1 … #define mmDAGB0_RESERVE1_BASE_IDX … #define mmDAGB0_RESERVE2 … #define mmDAGB0_RESERVE2_BASE_IDX … #define mmDAGB0_RESERVE3 … #define mmDAGB0_RESERVE3_BASE_IDX … #define mmDAGB0_RESERVE4 … #define mmDAGB0_RESERVE4_BASE_IDX … #define mmDAGB0_RESERVE5 … #define mmDAGB0_RESERVE5_BASE_IDX … #define mmDAGB0_RESERVE6 … #define mmDAGB0_RESERVE6_BASE_IDX … #define mmDAGB0_RESERVE7 … #define mmDAGB0_RESERVE7_BASE_IDX … #define mmDAGB0_RESERVE8 … #define mmDAGB0_RESERVE8_BASE_IDX … #define mmDAGB0_RESERVE9 … #define mmDAGB0_RESERVE9_BASE_IDX … // addressBlock: mmhub_mmea_mmeadec0 // base address: 0x68400 #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 … #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 … #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 … #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 … #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA0_DRAM_RD_GRP2VC_MAP … #define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX … #define mmMMEA0_DRAM_WR_GRP2VC_MAP … #define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX … #define mmMMEA0_DRAM_RD_LAZY … #define mmMMEA0_DRAM_RD_LAZY_BASE_IDX … #define mmMMEA0_DRAM_WR_LAZY … #define mmMMEA0_DRAM_WR_LAZY_BASE_IDX … #define mmMMEA0_DRAM_RD_CAM_CNTL … #define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX … #define mmMMEA0_DRAM_WR_CAM_CNTL … #define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX … #define mmMMEA0_DRAM_PAGE_BURST … #define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_AGE … #define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_AGE … #define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_QUEUING … #define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_QUEUING … #define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_FIXED … #define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_FIXED … #define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_URGENCY … #define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_URGENCY … #define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 … #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 … #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 … #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 … #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 … #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 … #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA0_ADDRNORM_BASE_ADDR0 … #define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX … #define mmMMEA0_ADDRNORM_LIMIT_ADDR0 … #define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX … #define mmMMEA0_ADDRNORM_BASE_ADDR1 … #define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX … #define mmMMEA0_ADDRNORM_LIMIT_ADDR1 … #define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX … #define mmMMEA0_ADDRNORM_OFFSET_ADDR1 … #define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX … #define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL … #define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX … #define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG … #define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX … #define mmMMEA0_ADDRDEC_BANK_CFG … #define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX … #define mmMMEA0_ADDRDEC_MISC_CFG … #define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 … #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE … #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0 … #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0 … #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1 … #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1 … #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 … #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 … #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 … #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 … #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 … #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 … #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 … #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 … #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 … #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01 … #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23 … #define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 … #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 … #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 … #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 … #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_RM_SEL_CS01 … #define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC0_RM_SEL_CS23 … #define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC0_RM_SEL_CS1 … #define mmMMEA0_ADDRDEC0_RM_SEL_CS1_BASE_IDX … #define mmMMEA0_ADDRDEC0_RM_SEL_CS3 … #define mmMMEA0_ADDRDEC0_RM_SEL_CS3_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 … #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 … #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 … #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 … #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 … #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 … #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 … #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 … #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 … #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01 … #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23 … #define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 … #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 … #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 … #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 … #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_RM_SEL_CS01 … #define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX … #define mmMMEA0_ADDRDEC1_RM_SEL_CS23 … #define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX … #define mmMMEA0_ADDRDEC1_RM_SEL_CS1 … #define mmMMEA0_ADDRDEC1_RM_SEL_CS1_BASE_IDX … #define mmMMEA0_ADDRDEC1_RM_SEL_CS3 … #define mmMMEA0_ADDRDEC1_RM_SEL_CS3_BASE_IDX … #define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL … #define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ0 … #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ0_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ1 … #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ1_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ2 … #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ2_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ3 … #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ3_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ4 … #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ4_BASE_IDX … #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ5 … #define mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ5_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS1 … #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS1_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS3 … #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS3_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS1 … #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS1_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS3 … #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS3_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS1 … #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS1_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS3 … #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS3_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS1 … #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS1_BASE_IDX … #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS3 … #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS3_BASE_IDX … #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS1 … #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS1_BASE_IDX … #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS3 … #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS3_BASE_IDX … #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS1 … #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS1_BASE_IDX … #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS3 … #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS3_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS1 … #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS1_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS3 … #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS3_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS1 … #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS1_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS3 … #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS3_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS1 … #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS1_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS3 … #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS3_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS1 … #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS1_BASE_IDX … #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS3 … #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS3_BASE_IDX … #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS1 … #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS1_BASE_IDX … #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS3 … #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS3_BASE_IDX … #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS1 … #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS1_BASE_IDX … #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS3 … #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS3_BASE_IDX … #define mmMMEA0_ADDRNORMDRAM_MASKING … #define mmMMEA0_ADDRNORMDRAM_MASKING_BASE_IDX … #define mmMMEA0_IO_RD_CLI2GRP_MAP0 … #define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA0_IO_RD_CLI2GRP_MAP1 … #define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA0_IO_WR_CLI2GRP_MAP0 … #define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX … #define mmMMEA0_IO_WR_CLI2GRP_MAP1 … #define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX … #define mmMMEA0_IO_RD_COMBINE_FLUSH … #define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX … #define mmMMEA0_IO_WR_COMBINE_FLUSH … #define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX … #define mmMMEA0_IO_GROUP_BURST … #define mmMMEA0_IO_GROUP_BURST_BASE_IDX … #define mmMMEA0_IO_RD_PRI_AGE … #define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX … #define mmMMEA0_IO_WR_PRI_AGE … #define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX … #define mmMMEA0_IO_RD_PRI_QUEUING … #define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX … #define mmMMEA0_IO_WR_PRI_QUEUING … #define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX … #define mmMMEA0_IO_RD_PRI_FIXED … #define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX … #define mmMMEA0_IO_WR_PRI_FIXED … #define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX … #define mmMMEA0_IO_RD_PRI_URGENCY … #define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX … #define mmMMEA0_IO_WR_PRI_URGENCY … #define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX … #define mmMMEA0_IO_RD_PRI_URGENCY_MASKING … #define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA0_IO_WR_PRI_URGENCY_MASKING … #define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX … #define mmMMEA0_IO_RD_PRI_QUANT_PRI1 … #define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA0_IO_RD_PRI_QUANT_PRI2 … #define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA0_IO_RD_PRI_QUANT_PRI3 … #define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA0_IO_WR_PRI_QUANT_PRI1 … #define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX … #define mmMMEA0_IO_WR_PRI_QUANT_PRI2 … #define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX … #define mmMMEA0_IO_WR_PRI_QUANT_PRI3 … #define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX … #define mmMMEA0_SDP_ARB_DRAM … #define mmMMEA0_SDP_ARB_DRAM_BASE_IDX … #define mmMMEA0_SDP_ARB_FINAL … #define mmMMEA0_SDP_ARB_FINAL_BASE_IDX … #define mmMMEA0_SDP_DRAM_PRIORITY … #define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX … #define mmMMEA0_SDP_IO_PRIORITY … #define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX … #define mmMMEA0_SDP_CREDITS … #define mmMMEA0_SDP_CREDITS_BASE_IDX … #define mmMMEA0_SDP_TAG_RESERVE0 … #define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX … #define mmMMEA0_SDP_TAG_RESERVE1 … #define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX … #define mmMMEA0_SDP_VCC_RESERVE0 … #define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX … #define mmMMEA0_SDP_VCC_RESERVE1 … #define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX … #define mmMMEA0_SDP_VCD_RESERVE0 … #define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX … #define mmMMEA0_SDP_VCD_RESERVE1 … #define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX … #define mmMMEA0_SDP_REQ_CNTL … #define mmMMEA0_SDP_REQ_CNTL_BASE_IDX … #define mmMMEA0_MISC … #define mmMMEA0_MISC_BASE_IDX … #define mmMMEA0_LATENCY_SAMPLING … #define mmMMEA0_LATENCY_SAMPLING_BASE_IDX … #define mmMMEA0_PERFCOUNTER_LO … #define mmMMEA0_PERFCOUNTER_LO_BASE_IDX … #define mmMMEA0_PERFCOUNTER_HI … #define mmMMEA0_PERFCOUNTER_HI_BASE_IDX … #define mmMMEA0_PERFCOUNTER0_CFG … #define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX … #define mmMMEA0_PERFCOUNTER1_CFG … #define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX … #define mmMMEA0_PERFCOUNTER_RSLT_CNTL … #define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmMMEA0_EDC_CNT … #define mmMMEA0_EDC_CNT_BASE_IDX … #define mmMMEA0_EDC_CNT2 … #define mmMMEA0_EDC_CNT2_BASE_IDX … #define mmMMEA0_DSM_CNTL … #define mmMMEA0_DSM_CNTL_BASE_IDX … #define mmMMEA0_DSM_CNTLA … #define mmMMEA0_DSM_CNTLA_BASE_IDX … #define mmMMEA0_DSM_CNTLB … #define mmMMEA0_DSM_CNTLB_BASE_IDX … #define mmMMEA0_DSM_CNTL2 … #define mmMMEA0_DSM_CNTL2_BASE_IDX … #define mmMMEA0_DSM_CNTL2A … #define mmMMEA0_DSM_CNTL2A_BASE_IDX … #define mmMMEA0_DSM_CNTL2B … #define mmMMEA0_DSM_CNTL2B_BASE_IDX … #define mmMMEA0_CGTT_CLK_CTRL … #define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX … #define mmMMEA0_EDC_MODE … #define mmMMEA0_EDC_MODE_BASE_IDX … #define mmMMEA0_ERR_STATUS … #define mmMMEA0_ERR_STATUS_BASE_IDX … #define mmMMEA0_MISC2 … #define mmMMEA0_MISC2_BASE_IDX … #define mmMMEA0_ADDRDEC_SELECT … #define mmMMEA0_ADDRDEC_SELECT_BASE_IDX … #define mmMMEA0_EDC_CNT3 … #define mmMMEA0_EDC_CNT3_BASE_IDX … #define mmMMEA0_SDP_PRIORITY_OVERRIDE … #define mmMMEA0_SDP_PRIORITY_OVERRIDE_BASE_IDX … #define mmMMEA0_MISC_AON … #define mmMMEA0_MISC_AON_BASE_IDX … // addressBlock: mmhub_pctldec // base address: 0x68e00 #define mmPCTL_CTRL … #define mmPCTL_CTRL_BASE_IDX … #define mmPCTL_MMHUB_DEEPSLEEP_IB … #define mmPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX … #define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE … #define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX … #define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB … #define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX … #define mmPCTL_PG_IGNORE_DEEPSLEEP … #define mmPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX … #define mmPCTL_PG_IGNORE_DEEPSLEEP_IB … #define mmPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX … #define mmPCTL_SLICE0_CFG_DAGB_WRBUSY … #define mmPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX … #define mmPCTL_SLICE0_CFG_DAGB_RDBUSY … #define mmPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX … #define mmPCTL_SLICE0_CFG_DS_ALLOW … #define mmPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX … #define mmPCTL_SLICE0_CFG_DS_ALLOW_IB … #define mmPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX … #define mmPCTL_SLICE1_CFG_DAGB_WRBUSY … #define mmPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX … #define mmPCTL_SLICE1_CFG_DAGB_RDBUSY … #define mmPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX … #define mmPCTL_SLICE1_CFG_DS_ALLOW … #define mmPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX … #define mmPCTL_SLICE1_CFG_DS_ALLOW_IB … #define mmPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX … #define mmPCTL_UTCL2_MISC … #define mmPCTL_UTCL2_MISC_BASE_IDX … #define mmPCTL_SLICE0_MISC … #define mmPCTL_SLICE0_MISC_BASE_IDX … #define mmPCTL_SLICE1_MISC … #define mmPCTL_SLICE1_MISC_BASE_IDX … #define mmPCTL_RENG_CTRL … #define mmPCTL_RENG_CTRL_BASE_IDX … #define mmPCTL_UTCL2_RENG_EXECUTE … #define mmPCTL_UTCL2_RENG_EXECUTE_BASE_IDX … #define mmPCTL_SLICE0_RENG_EXECUTE … #define mmPCTL_SLICE0_RENG_EXECUTE_BASE_IDX … #define mmPCTL_SLICE1_RENG_EXECUTE … #define mmPCTL_SLICE1_RENG_EXECUTE_BASE_IDX … #define mmPCTL_UTCL2_RENG_RAM_INDEX … #define mmPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX … #define mmPCTL_UTCL2_RENG_RAM_DATA … #define mmPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX … #define mmPCTL_SLICE0_RENG_RAM_INDEX … #define mmPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX … #define mmPCTL_SLICE0_RENG_RAM_DATA … #define mmPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX … #define mmPCTL_SLICE1_RENG_RAM_INDEX … #define mmPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX … #define mmPCTL_SLICE1_RENG_RAM_DATA … #define mmPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX … #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 … #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 … #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 … #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 … #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX … #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 … #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX … #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 … #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX … #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 … #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 … #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 … #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 … #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX … #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 … #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX … #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 … #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX … #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 … #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 … #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 … #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 … #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX … #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 … #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX … #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 … #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX … #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … #define mmPCTL_STATUS … #define mmPCTL_STATUS_BASE_IDX … #define mmPCTL_PERFCOUNTER_LO … #define mmPCTL_PERFCOUNTER_LO_BASE_IDX … #define mmPCTL_PERFCOUNTER_HI … #define mmPCTL_PERFCOUNTER_HI_BASE_IDX … #define mmPCTL_PERFCOUNTER0_CFG … #define mmPCTL_PERFCOUNTER0_CFG_BASE_IDX … #define mmPCTL_PERFCOUNTER1_CFG … #define mmPCTL_PERFCOUNTER1_CFG_BASE_IDX … #define mmPCTL_PERFCOUNTER_RSLT_CNTL … #define mmPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmPCTL_RESERVED_0 … #define mmPCTL_RESERVED_0_BASE_IDX … #define mmPCTL_RESERVED_1 … #define mmPCTL_RESERVED_1_BASE_IDX … #define mmPCTL_RESERVED_2 … #define mmPCTL_RESERVED_2_BASE_IDX … #define mmPCTL_RESERVED_3 … #define mmPCTL_RESERVED_3_BASE_IDX … // addressBlock: mmhub_l1tlb_mmutcl1pfdec // base address: 0x69600 #define mmMMMC_VM_MX_L1_TLB0_STATUS … #define mmMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX … #define mmMMMC_VM_MX_L1_TLB1_STATUS … #define mmMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX … #define mmMMMC_VM_MX_L1_TLB2_STATUS … #define mmMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX … #define mmMMMC_VM_MX_L1_TLB3_STATUS … #define mmMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX … #define mmMMMC_VM_MX_L1_TLB4_STATUS … #define mmMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX … #define mmMMMC_VM_MX_L1_TLB5_STATUS … #define mmMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX … #define mmMMMC_VM_MX_L1_TLB6_STATUS … #define mmMMMC_VM_MX_L1_TLB6_STATUS_BASE_IDX … #define mmMMMC_VM_MX_L1_TLB7_STATUS … #define mmMMMC_VM_MX_L1_TLB7_STATUS_BASE_IDX … // addressBlock: mmhub_l1tlb_mmutcl1pldec // base address: 0x69670 #define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG … #define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX … #define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG … #define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX … #define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG … #define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX … #define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG … #define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX … #define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL … #define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: mmhub_l1tlb_mmutcl1prdec // base address: 0x69690 #define mmMMMC_VM_MX_L1_PERFCOUNTER_LO … #define mmMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX … #define mmMMMC_VM_MX_L1_PERFCOUNTER_HI … #define mmMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX … // addressBlock: mmhub_l1tlb_mmvmtlspfdec // base address: 0x696c0 #define mmMMMC_VM_MX_L1_TLS0_CNTL … #define mmMMMC_VM_MX_L1_TLS0_CNTL_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL0 … #define mmMMMC_VM_MX_L1_TLS0_CNTL0_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL1 … #define mmMMMC_VM_MX_L1_TLS0_CNTL1_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL2 … #define mmMMMC_VM_MX_L1_TLS0_CNTL2_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL3 … #define mmMMMC_VM_MX_L1_TLS0_CNTL3_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL4 … #define mmMMMC_VM_MX_L1_TLS0_CNTL4_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL5 … #define mmMMMC_VM_MX_L1_TLS0_CNTL5_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL6 … #define mmMMMC_VM_MX_L1_TLS0_CNTL6_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL7 … #define mmMMMC_VM_MX_L1_TLS0_CNTL7_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL8 … #define mmMMMC_VM_MX_L1_TLS0_CNTL8_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL9 … #define mmMMMC_VM_MX_L1_TLS0_CNTL9_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL10 … #define mmMMMC_VM_MX_L1_TLS0_CNTL10_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL11 … #define mmMMMC_VM_MX_L1_TLS0_CNTL11_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL12 … #define mmMMMC_VM_MX_L1_TLS0_CNTL12_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL13 … #define mmMMMC_VM_MX_L1_TLS0_CNTL13_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL14 … #define mmMMMC_VM_MX_L1_TLS0_CNTL14_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL15 … #define mmMMMC_VM_MX_L1_TLS0_CNTL15_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL16 … #define mmMMMC_VM_MX_L1_TLS0_CNTL16_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL17 … #define mmMMMC_VM_MX_L1_TLS0_CNTL17_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL18 … #define mmMMMC_VM_MX_L1_TLS0_CNTL18_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL19 … #define mmMMMC_VM_MX_L1_TLS0_CNTL19_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL20 … #define mmMMMC_VM_MX_L1_TLS0_CNTL20_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL21 … #define mmMMMC_VM_MX_L1_TLS0_CNTL21_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL22 … #define mmMMMC_VM_MX_L1_TLS0_CNTL22_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL23 … #define mmMMMC_VM_MX_L1_TLS0_CNTL23_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL24 … #define mmMMMC_VM_MX_L1_TLS0_CNTL24_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL25 … #define mmMMMC_VM_MX_L1_TLS0_CNTL25_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL26 … #define mmMMMC_VM_MX_L1_TLS0_CNTL26_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL27 … #define mmMMMC_VM_MX_L1_TLS0_CNTL27_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL28 … #define mmMMMC_VM_MX_L1_TLS0_CNTL28_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL29 … #define mmMMMC_VM_MX_L1_TLS0_CNTL29_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL30 … #define mmMMMC_VM_MX_L1_TLS0_CNTL30_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL31 … #define mmMMMC_VM_MX_L1_TLS0_CNTL31_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL32 … #define mmMMMC_VM_MX_L1_TLS0_CNTL32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL33 … #define mmMMMC_VM_MX_L1_TLS0_CNTL33_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL34 … #define mmMMMC_VM_MX_L1_TLS0_CNTL34_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL35 … #define mmMMMC_VM_MX_L1_TLS0_CNTL35_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL36 … #define mmMMMC_VM_MX_L1_TLS0_CNTL36_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_CNTL37 … #define mmMMMC_VM_MX_L1_TLS0_CNTL37_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32 … #define mmMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32 … #define mmMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32 … #define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32 … #define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32 … #define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32 … #define mmMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS … #define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32 … #define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32 … #define mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32_BASE_IDX … #define mmMMVM_L2_SAW_CNTL … #define mmMMVM_L2_SAW_CNTL_BASE_IDX … #define mmMMVM_L2_SAW_CNTL2 … #define mmMMVM_L2_SAW_CNTL2_BASE_IDX … #define mmMMVM_L2_SAW_CNTL3 … #define mmMMVM_L2_SAW_CNTL3_BASE_IDX … #define mmMMVM_L2_SAW_CNTL4 … #define mmMMVM_L2_SAW_CNTL4_BASE_IDX … #define mmMMVM_L2_SAW_CONTEXT0_CNTL … #define mmMMVM_L2_SAW_CONTEXT0_CNTL_BASE_IDX … #define mmMMVM_L2_SAW_CONTEXT0_CNTL2 … #define mmMMVM_L2_SAW_CONTEXT0_CNTL2_BASE_IDX … #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 … #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 … #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 … #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 … #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 … #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 … #define mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmMMVM_L2_SAW_CONTEXTS_DISABLE … #define mmMMVM_L2_SAW_CONTEXTS_DISABLE_BASE_IDX … #define mmMMVM_L2_SAW_PIPES_BUSY_LO32 … #define mmMMVM_L2_SAW_PIPES_BUSY_LO32_BASE_IDX … #define mmMMVM_L2_SAW_PIPES_BUSY_HI32 … #define mmMMVM_L2_SAW_PIPES_BUSY_HI32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS … #define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32 … #define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32_BASE_IDX … #define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32 … #define mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmatcl2dec // base address: 0x69b00 #define mmMM_ATC_L2_CNTL … #define mmMM_ATC_L2_CNTL_BASE_IDX … #define mmMM_ATC_L2_CNTL2 … #define mmMM_ATC_L2_CNTL2_BASE_IDX … #define mmMM_ATC_L2_CACHE_DATA0 … #define mmMM_ATC_L2_CACHE_DATA0_BASE_IDX … #define mmMM_ATC_L2_CACHE_DATA1 … #define mmMM_ATC_L2_CACHE_DATA1_BASE_IDX … #define mmMM_ATC_L2_CACHE_DATA2 … #define mmMM_ATC_L2_CACHE_DATA2_BASE_IDX … #define mmMM_ATC_L2_CNTL3 … #define mmMM_ATC_L2_CNTL3_BASE_IDX … #define mmMM_ATC_L2_CNTL4 … #define mmMM_ATC_L2_CNTL4_BASE_IDX … #define mmMM_ATC_L2_CNTL5 … #define mmMM_ATC_L2_CNTL5_BASE_IDX … #define mmMM_ATC_L2_MM_GROUP_RT_CLASSES … #define mmMM_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX … #define mmMM_ATC_L2_STATUS … #define mmMM_ATC_L2_STATUS_BASE_IDX … #define mmMM_ATC_L2_STATUS2 … #define mmMM_ATC_L2_STATUS2_BASE_IDX … #define mmMM_ATC_L2_MISC_CG … #define mmMM_ATC_L2_MISC_CG_BASE_IDX … #define mmMM_ATC_L2_MEM_POWER_LS … #define mmMM_ATC_L2_MEM_POWER_LS_BASE_IDX … #define mmMM_ATC_L2_CGTT_CLK_CTRL … #define mmMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX … #define mmMM_ATC_L2_SDPPORT_CTRL … #define mmMM_ATC_L2_SDPPORT_CTRL_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmvml2pfdec // base address: 0x69c00 #define mmMMVM_L2_CNTL … #define mmMMVM_L2_CNTL_BASE_IDX … #define mmMMVM_L2_CNTL2 … #define mmMMVM_L2_CNTL2_BASE_IDX … #define mmMMVM_L2_CNTL3 … #define mmMMVM_L2_CNTL3_BASE_IDX … #define mmMMVM_L2_STATUS … #define mmMMVM_L2_STATUS_BASE_IDX … #define mmMMVM_DUMMY_PAGE_FAULT_CNTL … #define mmMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX … #define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 … #define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX … #define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 … #define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX … #define mmMMVM_INVALIDATE_CNTL … #define mmMMVM_INVALIDATE_CNTL_BASE_IDX … #define mmMMVM_L2_PROTECTION_FAULT_CNTL … #define mmMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX … #define mmMMVM_L2_PROTECTION_FAULT_CNTL2 … #define mmMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX … #define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3 … #define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX … #define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4 … #define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX … #define mmMMVM_L2_PROTECTION_FAULT_STATUS … #define mmMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX … #define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32 … #define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX … #define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32 … #define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX … #define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 … #define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX … #define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 … #define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX … #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 … #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX … #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 … #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX … #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 … #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX … #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 … #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX … #define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 … #define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX … #define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 … #define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX … #define mmMMVM_L2_CNTL4 … #define mmMMVM_L2_CNTL4_BASE_IDX … #define mmMMVM_L2_MM_GROUP_RT_CLASSES … #define mmMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX … #define mmMMVM_L2_BANK_SELECT_RESERVED_CID … #define mmMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX … #define mmMMVM_L2_BANK_SELECT_RESERVED_CID2 … #define mmMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX … #define mmMMVM_L2_CACHE_PARITY_CNTL … #define mmMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX … #define mmMMVM_L2_IH_LOG_CNTL … #define mmMMVM_L2_IH_LOG_CNTL_BASE_IDX … #define mmMMVM_L2_IH_LOG_BUSY … #define mmMMVM_L2_IH_LOG_BUSY_BASE_IDX … #define mmMMVM_L2_CGTT_CLK_CTRL … #define mmMMVM_L2_CGTT_CLK_CTRL_BASE_IDX … #define mmMMVM_L2_CNTL5 … #define mmMMVM_L2_CNTL5_BASE_IDX … #define mmMMVM_L2_GCR_CNTL … #define mmMMVM_L2_GCR_CNTL_BASE_IDX … #define mmMMVM_L2_CGTT_BUSY_CTRL … #define mmMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX … #define mmMMVM_L2_PTE_CACHE_DUMP_CNTL … #define mmMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX … #define mmMMVM_L2_PTE_CACHE_DUMP_READ … #define mmMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmvml2vcdec // base address: 0x69d00 #define mmMMVM_CONTEXT0_CNTL … #define mmMMVM_CONTEXT0_CNTL_BASE_IDX … #define mmMMVM_CONTEXT1_CNTL … #define mmMMVM_CONTEXT1_CNTL_BASE_IDX … #define mmMMVM_CONTEXT2_CNTL … #define mmMMVM_CONTEXT2_CNTL_BASE_IDX … #define mmMMVM_CONTEXT3_CNTL … #define mmMMVM_CONTEXT3_CNTL_BASE_IDX … #define mmMMVM_CONTEXT4_CNTL … #define mmMMVM_CONTEXT4_CNTL_BASE_IDX … #define mmMMVM_CONTEXT5_CNTL … #define mmMMVM_CONTEXT5_CNTL_BASE_IDX … #define mmMMVM_CONTEXT6_CNTL … #define mmMMVM_CONTEXT6_CNTL_BASE_IDX … #define mmMMVM_CONTEXT7_CNTL … #define mmMMVM_CONTEXT7_CNTL_BASE_IDX … #define mmMMVM_CONTEXT8_CNTL … #define mmMMVM_CONTEXT8_CNTL_BASE_IDX … #define mmMMVM_CONTEXT9_CNTL … #define mmMMVM_CONTEXT9_CNTL_BASE_IDX … #define mmMMVM_CONTEXT10_CNTL … #define mmMMVM_CONTEXT10_CNTL_BASE_IDX … #define mmMMVM_CONTEXT11_CNTL … #define mmMMVM_CONTEXT11_CNTL_BASE_IDX … #define mmMMVM_CONTEXT12_CNTL … #define mmMMVM_CONTEXT12_CNTL_BASE_IDX … #define mmMMVM_CONTEXT13_CNTL … #define mmMMVM_CONTEXT13_CNTL_BASE_IDX … #define mmMMVM_CONTEXT14_CNTL … #define mmMMVM_CONTEXT14_CNTL_BASE_IDX … #define mmMMVM_CONTEXT15_CNTL … #define mmMMVM_CONTEXT15_CNTL_BASE_IDX … #define mmMMVM_CONTEXTS_DISABLE … #define mmMMVM_CONTEXTS_DISABLE_BASE_IDX … #define mmMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define mmMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define mmMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define mmMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define mmMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define mmMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define mmMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define mmMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define mmMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define mmMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define mmMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define mmMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define mmMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define mmMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define mmMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define mmMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define mmMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define mmMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define mmMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define mmMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define mmMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define mmMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define mmMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define mmMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define mmMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define mmMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define mmMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define mmMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define mmMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define mmMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define mmMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define mmMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define mmMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define mmMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmvml2pldec // base address: 0x6a090 #define mmMMMC_VM_L2_PERFCOUNTER0_CFG … #define mmMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX … #define mmMMMC_VM_L2_PERFCOUNTER1_CFG … #define mmMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX … #define mmMMMC_VM_L2_PERFCOUNTER2_CFG … #define mmMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX … #define mmMMMC_VM_L2_PERFCOUNTER3_CFG … #define mmMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX … #define mmMMMC_VM_L2_PERFCOUNTER4_CFG … #define mmMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX … #define mmMMMC_VM_L2_PERFCOUNTER5_CFG … #define mmMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX … #define mmMMMC_VM_L2_PERFCOUNTER6_CFG … #define mmMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX … #define mmMMMC_VM_L2_PERFCOUNTER7_CFG … #define mmMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX … #define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL … #define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define mmMMUTCL2_PERFCOUNTER0_CFG … #define mmMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX … #define mmMMUTCL2_PERFCOUNTER1_CFG … #define mmMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX … #define mmMMUTCL2_PERFCOUNTER2_CFG … #define mmMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX … #define mmMMUTCL2_PERFCOUNTER3_CFG … #define mmMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX … #define mmMMUTCL2_PERFCOUNTER_RSLT_CNTL … #define mmMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmvml2prdec // base address: 0x6a0e0 #define mmMMMC_VM_L2_PERFCOUNTER_LO … #define mmMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX … #define mmMMMC_VM_L2_PERFCOUNTER_HI … #define mmMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX … #define mmMMUTCL2_PERFCOUNTER_LO … #define mmMMUTCL2_PERFCOUNTER_LO_BASE_IDX … #define mmMMUTCL2_PERFCOUNTER_HI … #define mmMMUTCL2_PERFCOUNTER_HI_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmvmsharedhvdec // base address: 0x6a130 #define mmMMMC_VM_FB_SIZE_OFFSET_VF0 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF1 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF2 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF3 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF4 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF5 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF6 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF7 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF8 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF9 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF10 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF11 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF12 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF13 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF14 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF15 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF16 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF16_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF17 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF17_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF18 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF18_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF19 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF19_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF20 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF20_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF21 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF21_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF22 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF22_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF23 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF23_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF24 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF24_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF25 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF25_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF26 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF26_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF27 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF27_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF28 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF28_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF29 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF29_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF30 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF30_BASE_IDX … #define mmMMMC_VM_FB_SIZE_OFFSET_VF31 … #define mmMMMC_VM_FB_SIZE_OFFSET_VF31_BASE_IDX … #define mmMMVM_IOMMU_MMIO_CNTRL_1 … #define mmMMVM_IOMMU_MMIO_CNTRL_1_BASE_IDX … #define mmMMMC_VM_MARC_BASE_LO_0 … #define mmMMMC_VM_MARC_BASE_LO_0_BASE_IDX … #define mmMMMC_VM_MARC_BASE_LO_1 … #define mmMMMC_VM_MARC_BASE_LO_1_BASE_IDX … #define mmMMMC_VM_MARC_BASE_LO_2 … #define mmMMMC_VM_MARC_BASE_LO_2_BASE_IDX … #define mmMMMC_VM_MARC_BASE_LO_3 … #define mmMMMC_VM_MARC_BASE_LO_3_BASE_IDX … #define mmMMMC_VM_MARC_BASE_HI_0 … #define mmMMMC_VM_MARC_BASE_HI_0_BASE_IDX … #define mmMMMC_VM_MARC_BASE_HI_1 … #define mmMMMC_VM_MARC_BASE_HI_1_BASE_IDX … #define mmMMMC_VM_MARC_BASE_HI_2 … #define mmMMMC_VM_MARC_BASE_HI_2_BASE_IDX … #define mmMMMC_VM_MARC_BASE_HI_3 … #define mmMMMC_VM_MARC_BASE_HI_3_BASE_IDX … #define mmMMMC_VM_MARC_RELOC_LO_0 … #define mmMMMC_VM_MARC_RELOC_LO_0_BASE_IDX … #define mmMMMC_VM_MARC_RELOC_LO_1 … #define mmMMMC_VM_MARC_RELOC_LO_1_BASE_IDX … #define mmMMMC_VM_MARC_RELOC_LO_2 … #define mmMMMC_VM_MARC_RELOC_LO_2_BASE_IDX … #define mmMMMC_VM_MARC_RELOC_LO_3 … #define mmMMMC_VM_MARC_RELOC_LO_3_BASE_IDX … #define mmMMMC_VM_MARC_RELOC_HI_0 … #define mmMMMC_VM_MARC_RELOC_HI_0_BASE_IDX … #define mmMMMC_VM_MARC_RELOC_HI_1 … #define mmMMMC_VM_MARC_RELOC_HI_1_BASE_IDX … #define mmMMMC_VM_MARC_RELOC_HI_2 … #define mmMMMC_VM_MARC_RELOC_HI_2_BASE_IDX … #define mmMMMC_VM_MARC_RELOC_HI_3 … #define mmMMMC_VM_MARC_RELOC_HI_3_BASE_IDX … #define mmMMMC_VM_MARC_LEN_LO_0 … #define mmMMMC_VM_MARC_LEN_LO_0_BASE_IDX … #define mmMMMC_VM_MARC_LEN_LO_1 … #define mmMMMC_VM_MARC_LEN_LO_1_BASE_IDX … #define mmMMMC_VM_MARC_LEN_LO_2 … #define mmMMMC_VM_MARC_LEN_LO_2_BASE_IDX … #define mmMMMC_VM_MARC_LEN_LO_3 … #define mmMMMC_VM_MARC_LEN_LO_3_BASE_IDX … #define mmMMMC_VM_MARC_LEN_HI_0 … #define mmMMMC_VM_MARC_LEN_HI_0_BASE_IDX … #define mmMMMC_VM_MARC_LEN_HI_1 … #define mmMMMC_VM_MARC_LEN_HI_1_BASE_IDX … #define mmMMMC_VM_MARC_LEN_HI_2 … #define mmMMMC_VM_MARC_LEN_HI_2_BASE_IDX … #define mmMMMC_VM_MARC_LEN_HI_3 … #define mmMMMC_VM_MARC_LEN_HI_3_BASE_IDX … #define mmMMVM_IOMMU_CONTROL_REGISTER … #define mmMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX … #define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER … #define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL … #define mmMMVM_PCIE_ATS_CNTL_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_0 … #define mmMMVM_PCIE_ATS_CNTL_VF_0_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_1 … #define mmMMVM_PCIE_ATS_CNTL_VF_1_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_2 … #define mmMMVM_PCIE_ATS_CNTL_VF_2_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_3 … #define mmMMVM_PCIE_ATS_CNTL_VF_3_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_4 … #define mmMMVM_PCIE_ATS_CNTL_VF_4_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_5 … #define mmMMVM_PCIE_ATS_CNTL_VF_5_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_6 … #define mmMMVM_PCIE_ATS_CNTL_VF_6_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_7 … #define mmMMVM_PCIE_ATS_CNTL_VF_7_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_8 … #define mmMMVM_PCIE_ATS_CNTL_VF_8_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_9 … #define mmMMVM_PCIE_ATS_CNTL_VF_9_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_10 … #define mmMMVM_PCIE_ATS_CNTL_VF_10_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_11 … #define mmMMVM_PCIE_ATS_CNTL_VF_11_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_12 … #define mmMMVM_PCIE_ATS_CNTL_VF_12_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_13 … #define mmMMVM_PCIE_ATS_CNTL_VF_13_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_14 … #define mmMMVM_PCIE_ATS_CNTL_VF_14_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_15 … #define mmMMVM_PCIE_ATS_CNTL_VF_15_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_16 … #define mmMMVM_PCIE_ATS_CNTL_VF_16_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_17 … #define mmMMVM_PCIE_ATS_CNTL_VF_17_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_18 … #define mmMMVM_PCIE_ATS_CNTL_VF_18_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_19 … #define mmMMVM_PCIE_ATS_CNTL_VF_19_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_20 … #define mmMMVM_PCIE_ATS_CNTL_VF_20_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_21 … #define mmMMVM_PCIE_ATS_CNTL_VF_21_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_22 … #define mmMMVM_PCIE_ATS_CNTL_VF_22_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_23 … #define mmMMVM_PCIE_ATS_CNTL_VF_23_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_24 … #define mmMMVM_PCIE_ATS_CNTL_VF_24_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_25 … #define mmMMVM_PCIE_ATS_CNTL_VF_25_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_26 … #define mmMMVM_PCIE_ATS_CNTL_VF_26_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_27 … #define mmMMVM_PCIE_ATS_CNTL_VF_27_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_28 … #define mmMMVM_PCIE_ATS_CNTL_VF_28_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_29 … #define mmMMVM_PCIE_ATS_CNTL_VF_29_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_30 … #define mmMMVM_PCIE_ATS_CNTL_VF_30_BASE_IDX … #define mmMMVM_PCIE_ATS_CNTL_VF_31 … #define mmMMVM_PCIE_ATS_CNTL_VF_31_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmvmsharedpfdec // base address: 0x6a340 #define mmMMMC_VM_NB_MMIOBASE … #define mmMMMC_VM_NB_MMIOBASE_BASE_IDX … #define mmMMMC_VM_NB_MMIOLIMIT … #define mmMMMC_VM_NB_MMIOLIMIT_BASE_IDX … #define mmMMMC_VM_NB_PCI_CTRL … #define mmMMMC_VM_NB_PCI_CTRL_BASE_IDX … #define mmMMMC_VM_NB_PCI_ARB … #define mmMMMC_VM_NB_PCI_ARB_BASE_IDX … #define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1 … #define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX … #define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2 … #define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX … #define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2 … #define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX … #define mmMMMC_VM_FB_OFFSET … #define mmMMMC_VM_FB_OFFSET_BASE_IDX … #define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB … #define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX … #define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB … #define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX … #define mmMMMC_VM_STEERING … #define mmMMMC_VM_STEERING_BASE_IDX … #define mmMMMC_SHARED_VIRT_RESET_REQ … #define mmMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX … #define mmMMMC_MEM_POWER_LS … #define mmMMMC_MEM_POWER_LS_BASE_IDX … #define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START … #define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX … #define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END … #define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX … #define mmMMMC_VM_APT_CNTL … #define mmMMMC_VM_APT_CNTL_BASE_IDX … #define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL … #define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX … #define mmMMMC_VM_LOCAL_HBM_ADDRESS_START … #define mmMMMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX … #define mmMMMC_VM_LOCAL_HBM_ADDRESS_END … #define mmMMMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX … #define mmMMUTCL2_CGTT_CLK_CTRL … #define mmMMUTCL2_CGTT_CLK_CTRL_BASE_IDX … #define mmMMMC_SHARED_ACTIVE_FCN_ID … #define mmMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX … #define mmMMMC_SHARED_VIRT_RESET_REQ2 … #define mmMMMC_SHARED_VIRT_RESET_REQ2_BASE_IDX … #define mmMMUTCL2_CGTT_BUSY_CTRL … #define mmMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX … #define mmMMUTCL2_HARVEST_BYPASS_GROUPS … #define mmMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmvmsharedvcdec // base address: 0x6a3b0 #define mmMMMC_VM_FB_LOCATION_BASE … #define mmMMMC_VM_FB_LOCATION_BASE_BASE_IDX … #define mmMMMC_VM_FB_LOCATION_TOP … #define mmMMMC_VM_FB_LOCATION_TOP_BASE_IDX … #define mmMMMC_VM_AGP_TOP … #define mmMMMC_VM_AGP_TOP_BASE_IDX … #define mmMMMC_VM_AGP_BOT … #define mmMMMC_VM_AGP_BOT_BASE_IDX … #define mmMMMC_VM_AGP_BASE … #define mmMMMC_VM_AGP_BASE_BASE_IDX … #define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR … #define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX … #define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR … #define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX … #define mmMMMC_VM_MX_L1_TLB_CNTL … #define mmMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec // base address: 0x6a400 #define mmMM_ATC_L2_PERFCOUNTER_LO … #define mmMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX … #define mmMM_ATC_L2_PERFCOUNTER_HI … #define mmMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec // base address: 0x6a420 #define mmMM_ATC_L2_PERFCOUNTER0_CFG … #define mmMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX … #define mmMM_ATC_L2_PERFCOUNTER1_CFG … #define mmMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX … #define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL … #define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmvml2ptdec // base address: 0x6a500 #define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 … #define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 … #define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 … #define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 … #define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 … #define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 … #define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT0_PAGE_TABLE_RESERVE0 … #define mmMMVM_CONTEXT0_PAGE_TABLE_RESERVE0_BASE_IDX … #define mmMMVM_CONTEXT0_PAGE_TABLE_RESERVE1 … #define mmMMVM_CONTEXT0_PAGE_TABLE_RESERVE1_BASE_IDX … #define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 … #define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 … #define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 … #define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 … #define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 … #define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 … #define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT1_PAGE_TABLE_RESERVE0 … #define mmMMVM_CONTEXT1_PAGE_TABLE_RESERVE0_BASE_IDX … #define mmMMVM_CONTEXT1_PAGE_TABLE_RESERVE1 … #define mmMMVM_CONTEXT1_PAGE_TABLE_RESERVE1_BASE_IDX … #define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 … #define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 … #define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 … #define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 … #define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 … #define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 … #define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT2_PAGE_TABLE_RESERVE0 … #define mmMMVM_CONTEXT2_PAGE_TABLE_RESERVE0_BASE_IDX … #define mmMMVM_CONTEXT2_PAGE_TABLE_RESERVE1 … #define mmMMVM_CONTEXT2_PAGE_TABLE_RESERVE1_BASE_IDX … #define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 … #define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 … #define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 … #define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 … #define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 … #define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 … #define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT3_PAGE_TABLE_RESERVE0 … #define mmMMVM_CONTEXT3_PAGE_TABLE_RESERVE0_BASE_IDX … #define mmMMVM_CONTEXT3_PAGE_TABLE_RESERVE1 … #define mmMMVM_CONTEXT3_PAGE_TABLE_RESERVE1_BASE_IDX … #define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 … #define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 … #define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 … #define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 … #define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 … #define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 … #define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT4_PAGE_TABLE_RESERVE0 … #define mmMMVM_CONTEXT4_PAGE_TABLE_RESERVE0_BASE_IDX … #define mmMMVM_CONTEXT4_PAGE_TABLE_RESERVE1 … #define mmMMVM_CONTEXT4_PAGE_TABLE_RESERVE1_BASE_IDX … #define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 … #define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 … #define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 … #define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 … #define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 … #define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 … #define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT5_PAGE_TABLE_RESERVE0 … #define mmMMVM_CONTEXT5_PAGE_TABLE_RESERVE0_BASE_IDX … #define mmMMVM_CONTEXT5_PAGE_TABLE_RESERVE1 … #define mmMMVM_CONTEXT5_PAGE_TABLE_RESERVE1_BASE_IDX … #define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 … #define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 … #define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 … #define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 … #define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 … #define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 … #define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT6_PAGE_TABLE_RESERVE0 … #define mmMMVM_CONTEXT6_PAGE_TABLE_RESERVE0_BASE_IDX … #define mmMMVM_CONTEXT6_PAGE_TABLE_RESERVE1 … #define mmMMVM_CONTEXT6_PAGE_TABLE_RESERVE1_BASE_IDX … #define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 … #define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 … #define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 … #define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 … #define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 … #define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 … #define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT7_PAGE_TABLE_RESERVE0 … #define mmMMVM_CONTEXT7_PAGE_TABLE_RESERVE0_BASE_IDX … #define mmMMVM_CONTEXT7_PAGE_TABLE_RESERVE1 … #define mmMMVM_CONTEXT7_PAGE_TABLE_RESERVE1_BASE_IDX … #define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 … #define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 … #define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 … #define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 … #define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 … #define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 … #define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT8_PAGE_TABLE_RESERVE0 … #define mmMMVM_CONTEXT8_PAGE_TABLE_RESERVE0_BASE_IDX … #define mmMMVM_CONTEXT8_PAGE_TABLE_RESERVE1 … #define mmMMVM_CONTEXT8_PAGE_TABLE_RESERVE1_BASE_IDX … #define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 … #define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 … #define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 … #define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 … #define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 … #define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 … #define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT9_PAGE_TABLE_RESERVE0 … #define mmMMVM_CONTEXT9_PAGE_TABLE_RESERVE0_BASE_IDX … #define mmMMVM_CONTEXT9_PAGE_TABLE_RESERVE1 … #define mmMMVM_CONTEXT9_PAGE_TABLE_RESERVE1_BASE_IDX … #define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 … #define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 … #define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 … #define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 … #define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 … #define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 … #define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT10_PAGE_TABLE_RESERVE0 … #define mmMMVM_CONTEXT10_PAGE_TABLE_RESERVE0_BASE_IDX … #define mmMMVM_CONTEXT10_PAGE_TABLE_RESERVE1 … #define mmMMVM_CONTEXT10_PAGE_TABLE_RESERVE1_BASE_IDX … #define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 … #define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 … #define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 … #define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 … #define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 … #define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 … #define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT11_PAGE_TABLE_RESERVE0 … #define mmMMVM_CONTEXT11_PAGE_TABLE_RESERVE0_BASE_IDX … #define mmMMVM_CONTEXT11_PAGE_TABLE_RESERVE1 … #define mmMMVM_CONTEXT11_PAGE_TABLE_RESERVE1_BASE_IDX … #define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 … #define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 … #define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 … #define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 … #define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 … #define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 … #define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT12_PAGE_TABLE_RESERVE0 … #define mmMMVM_CONTEXT12_PAGE_TABLE_RESERVE0_BASE_IDX … #define mmMMVM_CONTEXT12_PAGE_TABLE_RESERVE1 … #define mmMMVM_CONTEXT12_PAGE_TABLE_RESERVE1_BASE_IDX … #define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 … #define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 … #define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 … #define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 … #define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 … #define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 … #define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT13_PAGE_TABLE_RESERVE0 … #define mmMMVM_CONTEXT13_PAGE_TABLE_RESERVE0_BASE_IDX … #define mmMMVM_CONTEXT13_PAGE_TABLE_RESERVE1 … #define mmMMVM_CONTEXT13_PAGE_TABLE_RESERVE1_BASE_IDX … #define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 … #define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 … #define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 … #define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 … #define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 … #define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 … #define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT14_PAGE_TABLE_RESERVE0 … #define mmMMVM_CONTEXT14_PAGE_TABLE_RESERVE0_BASE_IDX … #define mmMMVM_CONTEXT14_PAGE_TABLE_RESERVE1 … #define mmMMVM_CONTEXT14_PAGE_TABLE_RESERVE1_BASE_IDX … #define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 … #define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 … #define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 … #define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 … #define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 … #define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 … #define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define mmMMVM_CONTEXT15_PAGE_TABLE_RESERVE0 … #define mmMMVM_CONTEXT15_PAGE_TABLE_RESERVE0_BASE_IDX … #define mmMMVM_CONTEXT15_PAGE_TABLE_RESERVE1 … #define mmMMVM_CONTEXT15_PAGE_TABLE_RESERVE1_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmvml2indec // base address: 0x6a800 #define mmMMVM_INVALIDATE_ENG0_SEM … #define mmMMVM_INVALIDATE_ENG0_SEM_BASE_IDX … #define mmMMVM_INVALIDATE_ENG0_REQ … #define mmMMVM_INVALIDATE_ENG0_REQ_BASE_IDX … #define mmMMVM_INVALIDATE_ENG0_ACK … #define mmMMVM_INVALIDATE_ENG0_ACK_BASE_IDX … #define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 … #define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 … #define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG0_RESERVE0 … #define mmMMVM_INVALIDATE_ENG0_RESERVE0_BASE_IDX … #define mmMMVM_INVALIDATE_ENG0_RESERVE1 … #define mmMMVM_INVALIDATE_ENG0_RESERVE1_BASE_IDX … #define mmMMVM_INVALIDATE_ENG0_RESERVE2 … #define mmMMVM_INVALIDATE_ENG0_RESERVE2_BASE_IDX … #define mmMMVM_INVALIDATE_ENG1_SEM … #define mmMMVM_INVALIDATE_ENG1_SEM_BASE_IDX … #define mmMMVM_INVALIDATE_ENG1_REQ … #define mmMMVM_INVALIDATE_ENG1_REQ_BASE_IDX … #define mmMMVM_INVALIDATE_ENG1_ACK … #define mmMMVM_INVALIDATE_ENG1_ACK_BASE_IDX … #define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 … #define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 … #define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG1_RESERVE0 … #define mmMMVM_INVALIDATE_ENG1_RESERVE0_BASE_IDX … #define mmMMVM_INVALIDATE_ENG1_RESERVE1 … #define mmMMVM_INVALIDATE_ENG1_RESERVE1_BASE_IDX … #define mmMMVM_INVALIDATE_ENG1_RESERVE2 … #define mmMMVM_INVALIDATE_ENG1_RESERVE2_BASE_IDX … #define mmMMVM_INVALIDATE_ENG2_SEM … #define mmMMVM_INVALIDATE_ENG2_SEM_BASE_IDX … #define mmMMVM_INVALIDATE_ENG2_REQ … #define mmMMVM_INVALIDATE_ENG2_REQ_BASE_IDX … #define mmMMVM_INVALIDATE_ENG2_ACK … #define mmMMVM_INVALIDATE_ENG2_ACK_BASE_IDX … #define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 … #define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 … #define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG2_RESERVE0 … #define mmMMVM_INVALIDATE_ENG2_RESERVE0_BASE_IDX … #define mmMMVM_INVALIDATE_ENG2_RESERVE1 … #define mmMMVM_INVALIDATE_ENG2_RESERVE1_BASE_IDX … #define mmMMVM_INVALIDATE_ENG2_RESERVE2 … #define mmMMVM_INVALIDATE_ENG2_RESERVE2_BASE_IDX … #define mmMMVM_INVALIDATE_ENG3_SEM … #define mmMMVM_INVALIDATE_ENG3_SEM_BASE_IDX … #define mmMMVM_INVALIDATE_ENG3_REQ … #define mmMMVM_INVALIDATE_ENG3_REQ_BASE_IDX … #define mmMMVM_INVALIDATE_ENG3_ACK … #define mmMMVM_INVALIDATE_ENG3_ACK_BASE_IDX … #define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 … #define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 … #define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG3_RESERVE0 … #define mmMMVM_INVALIDATE_ENG3_RESERVE0_BASE_IDX … #define mmMMVM_INVALIDATE_ENG3_RESERVE1 … #define mmMMVM_INVALIDATE_ENG3_RESERVE1_BASE_IDX … #define mmMMVM_INVALIDATE_ENG3_RESERVE2 … #define mmMMVM_INVALIDATE_ENG3_RESERVE2_BASE_IDX … #define mmMMVM_INVALIDATE_ENG4_SEM … #define mmMMVM_INVALIDATE_ENG4_SEM_BASE_IDX … #define mmMMVM_INVALIDATE_ENG4_REQ … #define mmMMVM_INVALIDATE_ENG4_REQ_BASE_IDX … #define mmMMVM_INVALIDATE_ENG4_ACK … #define mmMMVM_INVALIDATE_ENG4_ACK_BASE_IDX … #define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 … #define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 … #define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG4_RESERVE0 … #define mmMMVM_INVALIDATE_ENG4_RESERVE0_BASE_IDX … #define mmMMVM_INVALIDATE_ENG4_RESERVE1 … #define mmMMVM_INVALIDATE_ENG4_RESERVE1_BASE_IDX … #define mmMMVM_INVALIDATE_ENG4_RESERVE2 … #define mmMMVM_INVALIDATE_ENG4_RESERVE2_BASE_IDX … #define mmMMVM_INVALIDATE_ENG5_SEM … #define mmMMVM_INVALIDATE_ENG5_SEM_BASE_IDX … #define mmMMVM_INVALIDATE_ENG5_REQ … #define mmMMVM_INVALIDATE_ENG5_REQ_BASE_IDX … #define mmMMVM_INVALIDATE_ENG5_ACK … #define mmMMVM_INVALIDATE_ENG5_ACK_BASE_IDX … #define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 … #define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 … #define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG5_RESERVE0 … #define mmMMVM_INVALIDATE_ENG5_RESERVE0_BASE_IDX … #define mmMMVM_INVALIDATE_ENG5_RESERVE1 … #define mmMMVM_INVALIDATE_ENG5_RESERVE1_BASE_IDX … #define mmMMVM_INVALIDATE_ENG5_RESERVE2 … #define mmMMVM_INVALIDATE_ENG5_RESERVE2_BASE_IDX … #define mmMMVM_INVALIDATE_ENG6_SEM … #define mmMMVM_INVALIDATE_ENG6_SEM_BASE_IDX … #define mmMMVM_INVALIDATE_ENG6_REQ … #define mmMMVM_INVALIDATE_ENG6_REQ_BASE_IDX … #define mmMMVM_INVALIDATE_ENG6_ACK … #define mmMMVM_INVALIDATE_ENG6_ACK_BASE_IDX … #define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 … #define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 … #define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG6_RESERVE0 … #define mmMMVM_INVALIDATE_ENG6_RESERVE0_BASE_IDX … #define mmMMVM_INVALIDATE_ENG6_RESERVE1 … #define mmMMVM_INVALIDATE_ENG6_RESERVE1_BASE_IDX … #define mmMMVM_INVALIDATE_ENG6_RESERVE2 … #define mmMMVM_INVALIDATE_ENG6_RESERVE2_BASE_IDX … #define mmMMVM_INVALIDATE_ENG7_SEM … #define mmMMVM_INVALIDATE_ENG7_SEM_BASE_IDX … #define mmMMVM_INVALIDATE_ENG7_REQ … #define mmMMVM_INVALIDATE_ENG7_REQ_BASE_IDX … #define mmMMVM_INVALIDATE_ENG7_ACK … #define mmMMVM_INVALIDATE_ENG7_ACK_BASE_IDX … #define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 … #define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 … #define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG7_RESERVE0 … #define mmMMVM_INVALIDATE_ENG7_RESERVE0_BASE_IDX … #define mmMMVM_INVALIDATE_ENG7_RESERVE1 … #define mmMMVM_INVALIDATE_ENG7_RESERVE1_BASE_IDX … #define mmMMVM_INVALIDATE_ENG7_RESERVE2 … #define mmMMVM_INVALIDATE_ENG7_RESERVE2_BASE_IDX … #define mmMMVM_INVALIDATE_ENG8_SEM … #define mmMMVM_INVALIDATE_ENG8_SEM_BASE_IDX … #define mmMMVM_INVALIDATE_ENG8_REQ … #define mmMMVM_INVALIDATE_ENG8_REQ_BASE_IDX … #define mmMMVM_INVALIDATE_ENG8_ACK … #define mmMMVM_INVALIDATE_ENG8_ACK_BASE_IDX … #define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 … #define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 … #define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG8_RESERVE0 … #define mmMMVM_INVALIDATE_ENG8_RESERVE0_BASE_IDX … #define mmMMVM_INVALIDATE_ENG8_RESERVE1 … #define mmMMVM_INVALIDATE_ENG8_RESERVE1_BASE_IDX … #define mmMMVM_INVALIDATE_ENG8_RESERVE2 … #define mmMMVM_INVALIDATE_ENG8_RESERVE2_BASE_IDX … #define mmMMVM_INVALIDATE_ENG9_SEM … #define mmMMVM_INVALIDATE_ENG9_SEM_BASE_IDX … #define mmMMVM_INVALIDATE_ENG9_REQ … #define mmMMVM_INVALIDATE_ENG9_REQ_BASE_IDX … #define mmMMVM_INVALIDATE_ENG9_ACK … #define mmMMVM_INVALIDATE_ENG9_ACK_BASE_IDX … #define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 … #define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 … #define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG9_RESERVE0 … #define mmMMVM_INVALIDATE_ENG9_RESERVE0_BASE_IDX … #define mmMMVM_INVALIDATE_ENG9_RESERVE1 … #define mmMMVM_INVALIDATE_ENG9_RESERVE1_BASE_IDX … #define mmMMVM_INVALIDATE_ENG9_RESERVE2 … #define mmMMVM_INVALIDATE_ENG9_RESERVE2_BASE_IDX … #define mmMMVM_INVALIDATE_ENG10_SEM … #define mmMMVM_INVALIDATE_ENG10_SEM_BASE_IDX … #define mmMMVM_INVALIDATE_ENG10_REQ … #define mmMMVM_INVALIDATE_ENG10_REQ_BASE_IDX … #define mmMMVM_INVALIDATE_ENG10_ACK … #define mmMMVM_INVALIDATE_ENG10_ACK_BASE_IDX … #define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 … #define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 … #define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG10_RESERVE0 … #define mmMMVM_INVALIDATE_ENG10_RESERVE0_BASE_IDX … #define mmMMVM_INVALIDATE_ENG10_RESERVE1 … #define mmMMVM_INVALIDATE_ENG10_RESERVE1_BASE_IDX … #define mmMMVM_INVALIDATE_ENG10_RESERVE2 … #define mmMMVM_INVALIDATE_ENG10_RESERVE2_BASE_IDX … #define mmMMVM_INVALIDATE_ENG11_SEM … #define mmMMVM_INVALIDATE_ENG11_SEM_BASE_IDX … #define mmMMVM_INVALIDATE_ENG11_REQ … #define mmMMVM_INVALIDATE_ENG11_REQ_BASE_IDX … #define mmMMVM_INVALIDATE_ENG11_ACK … #define mmMMVM_INVALIDATE_ENG11_ACK_BASE_IDX … #define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 … #define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 … #define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG11_RESERVE0 … #define mmMMVM_INVALIDATE_ENG11_RESERVE0_BASE_IDX … #define mmMMVM_INVALIDATE_ENG11_RESERVE1 … #define mmMMVM_INVALIDATE_ENG11_RESERVE1_BASE_IDX … #define mmMMVM_INVALIDATE_ENG11_RESERVE2 … #define mmMMVM_INVALIDATE_ENG11_RESERVE2_BASE_IDX … #define mmMMVM_INVALIDATE_ENG12_SEM … #define mmMMVM_INVALIDATE_ENG12_SEM_BASE_IDX … #define mmMMVM_INVALIDATE_ENG12_REQ … #define mmMMVM_INVALIDATE_ENG12_REQ_BASE_IDX … #define mmMMVM_INVALIDATE_ENG12_ACK … #define mmMMVM_INVALIDATE_ENG12_ACK_BASE_IDX … #define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 … #define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 … #define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG12_RESERVE0 … #define mmMMVM_INVALIDATE_ENG12_RESERVE0_BASE_IDX … #define mmMMVM_INVALIDATE_ENG12_RESERVE1 … #define mmMMVM_INVALIDATE_ENG12_RESERVE1_BASE_IDX … #define mmMMVM_INVALIDATE_ENG12_RESERVE2 … #define mmMMVM_INVALIDATE_ENG12_RESERVE2_BASE_IDX … #define mmMMVM_INVALIDATE_ENG13_SEM … #define mmMMVM_INVALIDATE_ENG13_SEM_BASE_IDX … #define mmMMVM_INVALIDATE_ENG13_REQ … #define mmMMVM_INVALIDATE_ENG13_REQ_BASE_IDX … #define mmMMVM_INVALIDATE_ENG13_ACK … #define mmMMVM_INVALIDATE_ENG13_ACK_BASE_IDX … #define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 … #define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 … #define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG13_RESERVE0 … #define mmMMVM_INVALIDATE_ENG13_RESERVE0_BASE_IDX … #define mmMMVM_INVALIDATE_ENG13_RESERVE1 … #define mmMMVM_INVALIDATE_ENG13_RESERVE1_BASE_IDX … #define mmMMVM_INVALIDATE_ENG13_RESERVE2 … #define mmMMVM_INVALIDATE_ENG13_RESERVE2_BASE_IDX … #define mmMMVM_INVALIDATE_ENG14_SEM … #define mmMMVM_INVALIDATE_ENG14_SEM_BASE_IDX … #define mmMMVM_INVALIDATE_ENG14_REQ … #define mmMMVM_INVALIDATE_ENG14_REQ_BASE_IDX … #define mmMMVM_INVALIDATE_ENG14_ACK … #define mmMMVM_INVALIDATE_ENG14_ACK_BASE_IDX … #define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 … #define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 … #define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG14_RESERVE0 … #define mmMMVM_INVALIDATE_ENG14_RESERVE0_BASE_IDX … #define mmMMVM_INVALIDATE_ENG14_RESERVE1 … #define mmMMVM_INVALIDATE_ENG14_RESERVE1_BASE_IDX … #define mmMMVM_INVALIDATE_ENG14_RESERVE2 … #define mmMMVM_INVALIDATE_ENG14_RESERVE2_BASE_IDX … #define mmMMVM_INVALIDATE_ENG15_SEM … #define mmMMVM_INVALIDATE_ENG15_SEM_BASE_IDX … #define mmMMVM_INVALIDATE_ENG15_REQ … #define mmMMVM_INVALIDATE_ENG15_REQ_BASE_IDX … #define mmMMVM_INVALIDATE_ENG15_ACK … #define mmMMVM_INVALIDATE_ENG15_ACK_BASE_IDX … #define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 … #define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 … #define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG15_RESERVE0 … #define mmMMVM_INVALIDATE_ENG15_RESERVE0_BASE_IDX … #define mmMMVM_INVALIDATE_ENG15_RESERVE1 … #define mmMMVM_INVALIDATE_ENG15_RESERVE1_BASE_IDX … #define mmMMVM_INVALIDATE_ENG15_RESERVE2 … #define mmMMVM_INVALIDATE_ENG15_RESERVE2_BASE_IDX … #define mmMMVM_INVALIDATE_ENG16_SEM … #define mmMMVM_INVALIDATE_ENG16_SEM_BASE_IDX … #define mmMMVM_INVALIDATE_ENG16_REQ … #define mmMMVM_INVALIDATE_ENG16_REQ_BASE_IDX … #define mmMMVM_INVALIDATE_ENG16_ACK … #define mmMMVM_INVALIDATE_ENG16_ACK_BASE_IDX … #define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 … #define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 … #define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG16_RESERVE0 … #define mmMMVM_INVALIDATE_ENG16_RESERVE0_BASE_IDX … #define mmMMVM_INVALIDATE_ENG16_RESERVE1 … #define mmMMVM_INVALIDATE_ENG16_RESERVE1_BASE_IDX … #define mmMMVM_INVALIDATE_ENG16_RESERVE2 … #define mmMMVM_INVALIDATE_ENG16_RESERVE2_BASE_IDX … #define mmMMVM_INVALIDATE_ENG17_SEM … #define mmMMVM_INVALIDATE_ENG17_SEM_BASE_IDX … #define mmMMVM_INVALIDATE_ENG17_REQ … #define mmMMVM_INVALIDATE_ENG17_REQ_BASE_IDX … #define mmMMVM_INVALIDATE_ENG17_ACK … #define mmMMVM_INVALIDATE_ENG17_ACK_BASE_IDX … #define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 … #define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 … #define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX … #define mmMMVM_INVALIDATE_ENG17_RESERVE0 … #define mmMMVM_INVALIDATE_ENG17_RESERVE0_BASE_IDX … #define mmMMVM_INVALIDATE_ENG17_RESERVE1 … #define mmMMVM_INVALIDATE_ENG17_RESERVE1_BASE_IDX … #define mmMMVM_INVALIDATE_ENG17_RESERVE2 … #define mmMMVM_INVALIDATE_ENG17_RESERVE2_BASE_IDX … // addressBlock: mmhub_mmutcl2_mml2tlbpfdec // base address: 0x6aa90 #define mmMML2TLB_TLB0_STATUS … #define mmMML2TLB_TLB0_STATUS_BASE_IDX … // addressBlock: mmhub_mmutcl2_mml2tlbpldec // base address: 0x6ab00 #define mmMML2TLB_PERFCOUNTER0_CFG … #define mmMML2TLB_PERFCOUNTER0_CFG_BASE_IDX … #define mmMML2TLB_PERFCOUNTER1_CFG … #define mmMML2TLB_PERFCOUNTER1_CFG_BASE_IDX … #define mmMML2TLB_PERFCOUNTER2_CFG … #define mmMML2TLB_PERFCOUNTER2_CFG_BASE_IDX … #define mmMML2TLB_PERFCOUNTER3_CFG … #define mmMML2TLB_PERFCOUNTER3_CFG_BASE_IDX … #define mmMML2TLB_PERFCOUNTER_RSLT_CNTL … #define mmMML2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: mmhub_mmutcl2_mml2tlbprdec // base address: 0x6ab20 #define mmMML2TLB_PERFCOUNTER_LO … #define mmMML2TLB_PERFCOUNTER_LO_BASE_IDX … #define mmMML2TLB_PERFCOUNTER_HI … #define mmMML2TLB_PERFCOUNTER_HI_BASE_IDX … #endif
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