/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef _mmhub_3_0_1_OFFSET_HEADER #define _mmhub_3_0_1_OFFSET_HEADER // addressBlock: mmhub_dagbdec // base address: 0x68000 #define regDAGB0_RDCLI0 … #define regDAGB0_RDCLI0_BASE_IDX … #define regDAGB0_RDCLI1 … #define regDAGB0_RDCLI1_BASE_IDX … #define regDAGB0_RDCLI2 … #define regDAGB0_RDCLI2_BASE_IDX … #define regDAGB0_RDCLI3 … #define regDAGB0_RDCLI3_BASE_IDX … #define regDAGB0_RDCLI4 … #define regDAGB0_RDCLI4_BASE_IDX … #define regDAGB0_RDCLI5 … #define regDAGB0_RDCLI5_BASE_IDX … #define regDAGB0_RDCLI6 … #define regDAGB0_RDCLI6_BASE_IDX … #define regDAGB0_RDCLI7 … #define regDAGB0_RDCLI7_BASE_IDX … #define regDAGB0_RDCLI8 … #define regDAGB0_RDCLI8_BASE_IDX … #define regDAGB0_RDCLI9 … #define regDAGB0_RDCLI9_BASE_IDX … #define regDAGB0_RDCLI10 … #define regDAGB0_RDCLI10_BASE_IDX … #define regDAGB0_RDCLI11 … #define regDAGB0_RDCLI11_BASE_IDX … #define regDAGB0_RDCLI12 … #define regDAGB0_RDCLI12_BASE_IDX … #define regDAGB0_RDCLI13 … #define regDAGB0_RDCLI13_BASE_IDX … #define regDAGB0_RDCLI14 … #define regDAGB0_RDCLI14_BASE_IDX … #define regDAGB0_RDCLI15 … #define regDAGB0_RDCLI15_BASE_IDX … #define regDAGB0_RDCLI16 … #define regDAGB0_RDCLI16_BASE_IDX … #define regDAGB0_RDCLI17 … #define regDAGB0_RDCLI17_BASE_IDX … #define regDAGB0_RDCLI18 … #define regDAGB0_RDCLI18_BASE_IDX … #define regDAGB0_RDCLI19 … #define regDAGB0_RDCLI19_BASE_IDX … #define regDAGB0_RDCLI20 … #define regDAGB0_RDCLI20_BASE_IDX … #define regDAGB0_RDCLI21 … #define regDAGB0_RDCLI21_BASE_IDX … #define regDAGB0_RDCLI22 … #define regDAGB0_RDCLI22_BASE_IDX … #define regDAGB0_RDCLI23 … #define regDAGB0_RDCLI23_BASE_IDX … #define regDAGB0_RDCLI24 … #define regDAGB0_RDCLI24_BASE_IDX … #define regDAGB0_RDCLI25 … #define regDAGB0_RDCLI25_BASE_IDX … #define regDAGB0_RDCLI26 … #define regDAGB0_RDCLI26_BASE_IDX … #define regDAGB0_RDCLI27 … #define regDAGB0_RDCLI27_BASE_IDX … #define regDAGB0_RDCLI28 … #define regDAGB0_RDCLI28_BASE_IDX … #define regDAGB0_RDCLI29 … #define regDAGB0_RDCLI29_BASE_IDX … #define regDAGB0_RD_CNTL … #define regDAGB0_RD_CNTL_BASE_IDX … #define regDAGB0_RD_IO_CNTL … #define regDAGB0_RD_IO_CNTL_BASE_IDX … #define regDAGB0_RD_GMI_CNTL … #define regDAGB0_RD_GMI_CNTL_BASE_IDX … #define regDAGB0_RD_ADDR_DAGB … #define regDAGB0_RD_ADDR_DAGB_BASE_IDX … #define regDAGB0_RD_CGTT_CLK_CTRL … #define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL … #define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB0_RD_ADDR_DAGB_MAX_BURST0 … #define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 … #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define regDAGB0_RD_ADDR_DAGB_MAX_BURST1 … #define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 … #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define regDAGB0_RD_ADDR_DAGB_MAX_BURST2 … #define regDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX … #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 … #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX … #define regDAGB0_RD_ADDR_DAGB_MAX_BURST3 … #define regDAGB0_RD_ADDR_DAGB_MAX_BURST3_BASE_IDX … #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER3 … #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER3_BASE_IDX … #define regDAGB0_RD_VC0_CNTL … #define regDAGB0_RD_VC0_CNTL_BASE_IDX … #define regDAGB0_RD_VC1_CNTL … #define regDAGB0_RD_VC1_CNTL_BASE_IDX … #define regDAGB0_RD_VC2_CNTL … #define regDAGB0_RD_VC2_CNTL_BASE_IDX … #define regDAGB0_RD_VC3_CNTL … #define regDAGB0_RD_VC3_CNTL_BASE_IDX … #define regDAGB0_RD_VC4_CNTL … #define regDAGB0_RD_VC4_CNTL_BASE_IDX … #define regDAGB0_RD_VC5_CNTL … #define regDAGB0_RD_VC5_CNTL_BASE_IDX … #define regDAGB0_RD_IO_VC_CNTL … #define regDAGB0_RD_IO_VC_CNTL_BASE_IDX … #define regDAGB0_RD_GMI_VC_CNTL … #define regDAGB0_RD_GMI_VC_CNTL_BASE_IDX … #define regDAGB0_RD_CNTL_MISC … #define regDAGB0_RD_CNTL_MISC_BASE_IDX … #define regDAGB0_RD_TLB_CREDIT … #define regDAGB0_RD_TLB_CREDIT_BASE_IDX … #define regDAGB0_RDCLI_ASK_PENDING … #define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX … #define regDAGB0_RDCLI_GO_PENDING … #define regDAGB0_RDCLI_GO_PENDING_BASE_IDX … #define regDAGB0_RDCLI_GBLSEND_PENDING … #define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX … #define regDAGB0_RDCLI_TLB_PENDING … #define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX … #define regDAGB0_RDCLI_OARB_PENDING … #define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX … #define regDAGB0_RDCLI_ASK2ARB_PENDING … #define regDAGB0_RDCLI_ASK2ARB_PENDING_BASE_IDX … #define regDAGB0_RDCLI_ASK2DF_PENDING … #define regDAGB0_RDCLI_ASK2DF_PENDING_BASE_IDX … #define regDAGB0_RDCLI_OSD_PENDING … #define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX … #define regDAGB0_RDCLI_ASK_OSD_PENDING … #define regDAGB0_RDCLI_ASK_OSD_PENDING_BASE_IDX … #define regDAGB0_WRCLI0 … #define regDAGB0_WRCLI0_BASE_IDX … #define regDAGB0_WRCLI1 … #define regDAGB0_WRCLI1_BASE_IDX … #define regDAGB0_WRCLI2 … #define regDAGB0_WRCLI2_BASE_IDX … #define regDAGB0_WRCLI3 … #define regDAGB0_WRCLI3_BASE_IDX … #define regDAGB0_WRCLI4 … #define regDAGB0_WRCLI4_BASE_IDX … #define regDAGB0_WRCLI5 … #define regDAGB0_WRCLI5_BASE_IDX … #define regDAGB0_WRCLI6 … #define regDAGB0_WRCLI6_BASE_IDX … #define regDAGB0_WRCLI7 … #define regDAGB0_WRCLI7_BASE_IDX … #define regDAGB0_WRCLI8 … #define regDAGB0_WRCLI8_BASE_IDX … #define regDAGB0_WRCLI9 … #define regDAGB0_WRCLI9_BASE_IDX … #define regDAGB0_WRCLI10 … #define regDAGB0_WRCLI10_BASE_IDX … #define regDAGB0_WRCLI11 … #define regDAGB0_WRCLI11_BASE_IDX … #define regDAGB0_WRCLI12 … #define regDAGB0_WRCLI12_BASE_IDX … #define regDAGB0_WRCLI13 … #define regDAGB0_WRCLI13_BASE_IDX … #define regDAGB0_WRCLI14 … #define regDAGB0_WRCLI14_BASE_IDX … #define regDAGB0_WRCLI15 … #define regDAGB0_WRCLI15_BASE_IDX … #define regDAGB0_WRCLI16 … #define regDAGB0_WRCLI16_BASE_IDX … #define regDAGB0_WRCLI17 … #define regDAGB0_WRCLI17_BASE_IDX … #define regDAGB0_WRCLI18 … #define regDAGB0_WRCLI18_BASE_IDX … #define regDAGB0_WRCLI19 … #define regDAGB0_WRCLI19_BASE_IDX … #define regDAGB0_WRCLI20 … #define regDAGB0_WRCLI20_BASE_IDX … #define regDAGB0_WRCLI21 … #define regDAGB0_WRCLI21_BASE_IDX … #define regDAGB0_WRCLI22 … #define regDAGB0_WRCLI22_BASE_IDX … #define regDAGB0_WRCLI23 … #define regDAGB0_WRCLI23_BASE_IDX … #define regDAGB0_WRCLI24 … #define regDAGB0_WRCLI24_BASE_IDX … #define regDAGB0_WRCLI25 … #define regDAGB0_WRCLI25_BASE_IDX … #define regDAGB0_WRCLI26 … #define regDAGB0_WRCLI26_BASE_IDX … #define regDAGB0_WRCLI27 … #define regDAGB0_WRCLI27_BASE_IDX … #define regDAGB0_WRCLI28 … #define regDAGB0_WRCLI28_BASE_IDX … #define regDAGB0_WRCLI29 … #define regDAGB0_WRCLI29_BASE_IDX … #define regDAGB0_WR_CNTL … #define regDAGB0_WR_CNTL_BASE_IDX … #define regDAGB0_WR_IO_CNTL … #define regDAGB0_WR_IO_CNTL_BASE_IDX … #define regDAGB0_WR_GMI_CNTL … #define regDAGB0_WR_GMI_CNTL_BASE_IDX … #define regDAGB0_WR_ADDR_DAGB … #define regDAGB0_WR_ADDR_DAGB_BASE_IDX … #define regDAGB0_WR_CGTT_CLK_CTRL … #define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL … #define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB0_WR_ADDR_DAGB_MAX_BURST0 … #define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 … #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define regDAGB0_WR_ADDR_DAGB_MAX_BURST1 … #define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 … #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define regDAGB0_WR_ADDR_DAGB_MAX_BURST2 … #define regDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX … #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 … #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX … #define regDAGB0_WR_ADDR_DAGB_MAX_BURST3 … #define regDAGB0_WR_ADDR_DAGB_MAX_BURST3_BASE_IDX … #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER3 … #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER3_BASE_IDX … #define regDAGB0_WR_DATA_DAGB … #define regDAGB0_WR_DATA_DAGB_BASE_IDX … #define regDAGB0_WR_DATA_DAGB_MAX_BURST0 … #define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX … #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 … #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX … #define regDAGB0_WR_DATA_DAGB_MAX_BURST1 … #define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX … #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 … #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX … #define regDAGB0_WR_DATA_DAGB_MAX_BURST2 … #define regDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX … #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2 … #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX … #define regDAGB0_WR_DATA_DAGB_MAX_BURST3 … #define regDAGB0_WR_DATA_DAGB_MAX_BURST3_BASE_IDX … #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER3 … #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER3_BASE_IDX … #define regDAGB0_WR_VC0_CNTL … #define regDAGB0_WR_VC0_CNTL_BASE_IDX … #define regDAGB0_WR_VC1_CNTL … #define regDAGB0_WR_VC1_CNTL_BASE_IDX … #define regDAGB0_WR_VC2_CNTL … #define regDAGB0_WR_VC2_CNTL_BASE_IDX … #define regDAGB0_WR_VC3_CNTL … #define regDAGB0_WR_VC3_CNTL_BASE_IDX … #define regDAGB0_WR_VC4_CNTL … #define regDAGB0_WR_VC4_CNTL_BASE_IDX … #define regDAGB0_WR_VC5_CNTL … #define regDAGB0_WR_VC5_CNTL_BASE_IDX … #define regDAGB0_WR_IO_VC_CNTL … #define regDAGB0_WR_IO_VC_CNTL_BASE_IDX … #define regDAGB0_WR_GMI_VC_CNTL … #define regDAGB0_WR_GMI_VC_CNTL_BASE_IDX … #define regDAGB0_WR_CNTL_MISC … #define regDAGB0_WR_CNTL_MISC_BASE_IDX … #define regDAGB0_WR_TLB_CREDIT … #define regDAGB0_WR_TLB_CREDIT_BASE_IDX … #define regDAGB0_WR_DATA_CREDIT … #define regDAGB0_WR_DATA_CREDIT_BASE_IDX … #define regDAGB0_WR_MISC_CREDIT … #define regDAGB0_WR_MISC_CREDIT_BASE_IDX … #define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1 … #define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX … #define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 … #define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX … #define regDAGB0_WRCLI_ASK_PENDING … #define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX … #define regDAGB0_WRCLI_GO_PENDING … #define regDAGB0_WRCLI_GO_PENDING_BASE_IDX … #define regDAGB0_WRCLI_GBLSEND_PENDING … #define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX … #define regDAGB0_WRCLI_TLB_PENDING … #define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX … #define regDAGB0_WRCLI_OARB_PENDING … #define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX … #define regDAGB0_WRCLI_ASK2ARB_PENDING … #define regDAGB0_WRCLI_ASK2ARB_PENDING_BASE_IDX … #define regDAGB0_WRCLI_ASK2DF_PENDING … #define regDAGB0_WRCLI_ASK2DF_PENDING_BASE_IDX … #define regDAGB0_WRCLI_OSD_PENDING … #define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX … #define regDAGB0_WRCLI_ASK_OSD_PENDING … #define regDAGB0_WRCLI_ASK_OSD_PENDING_BASE_IDX … #define regDAGB0_WRCLI_DBUS_ASK_PENDING … #define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX … #define regDAGB0_WRCLI_DBUS_GO_PENDING … #define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX … #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE … #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX … #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE … #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX … #define regDAGB0_DAGB_DLY … #define regDAGB0_DAGB_DLY_BASE_IDX … #define regDAGB0_CNTL_MISC … #define regDAGB0_CNTL_MISC_BASE_IDX … #define regDAGB0_CNTL_MISC2 … #define regDAGB0_CNTL_MISC2_BASE_IDX … #define regDAGB0_FIFO_EMPTY … #define regDAGB0_FIFO_EMPTY_BASE_IDX … #define regDAGB0_FIFO_FULL … #define regDAGB0_FIFO_FULL_BASE_IDX … #define regDAGB0_RD_CREDITS_FULL … #define regDAGB0_RD_CREDITS_FULL_BASE_IDX … #define regDAGB0_WR_CREDITS_FULL … #define regDAGB0_WR_CREDITS_FULL_BASE_IDX … #define regDAGB0_PERFCOUNTER_LO … #define regDAGB0_PERFCOUNTER_LO_BASE_IDX … #define regDAGB0_PERFCOUNTER_HI … #define regDAGB0_PERFCOUNTER_HI_BASE_IDX … #define regDAGB0_PERFCOUNTER0_CFG … #define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX … #define regDAGB0_PERFCOUNTER1_CFG … #define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX … #define regDAGB0_PERFCOUNTER2_CFG … #define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX … #define regDAGB0_PERFCOUNTER_RSLT_CNTL … #define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define regDAGB0_L1TLB_REG_RW … #define regDAGB0_L1TLB_REG_RW_BASE_IDX … #define regDAGB0_RESERVE1 … #define regDAGB0_RESERVE1_BASE_IDX … #define regDAGB0_RESERVE2 … #define regDAGB0_RESERVE2_BASE_IDX … #define regDAGB0_RESERVE3 … #define regDAGB0_RESERVE3_BASE_IDX … #define regDAGB0_RESERVE4 … #define regDAGB0_RESERVE4_BASE_IDX … #define regDAGB0_SDP_RD_BW_CNTL … #define regDAGB0_SDP_RD_BW_CNTL_BASE_IDX … #define regDAGB0_SDP_PRIORITY_OVERRIDE … #define regDAGB0_SDP_PRIORITY_OVERRIDE_BASE_IDX … #define regDAGB0_SDP_RD_PRIORITY … #define regDAGB0_SDP_RD_PRIORITY_BASE_IDX … #define regDAGB0_SDP_WR_PRIORITY … #define regDAGB0_SDP_WR_PRIORITY_BASE_IDX … #define regDAGB0_SDP_RD_CLI2SDP_VC_MAP … #define regDAGB0_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX … #define regDAGB0_SDP_WR_CLI2SDP_VC_MAP … #define regDAGB0_SDP_WR_CLI2SDP_VC_MAP_BASE_IDX … #define regDAGB0_SDP_ENABLE … #define regDAGB0_SDP_ENABLE_BASE_IDX … #define regDAGB0_SDP_CREDITS … #define regDAGB0_SDP_CREDITS_BASE_IDX … #define regDAGB0_SDP_TAG_RESERVE0 … #define regDAGB0_SDP_TAG_RESERVE0_BASE_IDX … #define regDAGB0_SDP_TAG_RESERVE1 … #define regDAGB0_SDP_TAG_RESERVE1_BASE_IDX … #define regDAGB0_SDP_VCC_RESERVE0 … #define regDAGB0_SDP_VCC_RESERVE0_BASE_IDX … #define regDAGB0_SDP_VCC_RESERVE1 … #define regDAGB0_SDP_VCC_RESERVE1_BASE_IDX … #define regDAGB0_SDP_ERR_STATUS … #define regDAGB0_SDP_ERR_STATUS_BASE_IDX … #define regDAGB0_SDP_REQ_CNTL … #define regDAGB0_SDP_REQ_CNTL_BASE_IDX … #define regDAGB0_SDP_MISC_AON … #define regDAGB0_SDP_MISC_AON_BASE_IDX … #define regDAGB0_SDP_MISC … #define regDAGB0_SDP_MISC_BASE_IDX … #define regDAGB0_SDP_MISC2 … #define regDAGB0_SDP_MISC2_BASE_IDX … #define regDAGB0_SDP_VCD_RESERVE0 … #define regDAGB0_SDP_VCD_RESERVE0_BASE_IDX … #define regDAGB0_SDP_VCD_RESERVE1 … #define regDAGB0_SDP_VCD_RESERVE1_BASE_IDX … #define regDAGB0_SDP_ARB_CNTL0 … #define regDAGB0_SDP_ARB_CNTL0_BASE_IDX … #define regDAGB0_SDP_ARB_CNTL1 … #define regDAGB0_SDP_ARB_CNTL1_BASE_IDX … #define regDAGB0_SDP_CGTT_CLK_CTRL … #define regDAGB0_SDP_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB0_SDP_LATENCY_SAMPLING … #define regDAGB0_SDP_LATENCY_SAMPLING_BASE_IDX … // addressBlock: mmhub_pctldec // base address: 0x68e00 #define regPCTL_CTRL … #define regPCTL_CTRL_BASE_IDX … #define regPCTL_MMHUB_DEEPSLEEP_IB … #define regPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX … #define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE … #define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX … #define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB … #define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX … #define regPCTL_PG_IGNORE_DEEPSLEEP … #define regPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX … #define regPCTL_PG_IGNORE_DEEPSLEEP_IB … #define regPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX … #define regPCTL_SLICE0_CFG_DAGB_WRBUSY … #define regPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX … #define regPCTL_SLICE0_CFG_DAGB_RDBUSY … #define regPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX … #define regPCTL_SLICE0_CFG_DS_ALLOW … #define regPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX … #define regPCTL_SLICE0_CFG_DS_ALLOW_IB … #define regPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX … #define regPCTL_SLICE1_CFG_DAGB_WRBUSY … #define regPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX … #define regPCTL_SLICE1_CFG_DAGB_RDBUSY … #define regPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX … #define regPCTL_SLICE1_CFG_DS_ALLOW … #define regPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX … #define regPCTL_SLICE1_CFG_DS_ALLOW_IB … #define regPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX … #define regPCTL_UTCL2_MISC … #define regPCTL_UTCL2_MISC_BASE_IDX … #define regPCTL_SLICE0_MISC … #define regPCTL_SLICE0_MISC_BASE_IDX … #define regPCTL_SLICE1_MISC … #define regPCTL_SLICE1_MISC_BASE_IDX … #define regPCTL_RENG_CTRL … #define regPCTL_RENG_CTRL_BASE_IDX … #define regPCTL_UTCL2_RENG_EXECUTE … #define regPCTL_UTCL2_RENG_EXECUTE_BASE_IDX … #define regPCTL_SLICE0_RENG_EXECUTE … #define regPCTL_SLICE0_RENG_EXECUTE_BASE_IDX … #define regPCTL_SLICE1_RENG_EXECUTE … #define regPCTL_SLICE1_RENG_EXECUTE_BASE_IDX … #define regPCTL_UTCL2_RENG_RAM_INDEX … #define regPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX … #define regPCTL_UTCL2_RENG_RAM_DATA … #define regPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX … #define regPCTL_SLICE0_RENG_RAM_INDEX … #define regPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX … #define regPCTL_SLICE0_RENG_RAM_DATA … #define regPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX … #define regPCTL_SLICE1_RENG_RAM_INDEX … #define regPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX … #define regPCTL_SLICE1_RENG_RAM_DATA … #define regPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX … #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 … #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 … #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 … #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 … #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX … #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 … #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX … #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 … #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX … #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 … #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 … #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 … #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 … #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX … #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 … #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX … #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 … #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX … #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 … #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX … #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 … #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX … #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 … #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX … #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 … #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX … #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 … #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX … #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 … #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX … #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 … #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX … #define regPCTL_STATUS … #define regPCTL_STATUS_BASE_IDX … #define regPCTL_PERFCOUNTER_LO … #define regPCTL_PERFCOUNTER_LO_BASE_IDX … #define regPCTL_PERFCOUNTER_HI … #define regPCTL_PERFCOUNTER_HI_BASE_IDX … #define regPCTL_PERFCOUNTER0_CFG … #define regPCTL_PERFCOUNTER0_CFG_BASE_IDX … #define regPCTL_PERFCOUNTER1_CFG … #define regPCTL_PERFCOUNTER1_CFG_BASE_IDX … #define regPCTL_PERFCOUNTER_RSLT_CNTL … #define regPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define regPCTL_RESERVED_0 … #define regPCTL_RESERVED_0_BASE_IDX … #define regPCTL_RESERVED_1 … #define regPCTL_RESERVED_1_BASE_IDX … #define regPCTL_RESERVED_2 … #define regPCTL_RESERVED_2_BASE_IDX … #define regPCTL_RESERVED_3 … #define regPCTL_RESERVED_3_BASE_IDX … // addressBlock: mmhub_l1tlb_mmutcl1pfdec // base address: 0x69600 #define regMMMC_VM_MX_L1_TLB0_STATUS … #define regMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX … #define regMMMC_VM_MX_L1_TLB1_STATUS … #define regMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX … #define regMMMC_VM_MX_L1_TLB2_STATUS … #define regMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX … #define regMMMC_VM_MX_L1_TLB3_STATUS … #define regMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX … #define regMMMC_VM_MX_L1_TLB4_STATUS … #define regMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX … #define regMMMC_VM_MX_L1_TLB5_STATUS … #define regMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX … #define regMMMC_VM_MX_L1_TLB6_STATUS … #define regMMMC_VM_MX_L1_TLB6_STATUS_BASE_IDX … #define regMMMC_VM_MX_L1_TLB7_STATUS … #define regMMMC_VM_MX_L1_TLB7_STATUS_BASE_IDX … // addressBlock: mmhub_l1tlb_mmutcl1pldec // base address: 0x69670 #define regMMMC_VM_MX_L1_PERFCOUNTER0_CFG … #define regMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX … #define regMMMC_VM_MX_L1_PERFCOUNTER1_CFG … #define regMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX … #define regMMMC_VM_MX_L1_PERFCOUNTER2_CFG … #define regMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX … #define regMMMC_VM_MX_L1_PERFCOUNTER3_CFG … #define regMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX … #define regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL … #define regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: mmhub_l1tlb_mmutcl1prdec // base address: 0x69690 #define regMMMC_VM_MX_L1_PERFCOUNTER_LO … #define regMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX … #define regMMMC_VM_MX_L1_PERFCOUNTER_HI … #define regMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX … // addressBlock: mmhub_l1tlb_mmvmtlspfdec // base address: 0x696c0 #define regMMMC_VM_MX_L1_TLS0_CNTL … #define regMMMC_VM_MX_L1_TLS0_CNTL_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL0 … #define regMMMC_VM_MX_L1_TLS0_CNTL0_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL1 … #define regMMMC_VM_MX_L1_TLS0_CNTL1_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL2 … #define regMMMC_VM_MX_L1_TLS0_CNTL2_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL3 … #define regMMMC_VM_MX_L1_TLS0_CNTL3_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL4 … #define regMMMC_VM_MX_L1_TLS0_CNTL4_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL5 … #define regMMMC_VM_MX_L1_TLS0_CNTL5_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL6 … #define regMMMC_VM_MX_L1_TLS0_CNTL6_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL7 … #define regMMMC_VM_MX_L1_TLS0_CNTL7_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL8 … #define regMMMC_VM_MX_L1_TLS0_CNTL8_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL9 … #define regMMMC_VM_MX_L1_TLS0_CNTL9_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL10 … #define regMMMC_VM_MX_L1_TLS0_CNTL10_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL11 … #define regMMMC_VM_MX_L1_TLS0_CNTL11_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL12 … #define regMMMC_VM_MX_L1_TLS0_CNTL12_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL13 … #define regMMMC_VM_MX_L1_TLS0_CNTL13_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL14 … #define regMMMC_VM_MX_L1_TLS0_CNTL14_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL15 … #define regMMMC_VM_MX_L1_TLS0_CNTL15_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL16 … #define regMMMC_VM_MX_L1_TLS0_CNTL16_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL17 … #define regMMMC_VM_MX_L1_TLS0_CNTL17_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL18 … #define regMMMC_VM_MX_L1_TLS0_CNTL18_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL19 … #define regMMMC_VM_MX_L1_TLS0_CNTL19_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL20 … #define regMMMC_VM_MX_L1_TLS0_CNTL20_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL21 … #define regMMMC_VM_MX_L1_TLS0_CNTL21_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL22 … #define regMMMC_VM_MX_L1_TLS0_CNTL22_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL23 … #define regMMMC_VM_MX_L1_TLS0_CNTL23_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL24 … #define regMMMC_VM_MX_L1_TLS0_CNTL24_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL25 … #define regMMMC_VM_MX_L1_TLS0_CNTL25_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL26 … #define regMMMC_VM_MX_L1_TLS0_CNTL26_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL27 … #define regMMMC_VM_MX_L1_TLS0_CNTL27_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL28 … #define regMMMC_VM_MX_L1_TLS0_CNTL28_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL29 … #define regMMMC_VM_MX_L1_TLS0_CNTL29_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL30 … #define regMMMC_VM_MX_L1_TLS0_CNTL30_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL31 … #define regMMMC_VM_MX_L1_TLS0_CNTL31_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL32 … #define regMMMC_VM_MX_L1_TLS0_CNTL32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL33 … #define regMMMC_VM_MX_L1_TLS0_CNTL33_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL34 … #define regMMMC_VM_MX_L1_TLS0_CNTL34_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL35 … #define regMMMC_VM_MX_L1_TLS0_CNTL35_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL36 … #define regMMMC_VM_MX_L1_TLS0_CNTL36_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_CNTL37 … #define regMMMC_VM_MX_L1_TLS0_CNTL37_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32 … #define regMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32 … #define regMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32 … #define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32 … #define regMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32 … #define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32 … #define regMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS … #define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32 … #define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32 … #define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32_BASE_IDX … #define regMMVM_L2_SAW_CNTL … #define regMMVM_L2_SAW_CNTL_BASE_IDX … #define regMMVM_L2_SAW_CNTL2 … #define regMMVM_L2_SAW_CNTL2_BASE_IDX … #define regMMVM_L2_SAW_CNTL3 … #define regMMVM_L2_SAW_CNTL3_BASE_IDX … #define regMMVM_L2_SAW_CNTL4 … #define regMMVM_L2_SAW_CNTL4_BASE_IDX … #define regMMVM_L2_SAW_CONTEXT0_CNTL … #define regMMVM_L2_SAW_CONTEXT0_CNTL_BASE_IDX … #define regMMVM_L2_SAW_CONTEXT0_CNTL2 … #define regMMVM_L2_SAW_CONTEXT0_CNTL2_BASE_IDX … #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 … #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 … #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 … #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 … #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 … #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 … #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regMMVM_L2_SAW_CONTEXTS_DISABLE … #define regMMVM_L2_SAW_CONTEXTS_DISABLE_BASE_IDX … #define regMMVM_L2_SAW_PIPES_BUSY_LO32 … #define regMMVM_L2_SAW_PIPES_BUSY_LO32_BASE_IDX … #define regMMVM_L2_SAW_PIPES_BUSY_HI32 … #define regMMVM_L2_SAW_PIPES_BUSY_HI32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS … #define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32 … #define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32_BASE_IDX … #define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32 … #define regMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmatcl2dec // base address: 0x69b00 #define regMM_ATC_L2_CNTL … #define regMM_ATC_L2_CNTL_BASE_IDX … #define regMM_ATC_L2_CNTL2 … #define regMM_ATC_L2_CNTL2_BASE_IDX … #define regMM_ATC_L2_CACHE_DATA0 … #define regMM_ATC_L2_CACHE_DATA0_BASE_IDX … #define regMM_ATC_L2_CACHE_DATA1 … #define regMM_ATC_L2_CACHE_DATA1_BASE_IDX … #define regMM_ATC_L2_CACHE_DATA2 … #define regMM_ATC_L2_CACHE_DATA2_BASE_IDX … #define regMM_ATC_L2_CNTL3 … #define regMM_ATC_L2_CNTL3_BASE_IDX … #define regMM_ATC_L2_CNTL4 … #define regMM_ATC_L2_CNTL4_BASE_IDX … #define regMM_ATC_L2_CNTL5 … #define regMM_ATC_L2_CNTL5_BASE_IDX … #define regMM_ATC_L2_MM_GROUP_RT_CLASSES … #define regMM_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX … #define regMM_ATC_L2_STATUS … #define regMM_ATC_L2_STATUS_BASE_IDX … #define regMM_ATC_L2_STATUS2 … #define regMM_ATC_L2_STATUS2_BASE_IDX … #define regMM_ATC_L2_MISC_CG … #define regMM_ATC_L2_MISC_CG_BASE_IDX … #define regMM_ATC_L2_MEM_POWER_LS … #define regMM_ATC_L2_MEM_POWER_LS_BASE_IDX … #define regMM_ATC_L2_CGTT_CLK_CTRL … #define regMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX … #define regMM_ATC_L2_SDPPORT_CTRL … #define regMM_ATC_L2_SDPPORT_CTRL_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmvml2pfdec // base address: 0x69c00 #define regMMVM_L2_CNTL … #define regMMVM_L2_CNTL_BASE_IDX … #define regMMVM_L2_CNTL2 … #define regMMVM_L2_CNTL2_BASE_IDX … #define regMMVM_L2_CNTL3 … #define regMMVM_L2_CNTL3_BASE_IDX … #define regMMVM_L2_STATUS … #define regMMVM_L2_STATUS_BASE_IDX … #define regMMVM_DUMMY_PAGE_FAULT_CNTL … #define regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX … #define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 … #define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX … #define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 … #define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX … #define regMMVM_INVALIDATE_CNTL … #define regMMVM_INVALIDATE_CNTL_BASE_IDX … #define regMMVM_L2_PROTECTION_FAULT_CNTL … #define regMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX … #define regMMVM_L2_PROTECTION_FAULT_CNTL2 … #define regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX … #define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3 … #define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX … #define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4 … #define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX … #define regMMVM_L2_PROTECTION_FAULT_STATUS … #define regMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX … #define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32 … #define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX … #define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32 … #define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX … #define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 … #define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX … #define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 … #define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX … #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 … #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX … #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 … #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX … #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 … #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX … #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 … #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX … #define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 … #define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX … #define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 … #define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX … #define regMMVM_L2_CNTL4 … #define regMMVM_L2_CNTL4_BASE_IDX … #define regMMVM_L2_MM_GROUP_RT_CLASSES … #define regMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX … #define regMMVM_L2_BANK_SELECT_RESERVED_CID … #define regMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX … #define regMMVM_L2_BANK_SELECT_RESERVED_CID2 … #define regMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX … #define regMMVM_L2_CACHE_PARITY_CNTL … #define regMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX … #define regMMVM_L2_CGTT_CLK_CTRL … #define regMMVM_L2_CGTT_CLK_CTRL_BASE_IDX … #define regMMVM_L2_CNTL5 … #define regMMVM_L2_CNTL5_BASE_IDX … #define regMMVM_L2_GCR_CNTL … #define regMMVM_L2_GCR_CNTL_BASE_IDX … #define regMMVM_L2_CGTT_BUSY_CTRL … #define regMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX … #define regMMVM_L2_PTE_CACHE_DUMP_CNTL … #define regMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX … #define regMMVM_L2_PTE_CACHE_DUMP_READ … #define regMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX … #define regMMVM_L2_BANK_SELECT_MASKS … #define regMMVM_L2_BANK_SELECT_MASKS_BASE_IDX … #define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC … #define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX … #define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC … #define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX … #define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC … #define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX … #define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT … #define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX … #define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ … #define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmvml2vcdec // base address: 0x69d00 #define regMMVM_CONTEXT0_CNTL … #define regMMVM_CONTEXT0_CNTL_BASE_IDX … #define regMMVM_CONTEXT1_CNTL … #define regMMVM_CONTEXT1_CNTL_BASE_IDX … #define regMMVM_CONTEXT2_CNTL … #define regMMVM_CONTEXT2_CNTL_BASE_IDX … #define regMMVM_CONTEXT3_CNTL … #define regMMVM_CONTEXT3_CNTL_BASE_IDX … #define regMMVM_CONTEXT4_CNTL … #define regMMVM_CONTEXT4_CNTL_BASE_IDX … #define regMMVM_CONTEXT5_CNTL … #define regMMVM_CONTEXT5_CNTL_BASE_IDX … #define regMMVM_CONTEXT6_CNTL … #define regMMVM_CONTEXT6_CNTL_BASE_IDX … #define regMMVM_CONTEXT7_CNTL … #define regMMVM_CONTEXT7_CNTL_BASE_IDX … #define regMMVM_CONTEXT8_CNTL … #define regMMVM_CONTEXT8_CNTL_BASE_IDX … #define regMMVM_CONTEXT9_CNTL … #define regMMVM_CONTEXT9_CNTL_BASE_IDX … #define regMMVM_CONTEXT10_CNTL … #define regMMVM_CONTEXT10_CNTL_BASE_IDX … #define regMMVM_CONTEXT11_CNTL … #define regMMVM_CONTEXT11_CNTL_BASE_IDX … #define regMMVM_CONTEXT12_CNTL … #define regMMVM_CONTEXT12_CNTL_BASE_IDX … #define regMMVM_CONTEXT13_CNTL … #define regMMVM_CONTEXT13_CNTL_BASE_IDX … #define regMMVM_CONTEXT14_CNTL … #define regMMVM_CONTEXT14_CNTL_BASE_IDX … #define regMMVM_CONTEXT15_CNTL … #define regMMVM_CONTEXT15_CNTL_BASE_IDX … #define regMMVM_CONTEXTS_DISABLE … #define regMMVM_CONTEXTS_DISABLE_BASE_IDX … #define regMMVM_INVALIDATE_ENG0_SEM … #define regMMVM_INVALIDATE_ENG0_SEM_BASE_IDX … #define regMMVM_INVALIDATE_ENG1_SEM … #define regMMVM_INVALIDATE_ENG1_SEM_BASE_IDX … #define regMMVM_INVALIDATE_ENG2_SEM … #define regMMVM_INVALIDATE_ENG2_SEM_BASE_IDX … #define regMMVM_INVALIDATE_ENG3_SEM … #define regMMVM_INVALIDATE_ENG3_SEM_BASE_IDX … #define regMMVM_INVALIDATE_ENG4_SEM … #define regMMVM_INVALIDATE_ENG4_SEM_BASE_IDX … #define regMMVM_INVALIDATE_ENG5_SEM … #define regMMVM_INVALIDATE_ENG5_SEM_BASE_IDX … #define regMMVM_INVALIDATE_ENG6_SEM … #define regMMVM_INVALIDATE_ENG6_SEM_BASE_IDX … #define regMMVM_INVALIDATE_ENG7_SEM … #define regMMVM_INVALIDATE_ENG7_SEM_BASE_IDX … #define regMMVM_INVALIDATE_ENG8_SEM … #define regMMVM_INVALIDATE_ENG8_SEM_BASE_IDX … #define regMMVM_INVALIDATE_ENG9_SEM … #define regMMVM_INVALIDATE_ENG9_SEM_BASE_IDX … #define regMMVM_INVALIDATE_ENG10_SEM … #define regMMVM_INVALIDATE_ENG10_SEM_BASE_IDX … #define regMMVM_INVALIDATE_ENG11_SEM … #define regMMVM_INVALIDATE_ENG11_SEM_BASE_IDX … #define regMMVM_INVALIDATE_ENG12_SEM … #define regMMVM_INVALIDATE_ENG12_SEM_BASE_IDX … #define regMMVM_INVALIDATE_ENG13_SEM … #define regMMVM_INVALIDATE_ENG13_SEM_BASE_IDX … #define regMMVM_INVALIDATE_ENG14_SEM … #define regMMVM_INVALIDATE_ENG14_SEM_BASE_IDX … #define regMMVM_INVALIDATE_ENG15_SEM … #define regMMVM_INVALIDATE_ENG15_SEM_BASE_IDX … #define regMMVM_INVALIDATE_ENG16_SEM … #define regMMVM_INVALIDATE_ENG16_SEM_BASE_IDX … #define regMMVM_INVALIDATE_ENG17_SEM … #define regMMVM_INVALIDATE_ENG17_SEM_BASE_IDX … #define regMMVM_INVALIDATE_ENG0_REQ … #define regMMVM_INVALIDATE_ENG0_REQ_BASE_IDX … #define regMMVM_INVALIDATE_ENG1_REQ … #define regMMVM_INVALIDATE_ENG1_REQ_BASE_IDX … #define regMMVM_INVALIDATE_ENG2_REQ … #define regMMVM_INVALIDATE_ENG2_REQ_BASE_IDX … #define regMMVM_INVALIDATE_ENG3_REQ … #define regMMVM_INVALIDATE_ENG3_REQ_BASE_IDX … #define regMMVM_INVALIDATE_ENG4_REQ … #define regMMVM_INVALIDATE_ENG4_REQ_BASE_IDX … #define regMMVM_INVALIDATE_ENG5_REQ … #define regMMVM_INVALIDATE_ENG5_REQ_BASE_IDX … #define regMMVM_INVALIDATE_ENG6_REQ … #define regMMVM_INVALIDATE_ENG6_REQ_BASE_IDX … #define regMMVM_INVALIDATE_ENG7_REQ … #define regMMVM_INVALIDATE_ENG7_REQ_BASE_IDX … #define regMMVM_INVALIDATE_ENG8_REQ … #define regMMVM_INVALIDATE_ENG8_REQ_BASE_IDX … #define regMMVM_INVALIDATE_ENG9_REQ … #define regMMVM_INVALIDATE_ENG9_REQ_BASE_IDX … #define regMMVM_INVALIDATE_ENG10_REQ … #define regMMVM_INVALIDATE_ENG10_REQ_BASE_IDX … #define regMMVM_INVALIDATE_ENG11_REQ … #define regMMVM_INVALIDATE_ENG11_REQ_BASE_IDX … #define regMMVM_INVALIDATE_ENG12_REQ … #define regMMVM_INVALIDATE_ENG12_REQ_BASE_IDX … #define regMMVM_INVALIDATE_ENG13_REQ … #define regMMVM_INVALIDATE_ENG13_REQ_BASE_IDX … #define regMMVM_INVALIDATE_ENG14_REQ … #define regMMVM_INVALIDATE_ENG14_REQ_BASE_IDX … #define regMMVM_INVALIDATE_ENG15_REQ … #define regMMVM_INVALIDATE_ENG15_REQ_BASE_IDX … #define regMMVM_INVALIDATE_ENG16_REQ … #define regMMVM_INVALIDATE_ENG16_REQ_BASE_IDX … #define regMMVM_INVALIDATE_ENG17_REQ … #define regMMVM_INVALIDATE_ENG17_REQ_BASE_IDX … #define regMMVM_INVALIDATE_ENG0_ACK … #define regMMVM_INVALIDATE_ENG0_ACK_BASE_IDX … #define regMMVM_INVALIDATE_ENG1_ACK … #define regMMVM_INVALIDATE_ENG1_ACK_BASE_IDX … #define regMMVM_INVALIDATE_ENG2_ACK … #define regMMVM_INVALIDATE_ENG2_ACK_BASE_IDX … #define regMMVM_INVALIDATE_ENG3_ACK … #define regMMVM_INVALIDATE_ENG3_ACK_BASE_IDX … #define regMMVM_INVALIDATE_ENG4_ACK … #define regMMVM_INVALIDATE_ENG4_ACK_BASE_IDX … #define regMMVM_INVALIDATE_ENG5_ACK … #define regMMVM_INVALIDATE_ENG5_ACK_BASE_IDX … #define regMMVM_INVALIDATE_ENG6_ACK … #define regMMVM_INVALIDATE_ENG6_ACK_BASE_IDX … #define regMMVM_INVALIDATE_ENG7_ACK … #define regMMVM_INVALIDATE_ENG7_ACK_BASE_IDX … #define regMMVM_INVALIDATE_ENG8_ACK … #define regMMVM_INVALIDATE_ENG8_ACK_BASE_IDX … #define regMMVM_INVALIDATE_ENG9_ACK … #define regMMVM_INVALIDATE_ENG9_ACK_BASE_IDX … #define regMMVM_INVALIDATE_ENG10_ACK … #define regMMVM_INVALIDATE_ENG10_ACK_BASE_IDX … #define regMMVM_INVALIDATE_ENG11_ACK … #define regMMVM_INVALIDATE_ENG11_ACK_BASE_IDX … #define regMMVM_INVALIDATE_ENG12_ACK … #define regMMVM_INVALIDATE_ENG12_ACK_BASE_IDX … #define regMMVM_INVALIDATE_ENG13_ACK … #define regMMVM_INVALIDATE_ENG13_ACK_BASE_IDX … #define regMMVM_INVALIDATE_ENG14_ACK … #define regMMVM_INVALIDATE_ENG14_ACK_BASE_IDX … #define regMMVM_INVALIDATE_ENG15_ACK … #define regMMVM_INVALIDATE_ENG15_ACK_BASE_IDX … #define regMMVM_INVALIDATE_ENG16_ACK … #define regMMVM_INVALIDATE_ENG16_ACK_BASE_IDX … #define regMMVM_INVALIDATE_ENG17_ACK … #define regMMVM_INVALIDATE_ENG17_ACK_BASE_IDX … #define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 … #define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX … #define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 … #define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX … #define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 … #define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX … #define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 … #define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX … #define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 … #define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX … #define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 … #define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX … #define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 … #define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX … #define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 … #define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX … #define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 … #define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX … #define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 … #define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX … #define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 … #define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX … #define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 … #define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX … #define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 … #define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX … #define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 … #define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX … #define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 … #define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX … #define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 … #define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX … #define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 … #define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX … #define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 … #define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX … #define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 … #define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX … #define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 … #define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX … #define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 … #define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX … #define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 … #define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX … #define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 … #define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX … #define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 … #define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX … #define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 … #define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX … #define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 … #define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX … #define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 … #define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX … #define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 … #define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX … #define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 … #define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX … #define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 … #define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX … #define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 … #define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX … #define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 … #define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX … #define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 … #define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX … #define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 … #define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX … #define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 … #define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX … #define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 … #define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX … #define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 … #define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 … #define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 … #define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 … #define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 … #define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 … #define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 … #define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 … #define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 … #define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 … #define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 … #define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 … #define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 … #define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 … #define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 … #define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 … #define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 … #define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 … #define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 … #define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 … #define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 … #define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 … #define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 … #define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 … #define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 … #define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 … #define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 … #define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 … #define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 … #define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 … #define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 … #define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 … #define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 … #define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 … #define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 … #define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 … #define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 … #define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 … #define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 … #define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 … #define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 … #define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 … #define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 … #define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 … #define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 … #define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 … #define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 … #define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 … #define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 … #define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 … #define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 … #define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 … #define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 … #define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 … #define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 … #define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 … #define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 … #define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 … #define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 … #define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 … #define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 … #define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 … #define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 … #define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 … #define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 … #define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 … #define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 … #define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 … #define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 … #define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 … #define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 … #define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 … #define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 … #define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 … #define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 … #define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 … #define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 … #define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 … #define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 … #define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 … #define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 … #define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 … #define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 … #define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 … #define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 … #define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 … #define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 … #define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 … #define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 … #define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 … #define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 … #define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 … #define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 … #define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 … #define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 … #define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 … #define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmvml2pldec // base address: 0x6a090 #define regMMMC_VM_L2_PERFCOUNTER0_CFG … #define regMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX … #define regMMMC_VM_L2_PERFCOUNTER1_CFG … #define regMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX … #define regMMMC_VM_L2_PERFCOUNTER2_CFG … #define regMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX … #define regMMMC_VM_L2_PERFCOUNTER3_CFG … #define regMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX … #define regMMMC_VM_L2_PERFCOUNTER4_CFG … #define regMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX … #define regMMMC_VM_L2_PERFCOUNTER5_CFG … #define regMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX … #define regMMMC_VM_L2_PERFCOUNTER6_CFG … #define regMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX … #define regMMMC_VM_L2_PERFCOUNTER7_CFG … #define regMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX … #define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL … #define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define regMMUTCL2_PERFCOUNTER0_CFG … #define regMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX … #define regMMUTCL2_PERFCOUNTER1_CFG … #define regMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX … #define regMMUTCL2_PERFCOUNTER2_CFG … #define regMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX … #define regMMUTCL2_PERFCOUNTER3_CFG … #define regMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX … #define regMMUTCL2_PERFCOUNTER_RSLT_CNTL … #define regMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmvml2prdec // base address: 0x6a0e0 #define regMMMC_VM_L2_PERFCOUNTER_LO … #define regMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX … #define regMMMC_VM_L2_PERFCOUNTER_HI … #define regMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX … #define regMMUTCL2_PERFCOUNTER_LO … #define regMMUTCL2_PERFCOUNTER_LO_BASE_IDX … #define regMMUTCL2_PERFCOUNTER_HI … #define regMMUTCL2_PERFCOUNTER_HI_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmvmsharedhvdec // base address: 0x6a130 #define regMMVM_PCIE_ATS_CNTL … #define regMMVM_PCIE_ATS_CNTL_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmvmsharedpfdec // base address: 0x6a340 #define regMMMC_VM_NB_MMIOBASE … #define regMMMC_VM_NB_MMIOBASE_BASE_IDX … #define regMMMC_VM_NB_MMIOLIMIT … #define regMMMC_VM_NB_MMIOLIMIT_BASE_IDX … #define regMMMC_VM_NB_PCI_CTRL … #define regMMMC_VM_NB_PCI_CTRL_BASE_IDX … #define regMMMC_VM_NB_PCI_ARB … #define regMMMC_VM_NB_PCI_ARB_BASE_IDX … #define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1 … #define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX … #define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2 … #define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX … #define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2 … #define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX … #define regMMMC_VM_FB_OFFSET … #define regMMMC_VM_FB_OFFSET_BASE_IDX … #define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB … #define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX … #define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB … #define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX … #define regMMMC_VM_STEERING … #define regMMMC_VM_STEERING_BASE_IDX … #define regMMMC_SHARED_VIRT_RESET_REQ … #define regMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX … #define regMMMC_MEM_POWER_LS … #define regMMMC_MEM_POWER_LS_BASE_IDX … #define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START … #define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX … #define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END … #define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX … #define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START … #define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX … #define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END … #define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX … #define regMMMC_VM_APT_CNTL … #define regMMMC_VM_APT_CNTL_BASE_IDX … #define regMMMC_VM_LOCAL_FB_ADDRESS_START … #define regMMMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX … #define regMMMC_VM_LOCAL_FB_ADDRESS_END … #define regMMMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX … #define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL … #define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX … #define regMMUTCL2_CGTT_CLK_CTRL … #define regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX … #define regMMMC_SHARED_ACTIVE_FCN_ID … #define regMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX … #define regMMUTCL2_CGTT_BUSY_CTRL … #define regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX … #define regMMUTCL2_HARVEST_BYPASS_GROUPS … #define regMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX … #define regMMUTCL2_GROUP_RET_FAULT_STATUS … #define regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmvmsharedvcdec // base address: 0x6a3b0 #define regMMMC_VM_FB_LOCATION_BASE … #define regMMMC_VM_FB_LOCATION_BASE_BASE_IDX … #define regMMMC_VM_FB_LOCATION_TOP … #define regMMMC_VM_FB_LOCATION_TOP_BASE_IDX … #define regMMMC_VM_AGP_TOP … #define regMMMC_VM_AGP_TOP_BASE_IDX … #define regMMMC_VM_AGP_BOT … #define regMMMC_VM_AGP_BOT_BASE_IDX … #define regMMMC_VM_AGP_BASE … #define regMMMC_VM_AGP_BASE_BASE_IDX … #define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR … #define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX … #define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR … #define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX … #define regMMMC_VM_MX_L1_TLB_CNTL … #define regMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec // base address: 0x6a400 #define regMM_ATC_L2_PERFCOUNTER_LO … #define regMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX … #define regMM_ATC_L2_PERFCOUNTER_HI … #define regMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec // base address: 0x6a420 #define regMM_ATC_L2_PERFCOUNTER0_CFG … #define regMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX … #define regMM_ATC_L2_PERFCOUNTER1_CFG … #define regMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX … #define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL … #define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmvml2pspdec // base address: 0x6aa50 #define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID … #define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX … #define regMMVM_IOMMU_CONTROL_REGISTER … #define regMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX … #define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER … #define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX … #define regMMUTC_TRANSLATION_FAULT_CNTL0 … #define regMMUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX … #define regMMUTC_TRANSLATION_FAULT_CNTL1 … #define regMMUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX … // addressBlock: mmhub_mmutcl2_mml2tlbpspdec // base address: 0x6aa80 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL … #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX … // addressBlock: mmhub_mmutcl2_mmatcl2pspdec // base address: 0x6aa90 #define regMM_ATC_L2_IOV_MODE_CNTL … #define regMM_ATC_L2_IOV_MODE_CNTL_BASE_IDX … // addressBlock: mmhub_mmutcl2_mml2tlbpfdec // base address: 0x6aac0 #define regMML2TLB_TLB0_STATUS … #define regMML2TLB_TLB0_STATUS_BASE_IDX … #define regMML2TLB_TMZ_CNTL … #define regMML2TLB_TMZ_CNTL_BASE_IDX … #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO … #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX … #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI … #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX … #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO … #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX … #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI … #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX … #define regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ … #define regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX … // addressBlock: mmhub_mmutcl2_mml2tlbpldec // base address: 0x6ab00 #define regMML2TLB_PERFCOUNTER0_CFG … #define regMML2TLB_PERFCOUNTER0_CFG_BASE_IDX … #define regMML2TLB_PERFCOUNTER1_CFG … #define regMML2TLB_PERFCOUNTER1_CFG_BASE_IDX … #define regMML2TLB_PERFCOUNTER2_CFG … #define regMML2TLB_PERFCOUNTER2_CFG_BASE_IDX … #define regMML2TLB_PERFCOUNTER3_CFG … #define regMML2TLB_PERFCOUNTER3_CFG_BASE_IDX … #define regMML2TLB_PERFCOUNTER_RSLT_CNTL … #define regMML2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: mmhub_mmutcl2_mml2tlbprdec // base address: 0x6ab20 #define regMML2TLB_PERFCOUNTER_LO … #define regMML2TLB_PERFCOUNTER_LO_BASE_IDX … #define regMML2TLB_PERFCOUNTER_HI … #define regMML2TLB_PERFCOUNTER_HI_BASE_IDX … #endif
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