/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef _mmhub_3_0_1_SH_MASK_HEADER #define _mmhub_3_0_1_SH_MASK_HEADER // addressBlock: mmhub_dagbdec //DAGB0_RDCLI0 #define DAGB0_RDCLI0__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI0__URG_HIGH__SHIFT … #define DAGB0_RDCLI0__URG_LOW__SHIFT … #define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI0__MAX_BW__SHIFT … #define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI0__MIN_BW__SHIFT … #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI0__MAX_OSD__SHIFT … #define DAGB0_RDCLI0__VIRT_CHAN_MASK … #define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI0__URG_HIGH_MASK … #define DAGB0_RDCLI0__URG_LOW_MASK … #define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI0__MAX_BW_MASK … #define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI0__MIN_BW_MASK … #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI0__MAX_OSD_MASK … //DAGB0_RDCLI1 #define DAGB0_RDCLI1__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI1__URG_HIGH__SHIFT … #define DAGB0_RDCLI1__URG_LOW__SHIFT … #define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI1__MAX_BW__SHIFT … #define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI1__MIN_BW__SHIFT … #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI1__MAX_OSD__SHIFT … #define DAGB0_RDCLI1__VIRT_CHAN_MASK … #define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI1__URG_HIGH_MASK … #define DAGB0_RDCLI1__URG_LOW_MASK … #define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI1__MAX_BW_MASK … #define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI1__MIN_BW_MASK … #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI1__MAX_OSD_MASK … //DAGB0_RDCLI2 #define DAGB0_RDCLI2__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI2__URG_HIGH__SHIFT … #define DAGB0_RDCLI2__URG_LOW__SHIFT … #define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI2__MAX_BW__SHIFT … #define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI2__MIN_BW__SHIFT … #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI2__MAX_OSD__SHIFT … #define DAGB0_RDCLI2__VIRT_CHAN_MASK … #define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI2__URG_HIGH_MASK … #define DAGB0_RDCLI2__URG_LOW_MASK … #define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI2__MAX_BW_MASK … #define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI2__MIN_BW_MASK … #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI2__MAX_OSD_MASK … //DAGB0_RDCLI3 #define DAGB0_RDCLI3__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI3__URG_HIGH__SHIFT … #define DAGB0_RDCLI3__URG_LOW__SHIFT … #define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI3__MAX_BW__SHIFT … #define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI3__MIN_BW__SHIFT … #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI3__MAX_OSD__SHIFT … #define DAGB0_RDCLI3__VIRT_CHAN_MASK … #define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI3__URG_HIGH_MASK … #define DAGB0_RDCLI3__URG_LOW_MASK … #define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI3__MAX_BW_MASK … #define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI3__MIN_BW_MASK … #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI3__MAX_OSD_MASK … //DAGB0_RDCLI4 #define DAGB0_RDCLI4__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI4__URG_HIGH__SHIFT … #define DAGB0_RDCLI4__URG_LOW__SHIFT … #define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI4__MAX_BW__SHIFT … #define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI4__MIN_BW__SHIFT … #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI4__MAX_OSD__SHIFT … #define DAGB0_RDCLI4__VIRT_CHAN_MASK … #define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI4__URG_HIGH_MASK … #define DAGB0_RDCLI4__URG_LOW_MASK … #define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI4__MAX_BW_MASK … #define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI4__MIN_BW_MASK … #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI4__MAX_OSD_MASK … //DAGB0_RDCLI5 #define DAGB0_RDCLI5__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI5__URG_HIGH__SHIFT … #define DAGB0_RDCLI5__URG_LOW__SHIFT … #define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI5__MAX_BW__SHIFT … #define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI5__MIN_BW__SHIFT … #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI5__MAX_OSD__SHIFT … #define DAGB0_RDCLI5__VIRT_CHAN_MASK … #define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI5__URG_HIGH_MASK … #define DAGB0_RDCLI5__URG_LOW_MASK … #define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI5__MAX_BW_MASK … #define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI5__MIN_BW_MASK … #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI5__MAX_OSD_MASK … //DAGB0_RDCLI6 #define DAGB0_RDCLI6__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI6__URG_HIGH__SHIFT … #define DAGB0_RDCLI6__URG_LOW__SHIFT … #define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI6__MAX_BW__SHIFT … #define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI6__MIN_BW__SHIFT … #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI6__MAX_OSD__SHIFT … #define DAGB0_RDCLI6__VIRT_CHAN_MASK … #define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI6__URG_HIGH_MASK … #define DAGB0_RDCLI6__URG_LOW_MASK … #define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI6__MAX_BW_MASK … #define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI6__MIN_BW_MASK … #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI6__MAX_OSD_MASK … //DAGB0_RDCLI7 #define DAGB0_RDCLI7__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI7__URG_HIGH__SHIFT … #define DAGB0_RDCLI7__URG_LOW__SHIFT … #define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI7__MAX_BW__SHIFT … #define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI7__MIN_BW__SHIFT … #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI7__MAX_OSD__SHIFT … #define DAGB0_RDCLI7__VIRT_CHAN_MASK … #define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI7__URG_HIGH_MASK … #define DAGB0_RDCLI7__URG_LOW_MASK … #define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI7__MAX_BW_MASK … #define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI7__MIN_BW_MASK … #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI7__MAX_OSD_MASK … //DAGB0_RDCLI8 #define DAGB0_RDCLI8__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI8__URG_HIGH__SHIFT … #define DAGB0_RDCLI8__URG_LOW__SHIFT … #define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI8__MAX_BW__SHIFT … #define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI8__MIN_BW__SHIFT … #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI8__MAX_OSD__SHIFT … #define DAGB0_RDCLI8__VIRT_CHAN_MASK … #define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI8__URG_HIGH_MASK … #define DAGB0_RDCLI8__URG_LOW_MASK … #define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI8__MAX_BW_MASK … #define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI8__MIN_BW_MASK … #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI8__MAX_OSD_MASK … //DAGB0_RDCLI9 #define DAGB0_RDCLI9__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI9__URG_HIGH__SHIFT … #define DAGB0_RDCLI9__URG_LOW__SHIFT … #define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI9__MAX_BW__SHIFT … #define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI9__MIN_BW__SHIFT … #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI9__MAX_OSD__SHIFT … #define DAGB0_RDCLI9__VIRT_CHAN_MASK … #define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI9__URG_HIGH_MASK … #define DAGB0_RDCLI9__URG_LOW_MASK … #define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI9__MAX_BW_MASK … #define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI9__MIN_BW_MASK … #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI9__MAX_OSD_MASK … //DAGB0_RDCLI10 #define DAGB0_RDCLI10__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI10__URG_HIGH__SHIFT … #define DAGB0_RDCLI10__URG_LOW__SHIFT … #define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI10__MAX_BW__SHIFT … #define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI10__MIN_BW__SHIFT … #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI10__MAX_OSD__SHIFT … #define DAGB0_RDCLI10__VIRT_CHAN_MASK … #define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI10__URG_HIGH_MASK … #define DAGB0_RDCLI10__URG_LOW_MASK … #define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI10__MAX_BW_MASK … #define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI10__MIN_BW_MASK … #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI10__MAX_OSD_MASK … //DAGB0_RDCLI11 #define DAGB0_RDCLI11__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI11__URG_HIGH__SHIFT … #define DAGB0_RDCLI11__URG_LOW__SHIFT … #define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI11__MAX_BW__SHIFT … #define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI11__MIN_BW__SHIFT … #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI11__MAX_OSD__SHIFT … #define DAGB0_RDCLI11__VIRT_CHAN_MASK … #define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI11__URG_HIGH_MASK … #define DAGB0_RDCLI11__URG_LOW_MASK … #define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI11__MAX_BW_MASK … #define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI11__MIN_BW_MASK … #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI11__MAX_OSD_MASK … //DAGB0_RDCLI12 #define DAGB0_RDCLI12__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI12__URG_HIGH__SHIFT … #define DAGB0_RDCLI12__URG_LOW__SHIFT … #define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI12__MAX_BW__SHIFT … #define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI12__MIN_BW__SHIFT … #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI12__MAX_OSD__SHIFT … #define DAGB0_RDCLI12__VIRT_CHAN_MASK … #define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI12__URG_HIGH_MASK … #define DAGB0_RDCLI12__URG_LOW_MASK … #define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI12__MAX_BW_MASK … #define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI12__MIN_BW_MASK … #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI12__MAX_OSD_MASK … //DAGB0_RDCLI13 #define DAGB0_RDCLI13__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI13__URG_HIGH__SHIFT … #define DAGB0_RDCLI13__URG_LOW__SHIFT … #define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI13__MAX_BW__SHIFT … #define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI13__MIN_BW__SHIFT … #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI13__MAX_OSD__SHIFT … #define DAGB0_RDCLI13__VIRT_CHAN_MASK … #define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI13__URG_HIGH_MASK … #define DAGB0_RDCLI13__URG_LOW_MASK … #define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI13__MAX_BW_MASK … #define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI13__MIN_BW_MASK … #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI13__MAX_OSD_MASK … //DAGB0_RDCLI14 #define DAGB0_RDCLI14__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI14__URG_HIGH__SHIFT … #define DAGB0_RDCLI14__URG_LOW__SHIFT … #define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI14__MAX_BW__SHIFT … #define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI14__MIN_BW__SHIFT … #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI14__MAX_OSD__SHIFT … #define DAGB0_RDCLI14__VIRT_CHAN_MASK … #define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI14__URG_HIGH_MASK … #define DAGB0_RDCLI14__URG_LOW_MASK … #define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI14__MAX_BW_MASK … #define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI14__MIN_BW_MASK … #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI14__MAX_OSD_MASK … //DAGB0_RDCLI15 #define DAGB0_RDCLI15__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI15__URG_HIGH__SHIFT … #define DAGB0_RDCLI15__URG_LOW__SHIFT … #define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI15__MAX_BW__SHIFT … #define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI15__MIN_BW__SHIFT … #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI15__MAX_OSD__SHIFT … #define DAGB0_RDCLI15__VIRT_CHAN_MASK … #define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI15__URG_HIGH_MASK … #define DAGB0_RDCLI15__URG_LOW_MASK … #define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI15__MAX_BW_MASK … #define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI15__MIN_BW_MASK … #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI15__MAX_OSD_MASK … //DAGB0_RDCLI16 #define DAGB0_RDCLI16__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI16__URG_HIGH__SHIFT … #define DAGB0_RDCLI16__URG_LOW__SHIFT … #define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI16__MAX_BW__SHIFT … #define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI16__MIN_BW__SHIFT … #define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI16__MAX_OSD__SHIFT … #define DAGB0_RDCLI16__VIRT_CHAN_MASK … #define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI16__URG_HIGH_MASK … #define DAGB0_RDCLI16__URG_LOW_MASK … #define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI16__MAX_BW_MASK … #define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI16__MIN_BW_MASK … #define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI16__MAX_OSD_MASK … //DAGB0_RDCLI17 #define DAGB0_RDCLI17__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI17__URG_HIGH__SHIFT … #define DAGB0_RDCLI17__URG_LOW__SHIFT … #define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI17__MAX_BW__SHIFT … #define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI17__MIN_BW__SHIFT … #define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI17__MAX_OSD__SHIFT … #define DAGB0_RDCLI17__VIRT_CHAN_MASK … #define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI17__URG_HIGH_MASK … #define DAGB0_RDCLI17__URG_LOW_MASK … #define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI17__MAX_BW_MASK … #define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI17__MIN_BW_MASK … #define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI17__MAX_OSD_MASK … //DAGB0_RDCLI18 #define DAGB0_RDCLI18__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI18__URG_HIGH__SHIFT … #define DAGB0_RDCLI18__URG_LOW__SHIFT … #define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI18__MAX_BW__SHIFT … #define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI18__MIN_BW__SHIFT … #define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI18__MAX_OSD__SHIFT … #define DAGB0_RDCLI18__VIRT_CHAN_MASK … #define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI18__URG_HIGH_MASK … #define DAGB0_RDCLI18__URG_LOW_MASK … #define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI18__MAX_BW_MASK … #define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI18__MIN_BW_MASK … #define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI18__MAX_OSD_MASK … //DAGB0_RDCLI19 #define DAGB0_RDCLI19__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI19__URG_HIGH__SHIFT … #define DAGB0_RDCLI19__URG_LOW__SHIFT … #define DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI19__MAX_BW__SHIFT … #define DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI19__MIN_BW__SHIFT … #define DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI19__MAX_OSD__SHIFT … #define DAGB0_RDCLI19__VIRT_CHAN_MASK … #define DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI19__URG_HIGH_MASK … #define DAGB0_RDCLI19__URG_LOW_MASK … #define DAGB0_RDCLI19__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI19__MAX_BW_MASK … #define DAGB0_RDCLI19__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI19__MIN_BW_MASK … #define DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI19__MAX_OSD_MASK … //DAGB0_RDCLI20 #define DAGB0_RDCLI20__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI20__URG_HIGH__SHIFT … #define DAGB0_RDCLI20__URG_LOW__SHIFT … #define DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI20__MAX_BW__SHIFT … #define DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI20__MIN_BW__SHIFT … #define DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI20__MAX_OSD__SHIFT … #define DAGB0_RDCLI20__VIRT_CHAN_MASK … #define DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI20__URG_HIGH_MASK … #define DAGB0_RDCLI20__URG_LOW_MASK … #define DAGB0_RDCLI20__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI20__MAX_BW_MASK … #define DAGB0_RDCLI20__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI20__MIN_BW_MASK … #define DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI20__MAX_OSD_MASK … //DAGB0_RDCLI21 #define DAGB0_RDCLI21__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI21__URG_HIGH__SHIFT … #define DAGB0_RDCLI21__URG_LOW__SHIFT … #define DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI21__MAX_BW__SHIFT … #define DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI21__MIN_BW__SHIFT … #define DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI21__MAX_OSD__SHIFT … #define DAGB0_RDCLI21__VIRT_CHAN_MASK … #define DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI21__URG_HIGH_MASK … #define DAGB0_RDCLI21__URG_LOW_MASK … #define DAGB0_RDCLI21__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI21__MAX_BW_MASK … #define DAGB0_RDCLI21__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI21__MIN_BW_MASK … #define DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI21__MAX_OSD_MASK … //DAGB0_RDCLI22 #define DAGB0_RDCLI22__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI22__URG_HIGH__SHIFT … #define DAGB0_RDCLI22__URG_LOW__SHIFT … #define DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI22__MAX_BW__SHIFT … #define DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI22__MIN_BW__SHIFT … #define DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI22__MAX_OSD__SHIFT … #define DAGB0_RDCLI22__VIRT_CHAN_MASK … #define DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI22__URG_HIGH_MASK … #define DAGB0_RDCLI22__URG_LOW_MASK … #define DAGB0_RDCLI22__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI22__MAX_BW_MASK … #define DAGB0_RDCLI22__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI22__MIN_BW_MASK … #define DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI22__MAX_OSD_MASK … //DAGB0_RDCLI23 #define DAGB0_RDCLI23__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI23__URG_HIGH__SHIFT … #define DAGB0_RDCLI23__URG_LOW__SHIFT … #define DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI23__MAX_BW__SHIFT … #define DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI23__MIN_BW__SHIFT … #define DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI23__MAX_OSD__SHIFT … #define DAGB0_RDCLI23__VIRT_CHAN_MASK … #define DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI23__URG_HIGH_MASK … #define DAGB0_RDCLI23__URG_LOW_MASK … #define DAGB0_RDCLI23__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI23__MAX_BW_MASK … #define DAGB0_RDCLI23__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI23__MIN_BW_MASK … #define DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI23__MAX_OSD_MASK … //DAGB0_RDCLI24 #define DAGB0_RDCLI24__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI24__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI24__URG_HIGH__SHIFT … #define DAGB0_RDCLI24__URG_LOW__SHIFT … #define DAGB0_RDCLI24__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI24__MAX_BW__SHIFT … #define DAGB0_RDCLI24__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI24__MIN_BW__SHIFT … #define DAGB0_RDCLI24__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI24__MAX_OSD__SHIFT … #define DAGB0_RDCLI24__VIRT_CHAN_MASK … #define DAGB0_RDCLI24__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI24__URG_HIGH_MASK … #define DAGB0_RDCLI24__URG_LOW_MASK … #define DAGB0_RDCLI24__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI24__MAX_BW_MASK … #define DAGB0_RDCLI24__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI24__MIN_BW_MASK … #define DAGB0_RDCLI24__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI24__MAX_OSD_MASK … //DAGB0_RDCLI25 #define DAGB0_RDCLI25__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI25__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI25__URG_HIGH__SHIFT … #define DAGB0_RDCLI25__URG_LOW__SHIFT … #define DAGB0_RDCLI25__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI25__MAX_BW__SHIFT … #define DAGB0_RDCLI25__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI25__MIN_BW__SHIFT … #define DAGB0_RDCLI25__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI25__MAX_OSD__SHIFT … #define DAGB0_RDCLI25__VIRT_CHAN_MASK … #define DAGB0_RDCLI25__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI25__URG_HIGH_MASK … #define DAGB0_RDCLI25__URG_LOW_MASK … #define DAGB0_RDCLI25__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI25__MAX_BW_MASK … #define DAGB0_RDCLI25__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI25__MIN_BW_MASK … #define DAGB0_RDCLI25__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI25__MAX_OSD_MASK … //DAGB0_RDCLI26 #define DAGB0_RDCLI26__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI26__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI26__URG_HIGH__SHIFT … #define DAGB0_RDCLI26__URG_LOW__SHIFT … #define DAGB0_RDCLI26__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI26__MAX_BW__SHIFT … #define DAGB0_RDCLI26__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI26__MIN_BW__SHIFT … #define DAGB0_RDCLI26__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI26__MAX_OSD__SHIFT … #define DAGB0_RDCLI26__VIRT_CHAN_MASK … #define DAGB0_RDCLI26__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI26__URG_HIGH_MASK … #define DAGB0_RDCLI26__URG_LOW_MASK … #define DAGB0_RDCLI26__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI26__MAX_BW_MASK … #define DAGB0_RDCLI26__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI26__MIN_BW_MASK … #define DAGB0_RDCLI26__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI26__MAX_OSD_MASK … //DAGB0_RDCLI27 #define DAGB0_RDCLI27__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI27__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI27__URG_HIGH__SHIFT … #define DAGB0_RDCLI27__URG_LOW__SHIFT … #define DAGB0_RDCLI27__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI27__MAX_BW__SHIFT … #define DAGB0_RDCLI27__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI27__MIN_BW__SHIFT … #define DAGB0_RDCLI27__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI27__MAX_OSD__SHIFT … #define DAGB0_RDCLI27__VIRT_CHAN_MASK … #define DAGB0_RDCLI27__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI27__URG_HIGH_MASK … #define DAGB0_RDCLI27__URG_LOW_MASK … #define DAGB0_RDCLI27__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI27__MAX_BW_MASK … #define DAGB0_RDCLI27__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI27__MIN_BW_MASK … #define DAGB0_RDCLI27__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI27__MAX_OSD_MASK … //DAGB0_RDCLI28 #define DAGB0_RDCLI28__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI28__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI28__URG_HIGH__SHIFT … #define DAGB0_RDCLI28__URG_LOW__SHIFT … #define DAGB0_RDCLI28__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI28__MAX_BW__SHIFT … #define DAGB0_RDCLI28__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI28__MIN_BW__SHIFT … #define DAGB0_RDCLI28__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI28__MAX_OSD__SHIFT … #define DAGB0_RDCLI28__VIRT_CHAN_MASK … #define DAGB0_RDCLI28__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI28__URG_HIGH_MASK … #define DAGB0_RDCLI28__URG_LOW_MASK … #define DAGB0_RDCLI28__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI28__MAX_BW_MASK … #define DAGB0_RDCLI28__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI28__MIN_BW_MASK … #define DAGB0_RDCLI28__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI28__MAX_OSD_MASK … //DAGB0_RDCLI29 #define DAGB0_RDCLI29__VIRT_CHAN__SHIFT … #define DAGB0_RDCLI29__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_RDCLI29__URG_HIGH__SHIFT … #define DAGB0_RDCLI29__URG_LOW__SHIFT … #define DAGB0_RDCLI29__MAX_BW_ENABLE__SHIFT … #define DAGB0_RDCLI29__MAX_BW__SHIFT … #define DAGB0_RDCLI29__MIN_BW_ENABLE__SHIFT … #define DAGB0_RDCLI29__MIN_BW__SHIFT … #define DAGB0_RDCLI29__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RDCLI29__MAX_OSD__SHIFT … #define DAGB0_RDCLI29__VIRT_CHAN_MASK … #define DAGB0_RDCLI29__CHECK_TLB_CREDIT_MASK … #define DAGB0_RDCLI29__URG_HIGH_MASK … #define DAGB0_RDCLI29__URG_LOW_MASK … #define DAGB0_RDCLI29__MAX_BW_ENABLE_MASK … #define DAGB0_RDCLI29__MAX_BW_MASK … #define DAGB0_RDCLI29__MIN_BW_ENABLE_MASK … #define DAGB0_RDCLI29__MIN_BW_MASK … #define DAGB0_RDCLI29__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RDCLI29__MAX_OSD_MASK … //DAGB0_RD_CNTL #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT … #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT … #define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT … #define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT … #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK … #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK … #define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK … #define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN_MASK … //DAGB0_RD_IO_CNTL #define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT … #define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT … #define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT … #define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT … #define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT … #define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT … #define DAGB0_RD_IO_CNTL__COMMON_PRIORITY__SHIFT … #define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK … #define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK … #define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK … #define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK … #define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK … #define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK … #define DAGB0_RD_IO_CNTL__COMMON_PRIORITY_MASK … //DAGB0_RD_GMI_CNTL #define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT … #define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT … #define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT … #define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT … #define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT … #define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT … #define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT … #define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK … #define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK … #define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK … #define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK … #define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK … #define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK … #define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY_MASK … //DAGB0_RD_ADDR_DAGB #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT … #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT … #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT … #define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT … #define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT … #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK … #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK … #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK … #define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK … #define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK … //DAGB0_RD_CGTT_CLK_CTRL #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT … #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT … #define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT … #define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT … #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK … #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK … #define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK … #define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK … #define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK … //DAGB0_L1TLB_RD_CGTT_CLK_CTRL #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT … #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT … #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT … #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT … #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK … #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK … #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK … #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK … #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK … //DAGB0_RD_ADDR_DAGB_MAX_BURST0 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK … //DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK … //DAGB0_RD_ADDR_DAGB_MAX_BURST1 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK … //DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK … //DAGB0_RD_ADDR_DAGB_MAX_BURST2 #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK … //DAGB0_RD_ADDR_DAGB_LAZY_TIMER2 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK … //DAGB0_RD_ADDR_DAGB_MAX_BURST3 #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT … #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK … #define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK … //DAGB0_RD_ADDR_DAGB_LAZY_TIMER3 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK … #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK … //DAGB0_RD_VC0_CNTL #define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT … #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT … #define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT … #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT … #define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT … #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT … #define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK … #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK … #define DAGB0_RD_VC0_CNTL__MAX_BW_MASK … #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK … #define DAGB0_RD_VC0_CNTL__MIN_BW_MASK … #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK … //DAGB0_RD_VC1_CNTL #define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT … #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT … #define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT … #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT … #define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT … #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT … #define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK … #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK … #define DAGB0_RD_VC1_CNTL__MAX_BW_MASK … #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK … #define DAGB0_RD_VC1_CNTL__MIN_BW_MASK … #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK … //DAGB0_RD_VC2_CNTL #define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT … #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT … #define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT … #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT … #define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT … #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT … #define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK … #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK … #define DAGB0_RD_VC2_CNTL__MAX_BW_MASK … #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK … #define DAGB0_RD_VC2_CNTL__MIN_BW_MASK … #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK … //DAGB0_RD_VC3_CNTL #define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT … #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT … #define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT … #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT … #define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT … #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT … #define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK … #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK … #define DAGB0_RD_VC3_CNTL__MAX_BW_MASK … #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK … #define DAGB0_RD_VC3_CNTL__MIN_BW_MASK … #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK … //DAGB0_RD_VC4_CNTL #define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT … #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT … #define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT … #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT … #define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT … #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT … #define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK … #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK … #define DAGB0_RD_VC4_CNTL__MAX_BW_MASK … #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK … #define DAGB0_RD_VC4_CNTL__MIN_BW_MASK … #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK … //DAGB0_RD_VC5_CNTL #define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT … #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT … #define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT … #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT … #define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT … #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT … #define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK … #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK … #define DAGB0_RD_VC5_CNTL__MAX_BW_MASK … #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK … #define DAGB0_RD_VC5_CNTL__MIN_BW_MASK … #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK … //DAGB0_RD_IO_VC_CNTL #define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT … #define DAGB0_RD_IO_VC_CNTL__MAX_BW__SHIFT … #define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT … #define DAGB0_RD_IO_VC_CNTL__MIN_BW__SHIFT … #define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RD_IO_VC_CNTL__MAX_OSD__SHIFT … #define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK … #define DAGB0_RD_IO_VC_CNTL__MAX_BW_MASK … #define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK … #define DAGB0_RD_IO_VC_CNTL__MIN_BW_MASK … #define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RD_IO_VC_CNTL__MAX_OSD_MASK … //DAGB0_RD_GMI_VC_CNTL #define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT … #define DAGB0_RD_GMI_VC_CNTL__MAX_BW__SHIFT … #define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT … #define DAGB0_RD_GMI_VC_CNTL__MIN_BW__SHIFT … #define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_RD_GMI_VC_CNTL__MAX_OSD__SHIFT … #define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK … #define DAGB0_RD_GMI_VC_CNTL__MAX_BW_MASK … #define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK … #define DAGB0_RD_GMI_VC_CNTL__MIN_BW_MASK … #define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK … #define DAGB0_RD_GMI_VC_CNTL__MAX_OSD_MASK … //DAGB0_RD_CNTL_MISC #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT … #define DAGB0_RD_CNTL_MISC__UTCL2_VCI__SHIFT … #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK … #define DAGB0_RD_CNTL_MISC__UTCL2_VCI_MASK … //DAGB0_RD_TLB_CREDIT #define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT … #define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT … #define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT … #define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT … #define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT … #define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT … #define DAGB0_RD_TLB_CREDIT__TLB0_MASK … #define DAGB0_RD_TLB_CREDIT__TLB1_MASK … #define DAGB0_RD_TLB_CREDIT__TLB2_MASK … #define DAGB0_RD_TLB_CREDIT__TLB3_MASK … #define DAGB0_RD_TLB_CREDIT__TLB4_MASK … #define DAGB0_RD_TLB_CREDIT__TLB5_MASK … //DAGB0_RDCLI_ASK_PENDING #define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT … #define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK … //DAGB0_RDCLI_GO_PENDING #define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT … #define DAGB0_RDCLI_GO_PENDING__BUSY_MASK … //DAGB0_RDCLI_GBLSEND_PENDING #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT … #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK … //DAGB0_RDCLI_TLB_PENDING #define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT … #define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK … //DAGB0_RDCLI_OARB_PENDING #define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT … #define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK … //DAGB0_RDCLI_ASK2ARB_PENDING #define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT … #define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY_MASK … //DAGB0_RDCLI_ASK2DF_PENDING #define DAGB0_RDCLI_ASK2DF_PENDING__BUSY__SHIFT … #define DAGB0_RDCLI_ASK2DF_PENDING__BUSY_MASK … //DAGB0_RDCLI_OSD_PENDING #define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT … #define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK … //DAGB0_RDCLI_ASK_OSD_PENDING #define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT … #define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY_MASK … //DAGB0_WRCLI0 #define DAGB0_WRCLI0__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI0__URG_HIGH__SHIFT … #define DAGB0_WRCLI0__URG_LOW__SHIFT … #define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI0__MAX_BW__SHIFT … #define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI0__MIN_BW__SHIFT … #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI0__MAX_OSD__SHIFT … #define DAGB0_WRCLI0__VIRT_CHAN_MASK … #define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI0__URG_HIGH_MASK … #define DAGB0_WRCLI0__URG_LOW_MASK … #define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI0__MAX_BW_MASK … #define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI0__MIN_BW_MASK … #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI0__MAX_OSD_MASK … //DAGB0_WRCLI1 #define DAGB0_WRCLI1__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI1__URG_HIGH__SHIFT … #define DAGB0_WRCLI1__URG_LOW__SHIFT … #define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI1__MAX_BW__SHIFT … #define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI1__MIN_BW__SHIFT … #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI1__MAX_OSD__SHIFT … #define DAGB0_WRCLI1__VIRT_CHAN_MASK … #define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI1__URG_HIGH_MASK … #define DAGB0_WRCLI1__URG_LOW_MASK … #define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI1__MAX_BW_MASK … #define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI1__MIN_BW_MASK … #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI1__MAX_OSD_MASK … //DAGB0_WRCLI2 #define DAGB0_WRCLI2__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI2__URG_HIGH__SHIFT … #define DAGB0_WRCLI2__URG_LOW__SHIFT … #define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI2__MAX_BW__SHIFT … #define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI2__MIN_BW__SHIFT … #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI2__MAX_OSD__SHIFT … #define DAGB0_WRCLI2__VIRT_CHAN_MASK … #define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI2__URG_HIGH_MASK … #define DAGB0_WRCLI2__URG_LOW_MASK … #define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI2__MAX_BW_MASK … #define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI2__MIN_BW_MASK … #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI2__MAX_OSD_MASK … //DAGB0_WRCLI3 #define DAGB0_WRCLI3__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI3__URG_HIGH__SHIFT … #define DAGB0_WRCLI3__URG_LOW__SHIFT … #define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI3__MAX_BW__SHIFT … #define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI3__MIN_BW__SHIFT … #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI3__MAX_OSD__SHIFT … #define DAGB0_WRCLI3__VIRT_CHAN_MASK … #define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI3__URG_HIGH_MASK … #define DAGB0_WRCLI3__URG_LOW_MASK … #define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI3__MAX_BW_MASK … #define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI3__MIN_BW_MASK … #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI3__MAX_OSD_MASK … //DAGB0_WRCLI4 #define DAGB0_WRCLI4__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI4__URG_HIGH__SHIFT … #define DAGB0_WRCLI4__URG_LOW__SHIFT … #define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI4__MAX_BW__SHIFT … #define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI4__MIN_BW__SHIFT … #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI4__MAX_OSD__SHIFT … #define DAGB0_WRCLI4__VIRT_CHAN_MASK … #define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI4__URG_HIGH_MASK … #define DAGB0_WRCLI4__URG_LOW_MASK … #define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI4__MAX_BW_MASK … #define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI4__MIN_BW_MASK … #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI4__MAX_OSD_MASK … //DAGB0_WRCLI5 #define DAGB0_WRCLI5__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI5__URG_HIGH__SHIFT … #define DAGB0_WRCLI5__URG_LOW__SHIFT … #define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI5__MAX_BW__SHIFT … #define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI5__MIN_BW__SHIFT … #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI5__MAX_OSD__SHIFT … #define DAGB0_WRCLI5__VIRT_CHAN_MASK … #define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI5__URG_HIGH_MASK … #define DAGB0_WRCLI5__URG_LOW_MASK … #define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI5__MAX_BW_MASK … #define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI5__MIN_BW_MASK … #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI5__MAX_OSD_MASK … //DAGB0_WRCLI6 #define DAGB0_WRCLI6__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI6__URG_HIGH__SHIFT … #define DAGB0_WRCLI6__URG_LOW__SHIFT … #define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI6__MAX_BW__SHIFT … #define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI6__MIN_BW__SHIFT … #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI6__MAX_OSD__SHIFT … #define DAGB0_WRCLI6__VIRT_CHAN_MASK … #define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI6__URG_HIGH_MASK … #define DAGB0_WRCLI6__URG_LOW_MASK … #define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI6__MAX_BW_MASK … #define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI6__MIN_BW_MASK … #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI6__MAX_OSD_MASK … //DAGB0_WRCLI7 #define DAGB0_WRCLI7__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI7__URG_HIGH__SHIFT … #define DAGB0_WRCLI7__URG_LOW__SHIFT … #define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI7__MAX_BW__SHIFT … #define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI7__MIN_BW__SHIFT … #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI7__MAX_OSD__SHIFT … #define DAGB0_WRCLI7__VIRT_CHAN_MASK … #define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI7__URG_HIGH_MASK … #define DAGB0_WRCLI7__URG_LOW_MASK … #define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI7__MAX_BW_MASK … #define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI7__MIN_BW_MASK … #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI7__MAX_OSD_MASK … //DAGB0_WRCLI8 #define DAGB0_WRCLI8__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI8__URG_HIGH__SHIFT … #define DAGB0_WRCLI8__URG_LOW__SHIFT … #define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI8__MAX_BW__SHIFT … #define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI8__MIN_BW__SHIFT … #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI8__MAX_OSD__SHIFT … #define DAGB0_WRCLI8__VIRT_CHAN_MASK … #define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI8__URG_HIGH_MASK … #define DAGB0_WRCLI8__URG_LOW_MASK … #define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI8__MAX_BW_MASK … #define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI8__MIN_BW_MASK … #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI8__MAX_OSD_MASK … //DAGB0_WRCLI9 #define DAGB0_WRCLI9__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI9__URG_HIGH__SHIFT … #define DAGB0_WRCLI9__URG_LOW__SHIFT … #define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI9__MAX_BW__SHIFT … #define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI9__MIN_BW__SHIFT … #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI9__MAX_OSD__SHIFT … #define DAGB0_WRCLI9__VIRT_CHAN_MASK … #define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI9__URG_HIGH_MASK … #define DAGB0_WRCLI9__URG_LOW_MASK … #define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI9__MAX_BW_MASK … #define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI9__MIN_BW_MASK … #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI9__MAX_OSD_MASK … //DAGB0_WRCLI10 #define DAGB0_WRCLI10__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI10__URG_HIGH__SHIFT … #define DAGB0_WRCLI10__URG_LOW__SHIFT … #define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI10__MAX_BW__SHIFT … #define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI10__MIN_BW__SHIFT … #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI10__MAX_OSD__SHIFT … #define DAGB0_WRCLI10__VIRT_CHAN_MASK … #define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI10__URG_HIGH_MASK … #define DAGB0_WRCLI10__URG_LOW_MASK … #define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI10__MAX_BW_MASK … #define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI10__MIN_BW_MASK … #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI10__MAX_OSD_MASK … //DAGB0_WRCLI11 #define DAGB0_WRCLI11__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI11__URG_HIGH__SHIFT … #define DAGB0_WRCLI11__URG_LOW__SHIFT … #define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI11__MAX_BW__SHIFT … #define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI11__MIN_BW__SHIFT … #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI11__MAX_OSD__SHIFT … #define DAGB0_WRCLI11__VIRT_CHAN_MASK … #define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI11__URG_HIGH_MASK … #define DAGB0_WRCLI11__URG_LOW_MASK … #define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI11__MAX_BW_MASK … #define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI11__MIN_BW_MASK … #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI11__MAX_OSD_MASK … //DAGB0_WRCLI12 #define DAGB0_WRCLI12__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI12__URG_HIGH__SHIFT … #define DAGB0_WRCLI12__URG_LOW__SHIFT … #define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI12__MAX_BW__SHIFT … #define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI12__MIN_BW__SHIFT … #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI12__MAX_OSD__SHIFT … #define DAGB0_WRCLI12__VIRT_CHAN_MASK … #define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI12__URG_HIGH_MASK … #define DAGB0_WRCLI12__URG_LOW_MASK … #define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI12__MAX_BW_MASK … #define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI12__MIN_BW_MASK … #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI12__MAX_OSD_MASK … //DAGB0_WRCLI13 #define DAGB0_WRCLI13__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI13__URG_HIGH__SHIFT … #define DAGB0_WRCLI13__URG_LOW__SHIFT … #define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI13__MAX_BW__SHIFT … #define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI13__MIN_BW__SHIFT … #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI13__MAX_OSD__SHIFT … #define DAGB0_WRCLI13__VIRT_CHAN_MASK … #define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI13__URG_HIGH_MASK … #define DAGB0_WRCLI13__URG_LOW_MASK … #define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI13__MAX_BW_MASK … #define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI13__MIN_BW_MASK … #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI13__MAX_OSD_MASK … //DAGB0_WRCLI14 #define DAGB0_WRCLI14__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI14__URG_HIGH__SHIFT … #define DAGB0_WRCLI14__URG_LOW__SHIFT … #define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI14__MAX_BW__SHIFT … #define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI14__MIN_BW__SHIFT … #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI14__MAX_OSD__SHIFT … #define DAGB0_WRCLI14__VIRT_CHAN_MASK … #define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI14__URG_HIGH_MASK … #define DAGB0_WRCLI14__URG_LOW_MASK … #define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI14__MAX_BW_MASK … #define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI14__MIN_BW_MASK … #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI14__MAX_OSD_MASK … //DAGB0_WRCLI15 #define DAGB0_WRCLI15__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI15__URG_HIGH__SHIFT … #define DAGB0_WRCLI15__URG_LOW__SHIFT … #define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI15__MAX_BW__SHIFT … #define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI15__MIN_BW__SHIFT … #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI15__MAX_OSD__SHIFT … #define DAGB0_WRCLI15__VIRT_CHAN_MASK … #define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI15__URG_HIGH_MASK … #define DAGB0_WRCLI15__URG_LOW_MASK … #define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI15__MAX_BW_MASK … #define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI15__MIN_BW_MASK … #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI15__MAX_OSD_MASK … //DAGB0_WRCLI16 #define DAGB0_WRCLI16__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI16__URG_HIGH__SHIFT … #define DAGB0_WRCLI16__URG_LOW__SHIFT … #define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI16__MAX_BW__SHIFT … #define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI16__MIN_BW__SHIFT … #define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI16__MAX_OSD__SHIFT … #define DAGB0_WRCLI16__VIRT_CHAN_MASK … #define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI16__URG_HIGH_MASK … #define DAGB0_WRCLI16__URG_LOW_MASK … #define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI16__MAX_BW_MASK … #define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI16__MIN_BW_MASK … #define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI16__MAX_OSD_MASK … //DAGB0_WRCLI17 #define DAGB0_WRCLI17__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI17__URG_HIGH__SHIFT … #define DAGB0_WRCLI17__URG_LOW__SHIFT … #define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI17__MAX_BW__SHIFT … #define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI17__MIN_BW__SHIFT … #define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI17__MAX_OSD__SHIFT … #define DAGB0_WRCLI17__VIRT_CHAN_MASK … #define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI17__URG_HIGH_MASK … #define DAGB0_WRCLI17__URG_LOW_MASK … #define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI17__MAX_BW_MASK … #define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI17__MIN_BW_MASK … #define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI17__MAX_OSD_MASK … //DAGB0_WRCLI18 #define DAGB0_WRCLI18__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI18__URG_HIGH__SHIFT … #define DAGB0_WRCLI18__URG_LOW__SHIFT … #define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI18__MAX_BW__SHIFT … #define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI18__MIN_BW__SHIFT … #define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI18__MAX_OSD__SHIFT … #define DAGB0_WRCLI18__VIRT_CHAN_MASK … #define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI18__URG_HIGH_MASK … #define DAGB0_WRCLI18__URG_LOW_MASK … #define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI18__MAX_BW_MASK … #define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI18__MIN_BW_MASK … #define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI18__MAX_OSD_MASK … //DAGB0_WRCLI19 #define DAGB0_WRCLI19__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI19__URG_HIGH__SHIFT … #define DAGB0_WRCLI19__URG_LOW__SHIFT … #define DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI19__MAX_BW__SHIFT … #define DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI19__MIN_BW__SHIFT … #define DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI19__MAX_OSD__SHIFT … #define DAGB0_WRCLI19__VIRT_CHAN_MASK … #define DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI19__URG_HIGH_MASK … #define DAGB0_WRCLI19__URG_LOW_MASK … #define DAGB0_WRCLI19__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI19__MAX_BW_MASK … #define DAGB0_WRCLI19__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI19__MIN_BW_MASK … #define DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI19__MAX_OSD_MASK … //DAGB0_WRCLI20 #define DAGB0_WRCLI20__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI20__URG_HIGH__SHIFT … #define DAGB0_WRCLI20__URG_LOW__SHIFT … #define DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI20__MAX_BW__SHIFT … #define DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI20__MIN_BW__SHIFT … #define DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI20__MAX_OSD__SHIFT … #define DAGB0_WRCLI20__VIRT_CHAN_MASK … #define DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI20__URG_HIGH_MASK … #define DAGB0_WRCLI20__URG_LOW_MASK … #define DAGB0_WRCLI20__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI20__MAX_BW_MASK … #define DAGB0_WRCLI20__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI20__MIN_BW_MASK … #define DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI20__MAX_OSD_MASK … //DAGB0_WRCLI21 #define DAGB0_WRCLI21__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI21__URG_HIGH__SHIFT … #define DAGB0_WRCLI21__URG_LOW__SHIFT … #define DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI21__MAX_BW__SHIFT … #define DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI21__MIN_BW__SHIFT … #define DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI21__MAX_OSD__SHIFT … #define DAGB0_WRCLI21__VIRT_CHAN_MASK … #define DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI21__URG_HIGH_MASK … #define DAGB0_WRCLI21__URG_LOW_MASK … #define DAGB0_WRCLI21__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI21__MAX_BW_MASK … #define DAGB0_WRCLI21__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI21__MIN_BW_MASK … #define DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI21__MAX_OSD_MASK … //DAGB0_WRCLI22 #define DAGB0_WRCLI22__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI22__URG_HIGH__SHIFT … #define DAGB0_WRCLI22__URG_LOW__SHIFT … #define DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI22__MAX_BW__SHIFT … #define DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI22__MIN_BW__SHIFT … #define DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI22__MAX_OSD__SHIFT … #define DAGB0_WRCLI22__VIRT_CHAN_MASK … #define DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI22__URG_HIGH_MASK … #define DAGB0_WRCLI22__URG_LOW_MASK … #define DAGB0_WRCLI22__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI22__MAX_BW_MASK … #define DAGB0_WRCLI22__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI22__MIN_BW_MASK … #define DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI22__MAX_OSD_MASK … //DAGB0_WRCLI23 #define DAGB0_WRCLI23__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI23__URG_HIGH__SHIFT … #define DAGB0_WRCLI23__URG_LOW__SHIFT … #define DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI23__MAX_BW__SHIFT … #define DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI23__MIN_BW__SHIFT … #define DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI23__MAX_OSD__SHIFT … #define DAGB0_WRCLI23__VIRT_CHAN_MASK … #define DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI23__URG_HIGH_MASK … #define DAGB0_WRCLI23__URG_LOW_MASK … #define DAGB0_WRCLI23__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI23__MAX_BW_MASK … #define DAGB0_WRCLI23__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI23__MIN_BW_MASK … #define DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI23__MAX_OSD_MASK … //DAGB0_WRCLI24 #define DAGB0_WRCLI24__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI24__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI24__URG_HIGH__SHIFT … #define DAGB0_WRCLI24__URG_LOW__SHIFT … #define DAGB0_WRCLI24__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI24__MAX_BW__SHIFT … #define DAGB0_WRCLI24__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI24__MIN_BW__SHIFT … #define DAGB0_WRCLI24__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI24__MAX_OSD__SHIFT … #define DAGB0_WRCLI24__VIRT_CHAN_MASK … #define DAGB0_WRCLI24__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI24__URG_HIGH_MASK … #define DAGB0_WRCLI24__URG_LOW_MASK … #define DAGB0_WRCLI24__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI24__MAX_BW_MASK … #define DAGB0_WRCLI24__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI24__MIN_BW_MASK … #define DAGB0_WRCLI24__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI24__MAX_OSD_MASK … //DAGB0_WRCLI25 #define DAGB0_WRCLI25__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI25__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI25__URG_HIGH__SHIFT … #define DAGB0_WRCLI25__URG_LOW__SHIFT … #define DAGB0_WRCLI25__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI25__MAX_BW__SHIFT … #define DAGB0_WRCLI25__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI25__MIN_BW__SHIFT … #define DAGB0_WRCLI25__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI25__MAX_OSD__SHIFT … #define DAGB0_WRCLI25__VIRT_CHAN_MASK … #define DAGB0_WRCLI25__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI25__URG_HIGH_MASK … #define DAGB0_WRCLI25__URG_LOW_MASK … #define DAGB0_WRCLI25__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI25__MAX_BW_MASK … #define DAGB0_WRCLI25__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI25__MIN_BW_MASK … #define DAGB0_WRCLI25__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI25__MAX_OSD_MASK … //DAGB0_WRCLI26 #define DAGB0_WRCLI26__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI26__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI26__URG_HIGH__SHIFT … #define DAGB0_WRCLI26__URG_LOW__SHIFT … #define DAGB0_WRCLI26__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI26__MAX_BW__SHIFT … #define DAGB0_WRCLI26__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI26__MIN_BW__SHIFT … #define DAGB0_WRCLI26__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI26__MAX_OSD__SHIFT … #define DAGB0_WRCLI26__VIRT_CHAN_MASK … #define DAGB0_WRCLI26__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI26__URG_HIGH_MASK … #define DAGB0_WRCLI26__URG_LOW_MASK … #define DAGB0_WRCLI26__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI26__MAX_BW_MASK … #define DAGB0_WRCLI26__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI26__MIN_BW_MASK … #define DAGB0_WRCLI26__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI26__MAX_OSD_MASK … //DAGB0_WRCLI27 #define DAGB0_WRCLI27__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI27__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI27__URG_HIGH__SHIFT … #define DAGB0_WRCLI27__URG_LOW__SHIFT … #define DAGB0_WRCLI27__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI27__MAX_BW__SHIFT … #define DAGB0_WRCLI27__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI27__MIN_BW__SHIFT … #define DAGB0_WRCLI27__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI27__MAX_OSD__SHIFT … #define DAGB0_WRCLI27__VIRT_CHAN_MASK … #define DAGB0_WRCLI27__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI27__URG_HIGH_MASK … #define DAGB0_WRCLI27__URG_LOW_MASK … #define DAGB0_WRCLI27__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI27__MAX_BW_MASK … #define DAGB0_WRCLI27__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI27__MIN_BW_MASK … #define DAGB0_WRCLI27__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI27__MAX_OSD_MASK … //DAGB0_WRCLI28 #define DAGB0_WRCLI28__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI28__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI28__URG_HIGH__SHIFT … #define DAGB0_WRCLI28__URG_LOW__SHIFT … #define DAGB0_WRCLI28__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI28__MAX_BW__SHIFT … #define DAGB0_WRCLI28__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI28__MIN_BW__SHIFT … #define DAGB0_WRCLI28__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI28__MAX_OSD__SHIFT … #define DAGB0_WRCLI28__VIRT_CHAN_MASK … #define DAGB0_WRCLI28__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI28__URG_HIGH_MASK … #define DAGB0_WRCLI28__URG_LOW_MASK … #define DAGB0_WRCLI28__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI28__MAX_BW_MASK … #define DAGB0_WRCLI28__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI28__MIN_BW_MASK … #define DAGB0_WRCLI28__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI28__MAX_OSD_MASK … //DAGB0_WRCLI29 #define DAGB0_WRCLI29__VIRT_CHAN__SHIFT … #define DAGB0_WRCLI29__CHECK_TLB_CREDIT__SHIFT … #define DAGB0_WRCLI29__URG_HIGH__SHIFT … #define DAGB0_WRCLI29__URG_LOW__SHIFT … #define DAGB0_WRCLI29__MAX_BW_ENABLE__SHIFT … #define DAGB0_WRCLI29__MAX_BW__SHIFT … #define DAGB0_WRCLI29__MIN_BW_ENABLE__SHIFT … #define DAGB0_WRCLI29__MIN_BW__SHIFT … #define DAGB0_WRCLI29__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WRCLI29__MAX_OSD__SHIFT … #define DAGB0_WRCLI29__VIRT_CHAN_MASK … #define DAGB0_WRCLI29__CHECK_TLB_CREDIT_MASK … #define DAGB0_WRCLI29__URG_HIGH_MASK … #define DAGB0_WRCLI29__URG_LOW_MASK … #define DAGB0_WRCLI29__MAX_BW_ENABLE_MASK … #define DAGB0_WRCLI29__MAX_BW_MASK … #define DAGB0_WRCLI29__MIN_BW_ENABLE_MASK … #define DAGB0_WRCLI29__MIN_BW_MASK … #define DAGB0_WRCLI29__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WRCLI29__MAX_OSD_MASK … //DAGB0_WR_CNTL #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT … #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT … #define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN__SHIFT … #define DAGB0_WR_CNTL__UPDATE_FED__SHIFT … #define DAGB0_WR_CNTL__UPDATE_NACK__SHIFT … #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK … #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK … #define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN_MASK … #define DAGB0_WR_CNTL__UPDATE_FED_MASK … #define DAGB0_WR_CNTL__UPDATE_NACK_MASK … //DAGB0_WR_IO_CNTL #define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE__SHIFT … #define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT … #define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT … #define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE__SHIFT … #define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT … #define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT … #define DAGB0_WR_IO_CNTL__COMMON_PRIORITY__SHIFT … #define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE_MASK … #define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY_MASK … #define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK … #define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE_MASK … #define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY_MASK … #define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK … #define DAGB0_WR_IO_CNTL__COMMON_PRIORITY_MASK … //DAGB0_WR_GMI_CNTL #define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT … #define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT … #define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT … #define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT … #define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT … #define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT … #define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY__SHIFT … #define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE_MASK … #define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY_MASK … #define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK … #define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE_MASK … #define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY_MASK … #define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK … #define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY_MASK … //DAGB0_WR_ADDR_DAGB #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT … #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT … #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT … #define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT … #define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT … #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK … #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK … #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK … #define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK … #define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK … //DAGB0_WR_CGTT_CLK_CTRL #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT … #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT … #define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT … #define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT … #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK … #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK … #define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK … #define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK … #define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK … //DAGB0_L1TLB_WR_CGTT_CLK_CTRL #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT … #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT … #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT … #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT … #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK … #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK … #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK … #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK … #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK … //DAGB0_WR_ADDR_DAGB_MAX_BURST0 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK … //DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK … //DAGB0_WR_ADDR_DAGB_MAX_BURST1 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK … //DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK … //DAGB0_WR_ADDR_DAGB_MAX_BURST2 #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK … //DAGB0_WR_ADDR_DAGB_LAZY_TIMER2 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK … //DAGB0_WR_ADDR_DAGB_MAX_BURST3 #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT … #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK … #define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK … //DAGB0_WR_ADDR_DAGB_LAZY_TIMER3 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK … #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK … //DAGB0_WR_DATA_DAGB #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT … #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT … #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT … #define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT … #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK … #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK … #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK … #define DAGB0_WR_DATA_DAGB__WHOAMI_MASK … //DAGB0_WR_DATA_DAGB_MAX_BURST0 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK … //DAGB0_WR_DATA_DAGB_LAZY_TIMER0 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK … //DAGB0_WR_DATA_DAGB_MAX_BURST1 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK … //DAGB0_WR_DATA_DAGB_LAZY_TIMER1 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK … //DAGB0_WR_DATA_DAGB_MAX_BURST2 #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK … //DAGB0_WR_DATA_DAGB_LAZY_TIMER2 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK … //DAGB0_WR_DATA_DAGB_MAX_BURST3 #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31__SHIFT … #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30_MASK … #define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31_MASK … //DAGB0_WR_DATA_DAGB_LAZY_TIMER3 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31__SHIFT … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30_MASK … #define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31_MASK … //DAGB0_WR_VC0_CNTL #define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT … #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT … #define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT … #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT … #define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT … #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT … #define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK … #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK … #define DAGB0_WR_VC0_CNTL__MAX_BW_MASK … #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK … #define DAGB0_WR_VC0_CNTL__MIN_BW_MASK … #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK … //DAGB0_WR_VC1_CNTL #define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT … #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT … #define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT … #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT … #define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT … #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT … #define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK … #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK … #define DAGB0_WR_VC1_CNTL__MAX_BW_MASK … #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK … #define DAGB0_WR_VC1_CNTL__MIN_BW_MASK … #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK … //DAGB0_WR_VC2_CNTL #define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT … #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT … #define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT … #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT … #define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT … #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT … #define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK … #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK … #define DAGB0_WR_VC2_CNTL__MAX_BW_MASK … #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK … #define DAGB0_WR_VC2_CNTL__MIN_BW_MASK … #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK … //DAGB0_WR_VC3_CNTL #define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT … #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT … #define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT … #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT … #define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT … #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT … #define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK … #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK … #define DAGB0_WR_VC3_CNTL__MAX_BW_MASK … #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK … #define DAGB0_WR_VC3_CNTL__MIN_BW_MASK … #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK … //DAGB0_WR_VC4_CNTL #define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT … #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT … #define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT … #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT … #define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT … #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT … #define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK … #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK … #define DAGB0_WR_VC4_CNTL__MAX_BW_MASK … #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK … #define DAGB0_WR_VC4_CNTL__MIN_BW_MASK … #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK … //DAGB0_WR_VC5_CNTL #define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT … #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT … #define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT … #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT … #define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT … #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT … #define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK … #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK … #define DAGB0_WR_VC5_CNTL__MAX_BW_MASK … #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK … #define DAGB0_WR_VC5_CNTL__MIN_BW_MASK … #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK … //DAGB0_WR_IO_VC_CNTL #define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT … #define DAGB0_WR_IO_VC_CNTL__MAX_BW__SHIFT … #define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT … #define DAGB0_WR_IO_VC_CNTL__MIN_BW__SHIFT … #define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WR_IO_VC_CNTL__MAX_OSD__SHIFT … #define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE_MASK … #define DAGB0_WR_IO_VC_CNTL__MAX_BW_MASK … #define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE_MASK … #define DAGB0_WR_IO_VC_CNTL__MIN_BW_MASK … #define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WR_IO_VC_CNTL__MAX_OSD_MASK … //DAGB0_WR_GMI_VC_CNTL #define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT … #define DAGB0_WR_GMI_VC_CNTL__MAX_BW__SHIFT … #define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT … #define DAGB0_WR_GMI_VC_CNTL__MIN_BW__SHIFT … #define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT … #define DAGB0_WR_GMI_VC_CNTL__MAX_OSD__SHIFT … #define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE_MASK … #define DAGB0_WR_GMI_VC_CNTL__MAX_BW_MASK … #define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE_MASK … #define DAGB0_WR_GMI_VC_CNTL__MIN_BW_MASK … #define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK … #define DAGB0_WR_GMI_VC_CNTL__MAX_OSD_MASK … //DAGB0_WR_CNTL_MISC #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT … #define DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT … #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK … #define DAGB0_WR_CNTL_MISC__HDP_CID_MASK … //DAGB0_WR_TLB_CREDIT #define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT … #define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT … #define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT … #define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT … #define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT … #define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT … #define DAGB0_WR_TLB_CREDIT__TLB0_MASK … #define DAGB0_WR_TLB_CREDIT__TLB1_MASK … #define DAGB0_WR_TLB_CREDIT__TLB2_MASK … #define DAGB0_WR_TLB_CREDIT__TLB3_MASK … #define DAGB0_WR_TLB_CREDIT__TLB4_MASK … #define DAGB0_WR_TLB_CREDIT__TLB5_MASK … //DAGB0_WR_DATA_CREDIT #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT … #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT … #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT … #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT … #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK … #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK … #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK … #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK … //DAGB0_WR_MISC_CREDIT #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT … #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT … #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK … #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK … //DAGB0_WR_DATA_FIFO_CREDIT_CNTL1 #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT … #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT … #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT … #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT … #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT … #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT … #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT … #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0__SHIFT … #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK … #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK … #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK … #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK … #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK … #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE_MASK … #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ_MASK … #define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0_MASK … //DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT … #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT … #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT … #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT … #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT … #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT … #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT … #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT … #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK … #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK … #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK … #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK … #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK … #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK … #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK … #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK … //DAGB0_WRCLI_ASK_PENDING #define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT … #define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK … //DAGB0_WRCLI_GO_PENDING #define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT … #define DAGB0_WRCLI_GO_PENDING__BUSY_MASK … //DAGB0_WRCLI_GBLSEND_PENDING #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT … #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK … //DAGB0_WRCLI_TLB_PENDING #define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT … #define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK … //DAGB0_WRCLI_OARB_PENDING #define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT … #define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK … //DAGB0_WRCLI_ASK2ARB_PENDING #define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY__SHIFT … #define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY_MASK … //DAGB0_WRCLI_ASK2DF_PENDING #define DAGB0_WRCLI_ASK2DF_PENDING__BUSY__SHIFT … #define DAGB0_WRCLI_ASK2DF_PENDING__BUSY_MASK … //DAGB0_WRCLI_OSD_PENDING #define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT … #define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK … //DAGB0_WRCLI_ASK_OSD_PENDING #define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY__SHIFT … #define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY_MASK … //DAGB0_WRCLI_DBUS_ASK_PENDING #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT … #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK … //DAGB0_WRCLI_DBUS_GO_PENDING #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT … #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK … //DAGB0_WRCLI_GPU_SNOOP_OVERRIDE #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT … #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK … //DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT … #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK … //DAGB0_DAGB_DLY #define DAGB0_DAGB_DLY__DLY__SHIFT … #define DAGB0_DAGB_DLY__CLI__SHIFT … #define DAGB0_DAGB_DLY__POS__SHIFT … #define DAGB0_DAGB_DLY__DLY_MASK … #define DAGB0_DAGB_DLY__CLI_MASK … #define DAGB0_DAGB_DLY__POS_MASK … //DAGB0_CNTL_MISC #define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT … #define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK … //DAGB0_CNTL_MISC2 #define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT … #define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT … #define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT … #define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT … #define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT … #define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT … #define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT … #define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT … #define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT … #define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT … #define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT … #define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT … #define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK … #define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK … #define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK … #define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK … #define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK … #define DAGB0_CNTL_MISC2__SWAP_CTL_MASK … #define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK … #define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK … #define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK … #define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK … #define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK … #define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK … //DAGB0_FIFO_EMPTY #define DAGB0_FIFO_EMPTY__EMPTY__SHIFT … #define DAGB0_FIFO_EMPTY__EMPTY_MASK … //DAGB0_FIFO_FULL #define DAGB0_FIFO_FULL__FULL__SHIFT … #define DAGB0_FIFO_FULL__FULL_MASK … //DAGB0_RD_CREDITS_FULL #define DAGB0_RD_CREDITS_FULL__FULL__SHIFT … #define DAGB0_RD_CREDITS_FULL__FULL_MASK … //DAGB0_WR_CREDITS_FULL #define DAGB0_WR_CREDITS_FULL__FULL__SHIFT … #define DAGB0_WR_CREDITS_FULL__FULL_MASK … //DAGB0_PERFCOUNTER_LO #define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT … #define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK … //DAGB0_PERFCOUNTER_HI #define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT … #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT … #define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK … #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK … //DAGB0_PERFCOUNTER0_CFG #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT … #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT … #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT … #define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT … #define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT … #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK … #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK … #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK … #define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK … #define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK … //DAGB0_PERFCOUNTER1_CFG #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT … #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT … #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT … #define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT … #define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT … #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK … #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK … #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK … #define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK … #define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK … //DAGB0_PERFCOUNTER2_CFG #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT … #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT … #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT … #define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT … #define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT … #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK … #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK … #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK … #define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK … #define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK … //DAGB0_PERFCOUNTER_RSLT_CNTL #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT … #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT … #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT … #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT … #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT … #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT … #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK … #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK … #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK … #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK … #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK … #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK … //DAGB0_L1TLB_REG_RW #define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT … #define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT … #define DAGB0_L1TLB_REG_RW__RESERVE__SHIFT … #define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK … #define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK … #define DAGB0_L1TLB_REG_RW__RESERVE_MASK … //DAGB0_RESERVE1 #define DAGB0_RESERVE1__RESERVE__SHIFT … #define DAGB0_RESERVE1__RESERVE_MASK … //DAGB0_RESERVE2 #define DAGB0_RESERVE2__RESERVE__SHIFT … #define DAGB0_RESERVE2__RESERVE_MASK … //DAGB0_RESERVE3 #define DAGB0_RESERVE3__RESERVE__SHIFT … #define DAGB0_RESERVE3__RESERVE_MASK … //DAGB0_RESERVE4 #define DAGB0_RESERVE4__RESERVE__SHIFT … #define DAGB0_RESERVE4__RESERVE_MASK … //DAGB0_SDP_RD_BW_CNTL #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT … #define DAGB0_SDP_RD_BW_CNTL__MAX_BW__SHIFT … #define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT … #define DAGB0_SDP_RD_BW_CNTL__MIN_BW__SHIFT … #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT … #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK … #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_MASK … #define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK … #define DAGB0_SDP_RD_BW_CNTL__MIN_BW_MASK … #define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK … //DAGB0_SDP_PRIORITY_OVERRIDE #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK … #define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK … //DAGB0_SDP_RD_PRIORITY #define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT … #define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT … #define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT … #define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT … #define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT … #define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT … #define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK … #define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK … #define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK … #define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK … #define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK … #define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK … //DAGB0_SDP_WR_PRIORITY #define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY__SHIFT … #define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY__SHIFT … #define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY__SHIFT … #define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY__SHIFT … #define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY__SHIFT … #define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY__SHIFT … #define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY_MASK … #define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY_MASK … #define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY_MASK … #define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY_MASK … #define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY_MASK … #define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY_MASK … //DAGB0_SDP_RD_CLI2SDP_VC_MAP #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT … #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT … #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT … #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT … #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT … #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT … #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK … #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK … #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK … #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK … #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK … #define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK … //DAGB0_SDP_WR_CLI2SDP_VC_MAP #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT … #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT … #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT … #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT … #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT … #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT … #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK … #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK … #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK … #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK … #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP_MASK … #define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK … //DAGB0_SDP_ENABLE #define DAGB0_SDP_ENABLE__ENABLE__SHIFT … #define DAGB0_SDP_ENABLE__ENABLE_MASK … //DAGB0_SDP_CREDITS #define DAGB0_SDP_CREDITS__TAG_LIMIT__SHIFT … #define DAGB0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT … #define DAGB0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT … #define DAGB0_SDP_CREDITS__TAG_LIMIT_MASK … #define DAGB0_SDP_CREDITS__WR_RESP_CREDITS_MASK … #define DAGB0_SDP_CREDITS__RD_RESP_CREDITS_MASK … //DAGB0_SDP_TAG_RESERVE0 #define DAGB0_SDP_TAG_RESERVE0__VC0__SHIFT … #define DAGB0_SDP_TAG_RESERVE0__VC1__SHIFT … #define DAGB0_SDP_TAG_RESERVE0__VC2__SHIFT … #define DAGB0_SDP_TAG_RESERVE0__VC3__SHIFT … #define DAGB0_SDP_TAG_RESERVE0__VC0_MASK … #define DAGB0_SDP_TAG_RESERVE0__VC1_MASK … #define DAGB0_SDP_TAG_RESERVE0__VC2_MASK … #define DAGB0_SDP_TAG_RESERVE0__VC3_MASK … //DAGB0_SDP_TAG_RESERVE1 #define DAGB0_SDP_TAG_RESERVE1__VC4__SHIFT … #define DAGB0_SDP_TAG_RESERVE1__VC5__SHIFT … #define DAGB0_SDP_TAG_RESERVE1__VC6__SHIFT … #define DAGB0_SDP_TAG_RESERVE1__VC7__SHIFT … #define DAGB0_SDP_TAG_RESERVE1__VC4_MASK … #define DAGB0_SDP_TAG_RESERVE1__VC5_MASK … #define DAGB0_SDP_TAG_RESERVE1__VC6_MASK … #define DAGB0_SDP_TAG_RESERVE1__VC7_MASK … //DAGB0_SDP_VCC_RESERVE0 #define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT … #define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT … #define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT … #define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT … #define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT … #define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK … #define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK … #define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK … #define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK … #define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK … //DAGB0_SDP_VCC_RESERVE1 #define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT … #define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT … #define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT … #define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT … #define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK … #define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK … #define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK … #define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK … //DAGB0_SDP_ERR_STATUS #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT … #define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT … #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT … #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT … #define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT … #define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT … #define DAGB0_SDP_ERR_STATUS__FUE_FLAG__SHIFT … #define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT … #define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT … #define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT … #define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT … #define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT … #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK … #define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK … #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK … #define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK … #define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK … #define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK … #define DAGB0_SDP_ERR_STATUS__FUE_FLAG_MASK … #define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK … #define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK … #define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK … #define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK … #define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK … //DAGB0_SDP_REQ_CNTL #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT … #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT … #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT … #define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT … #define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT … #define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT … #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT … #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT … #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT … #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK … #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK … #define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK … #define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK … #define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK … #define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK … #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK … #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK … #define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK … //DAGB0_SDP_MISC_AON #define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT … #define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT … #define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK … #define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK … //DAGB0_SDP_MISC #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT … #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT … #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT … #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT … #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT … #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT … #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT … #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT … #define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT … #define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT … #define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT … #define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT … #define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT … #define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT … #define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT … #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK … #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK … #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK … #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK … #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK … #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK … #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK … #define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK … #define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA_MASK … #define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK … #define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK … #define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK … #define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK … #define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK … #define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK … //DAGB0_SDP_MISC2 #define DAGB0_SDP_MISC2__RRET_SWAP_MODE__SHIFT … #define DAGB0_SDP_MISC2__BLOCK_REQUESTS__SHIFT … #define DAGB0_SDP_MISC2__REQUESTS_BLOCKED__SHIFT … #define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT … #define DAGB0_SDP_MISC2__RRET_SWAP_MODE_MASK … #define DAGB0_SDP_MISC2__BLOCK_REQUESTS_MASK … #define DAGB0_SDP_MISC2__REQUESTS_BLOCKED_MASK … #define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK … //DAGB0_SDP_VCD_RESERVE0 #define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT … #define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT … #define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT … #define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT … #define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT … #define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK … #define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK … #define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK … #define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK … #define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK … //DAGB0_SDP_VCD_RESERVE1 #define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT … #define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT … #define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT … #define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT … #define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK … #define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK … #define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK … #define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK … //DAGB0_SDP_ARB_CNTL0 #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT … #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT … #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT … #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT … #define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT … #define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT … #define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT … #define DAGB0_SDP_ARB_CNTL0__DED_MODE__SHIFT … #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK … #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK … #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK … #define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK … #define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK … #define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK … #define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK … #define DAGB0_SDP_ARB_CNTL0__DED_MODE_MASK … //DAGB0_SDP_ARB_CNTL1 #define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT … #define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT … #define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT … #define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT … #define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK … #define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK … #define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK … #define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK … //DAGB0_SDP_CGTT_CLK_CTRL #define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT … #define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT … #define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT … #define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT … #define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK … #define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK … #define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK … #define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK … #define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK … //DAGB0_SDP_LATENCY_SAMPLING #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK … #define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK … // addressBlock: mmhub_pctldec //PCTL_CTRL #define PCTL_CTRL__PG_ENABLE__SHIFT … #define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT … #define PCTL_CTRL__RSMU_RDTIMER_ENABLE__SHIFT … #define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD__SHIFT … #define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT … #define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT … #define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT … #define PCTL_CTRL__UTCL2_LEGACY_MODE__SHIFT … #define PCTL_CTRL__SDP_DISCONNECT_MODE__SHIFT … #define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD__SHIFT … #define PCTL_CTRL__ZSC_TIMER_ENABLE__SHIFT … #define PCTL_CTRL__Z9_PWRDOWN__SHIFT … #define PCTL_CTRL__Z9_PWRUP__SHIFT … #define PCTL_CTRL__SNR_DISABLE__SHIFT … #define PCTL_CTRL__WRACK_GUARD__SHIFT … #define PCTL_CTRL__PG_ENABLE_MASK … #define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK … #define PCTL_CTRL__RSMU_RDTIMER_ENABLE_MASK … #define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD_MASK … #define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK … #define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK … #define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK … #define PCTL_CTRL__UTCL2_LEGACY_MODE_MASK … #define PCTL_CTRL__SDP_DISCONNECT_MODE_MASK … #define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD_MASK … #define PCTL_CTRL__ZSC_TIMER_ENABLE_MASK … #define PCTL_CTRL__Z9_PWRDOWN_MASK … #define PCTL_CTRL__Z9_PWRUP_MASK … #define PCTL_CTRL__SNR_DISABLE_MASK … #define PCTL_CTRL__WRACK_GUARD_MASK … //PCTL_MMHUB_DEEPSLEEP_IB #define PCTL_MMHUB_DEEPSLEEP_IB__DS0__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_IB__DS1__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_IB__DS2__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_IB__DS3__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_IB__DS4__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_IB__DS5__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_IB__DS6__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_IB__DS7__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_IB__DS8__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_IB__DS9__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_IB__DS10__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_IB__DS11__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_IB__DS12__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_IB__DS13__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_IB__DS14__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_IB__DS15__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_IB__DS16__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_IB__DS0_MASK … #define PCTL_MMHUB_DEEPSLEEP_IB__DS1_MASK … #define PCTL_MMHUB_DEEPSLEEP_IB__DS2_MASK … #define PCTL_MMHUB_DEEPSLEEP_IB__DS3_MASK … #define PCTL_MMHUB_DEEPSLEEP_IB__DS4_MASK … #define PCTL_MMHUB_DEEPSLEEP_IB__DS5_MASK … #define PCTL_MMHUB_DEEPSLEEP_IB__DS6_MASK … #define PCTL_MMHUB_DEEPSLEEP_IB__DS7_MASK … #define PCTL_MMHUB_DEEPSLEEP_IB__DS8_MASK … #define PCTL_MMHUB_DEEPSLEEP_IB__DS9_MASK … #define PCTL_MMHUB_DEEPSLEEP_IB__DS10_MASK … #define PCTL_MMHUB_DEEPSLEEP_IB__DS11_MASK … #define PCTL_MMHUB_DEEPSLEEP_IB__DS12_MASK … #define PCTL_MMHUB_DEEPSLEEP_IB__DS13_MASK … #define PCTL_MMHUB_DEEPSLEEP_IB__DS14_MASK … #define PCTL_MMHUB_DEEPSLEEP_IB__DS15_MASK … #define PCTL_MMHUB_DEEPSLEEP_IB__DS16_MASK … #define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK … //PCTL_MMHUB_DEEPSLEEP_OVERRIDE #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK … //PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK … #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK … //PCTL_PG_IGNORE_DEEPSLEEP #define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK … //PCTL_PG_IGNORE_DEEPSLEEP_IB #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK … #define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK … //PCTL_SLICE0_CFG_DAGB_WRBUSY #define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT … #define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG_MASK … //PCTL_SLICE0_CFG_DAGB_RDBUSY #define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT … #define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG_MASK … //PCTL_SLICE0_CFG_DS_ALLOW #define PCTL_SLICE0_CFG_DS_ALLOW__DS0__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW__DS1__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW__DS2__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW__DS3__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW__DS4__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW__DS5__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW__DS6__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW__DS7__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW__DS8__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW__DS9__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW__DS10__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW__DS11__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW__DS12__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW__DS13__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW__DS14__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW__DS15__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW__DS16__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW__DS0_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW__DS1_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW__DS2_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW__DS3_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW__DS4_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW__DS5_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW__DS6_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW__DS7_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW__DS8_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW__DS9_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW__DS10_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW__DS11_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW__DS12_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW__DS13_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW__DS14_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW__DS15_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW__DS16_MASK … //PCTL_SLICE0_CFG_DS_ALLOW_IB #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK … #define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK … //PCTL_SLICE1_CFG_DAGB_WRBUSY #define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT … #define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG_MASK … //PCTL_SLICE1_CFG_DAGB_RDBUSY #define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT … #define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG_MASK … //PCTL_SLICE1_CFG_DS_ALLOW #define PCTL_SLICE1_CFG_DS_ALLOW__DS0__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW__DS1__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW__DS2__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW__DS3__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW__DS4__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW__DS5__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW__DS6__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW__DS7__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW__DS8__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW__DS9__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW__DS10__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW__DS11__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW__DS12__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW__DS13__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW__DS14__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW__DS15__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW__DS16__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW__DS0_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW__DS1_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW__DS2_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW__DS3_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW__DS4_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW__DS5_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW__DS6_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW__DS7_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW__DS8_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW__DS9_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW__DS10_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW__DS11_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW__DS12_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW__DS13_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW__DS14_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW__DS15_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW__DS16_MASK … //PCTL_SLICE1_CFG_DS_ALLOW_IB #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK … #define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK … //PCTL_UTCL2_MISC #define PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT … #define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT … #define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT … #define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT … #define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT … #define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT … #define PCTL_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT … #define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE__SHIFT … #define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER__SHIFT … #define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER__SHIFT … #define PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK … #define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK … #define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK … #define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK … #define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK … #define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK … #define PCTL_UTCL2_MISC__RD_TIMER_ENABLE_MASK … #define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE_MASK … #define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER_MASK … #define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER_MASK … //PCTL_SLICE0_MISC #define PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT … #define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT … #define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT … #define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT … #define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT … #define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT … #define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT … #define PCTL_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT … #define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE__SHIFT … #define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER__SHIFT … #define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER__SHIFT … #define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK__SHIFT … #define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK__SHIFT … #define PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK … #define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK … #define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK … #define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK … #define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK … #define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK … #define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK … #define PCTL_SLICE0_MISC__RD_TIMER_ENABLE_MASK … #define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE_MASK … #define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER_MASK … #define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER_MASK … #define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK_MASK … #define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK_MASK … //PCTL_SLICE1_MISC #define PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT … #define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT … #define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT … #define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT … #define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT … #define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT … #define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT … #define PCTL_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT … #define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE__SHIFT … #define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER__SHIFT … #define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER__SHIFT … #define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK__SHIFT … #define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK__SHIFT … #define PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK … #define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK … #define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK … #define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK … #define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK … #define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK … #define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK … #define PCTL_SLICE1_MISC__RD_TIMER_ENABLE_MASK … #define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE_MASK … #define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER_MASK … #define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER_MASK … #define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK_MASK … #define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK_MASK … //PCTL_RENG_CTRL #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW__SHIFT … #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE__SHIFT … #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MASK … #define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE_MASK … //PCTL_UTCL2_RENG_EXECUTE #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT … #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT … #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT … #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT … #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK … #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK … #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK … #define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK … //PCTL_SLICE0_RENG_EXECUTE #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT … #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT … #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT … #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT … #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK … #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK … #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK … #define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK … //PCTL_SLICE1_RENG_EXECUTE #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT … #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT … #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT … #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT … #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK … #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK … #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK … #define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK … //PCTL_UTCL2_RENG_RAM_INDEX #define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT … #define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK … //PCTL_UTCL2_RENG_RAM_DATA #define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT … #define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK … //PCTL_SLICE0_RENG_RAM_INDEX #define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT … #define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK … //PCTL_SLICE0_RENG_RAM_DATA #define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT … #define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK … //PCTL_SLICE1_RENG_RAM_INDEX #define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT … #define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK … //PCTL_SLICE1_RENG_RAM_DATA #define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT … #define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK … //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK … //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK … //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK … //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK … //PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK … //PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK … //PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK … #define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK … //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK … //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK … //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK … //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK … //PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK … //PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK … //PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK … #define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK … //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK … //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK … //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK … //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK … //PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK … //PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK … //PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK … #define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK … //PCTL_STATUS #define PCTL_STATUS__MMHUB_CONFIG_DONE__SHIFT … #define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE__SHIFT … #define PCTL_STATUS__MMHUB_FENCE_REQ__SHIFT … #define PCTL_STATUS__MMHUB_FENCE_ACK__SHIFT … #define PCTL_STATUS__MMHUB_IDLE__SHIFT … #define PCTL_STATUS__PGFSM_CMD_STATUS__SHIFT … #define PCTL_STATUS__RSMU_RDTIMEOUT_CNT__SHIFT … #define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR__SHIFT … #define PCTL_STATUS__MMHUB_POWER__SHIFT … #define PCTL_STATUS__RENG_RAM_STALE__SHIFT … #define PCTL_STATUS__UTCL2_RENG_RAM_STALE__SHIFT … #define PCTL_STATUS__SLICE0_RENG_RAM_STALE__SHIFT … #define PCTL_STATUS__SLICE1_RENG_RAM_STALE__SHIFT … #define PCTL_STATUS__MMHUB_CONFIG_DONE_MASK … #define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE_MASK … #define PCTL_STATUS__MMHUB_FENCE_REQ_MASK … #define PCTL_STATUS__MMHUB_FENCE_ACK_MASK … #define PCTL_STATUS__MMHUB_IDLE_MASK … #define PCTL_STATUS__PGFSM_CMD_STATUS_MASK … #define PCTL_STATUS__RSMU_RDTIMEOUT_CNT_MASK … #define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR_MASK … #define PCTL_STATUS__MMHUB_POWER_MASK … #define PCTL_STATUS__RENG_RAM_STALE_MASK … #define PCTL_STATUS__UTCL2_RENG_RAM_STALE_MASK … #define PCTL_STATUS__SLICE0_RENG_RAM_STALE_MASK … #define PCTL_STATUS__SLICE1_RENG_RAM_STALE_MASK … //PCTL_PERFCOUNTER_LO #define PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT … #define PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK … //PCTL_PERFCOUNTER_HI #define PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT … #define PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT … #define PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK … #define PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK … //PCTL_PERFCOUNTER0_CFG #define PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT … #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT … #define PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT … #define PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT … #define PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT … #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK … #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK … #define PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK … #define PCTL_PERFCOUNTER0_CFG__ENABLE_MASK … #define PCTL_PERFCOUNTER0_CFG__CLEAR_MASK … //PCTL_PERFCOUNTER1_CFG #define PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT … #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT … #define PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT … #define PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT … #define PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT … #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK … #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK … #define PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK … #define PCTL_PERFCOUNTER1_CFG__ENABLE_MASK … #define PCTL_PERFCOUNTER1_CFG__CLEAR_MASK … //PCTL_PERFCOUNTER_RSLT_CNTL #define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT … #define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT … #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT … #define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT … #define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT … #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT … #define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK … #define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK … #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK … #define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK … #define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK … #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK … //PCTL_RESERVED_0 #define PCTL_RESERVED_0__WORD__SHIFT … #define PCTL_RESERVED_0__BYTE__SHIFT … #define PCTL_RESERVED_0__BIT7__SHIFT … #define PCTL_RESERVED_0__BIT6__SHIFT … #define PCTL_RESERVED_0__BIT5__SHIFT … #define PCTL_RESERVED_0__BIT4__SHIFT … #define PCTL_RESERVED_0__BIT3__SHIFT … #define PCTL_RESERVED_0__BIT2__SHIFT … #define PCTL_RESERVED_0__BIT1__SHIFT … #define PCTL_RESERVED_0__BIT0__SHIFT … #define PCTL_RESERVED_0__WORD_MASK … #define PCTL_RESERVED_0__BYTE_MASK … #define PCTL_RESERVED_0__BIT7_MASK … #define PCTL_RESERVED_0__BIT6_MASK … #define PCTL_RESERVED_0__BIT5_MASK … #define PCTL_RESERVED_0__BIT4_MASK … #define PCTL_RESERVED_0__BIT3_MASK … #define PCTL_RESERVED_0__BIT2_MASK … #define PCTL_RESERVED_0__BIT1_MASK … #define PCTL_RESERVED_0__BIT0_MASK … //PCTL_RESERVED_1 #define PCTL_RESERVED_1__WORD__SHIFT … #define PCTL_RESERVED_1__BYTE__SHIFT … #define PCTL_RESERVED_1__BIT7__SHIFT … #define PCTL_RESERVED_1__BIT6__SHIFT … #define PCTL_RESERVED_1__BIT5__SHIFT … #define PCTL_RESERVED_1__BIT4__SHIFT … #define PCTL_RESERVED_1__BIT3__SHIFT … #define PCTL_RESERVED_1__BIT2__SHIFT … #define PCTL_RESERVED_1__BIT1__SHIFT … #define PCTL_RESERVED_1__BIT0__SHIFT … #define PCTL_RESERVED_1__WORD_MASK … #define PCTL_RESERVED_1__BYTE_MASK … #define PCTL_RESERVED_1__BIT7_MASK … #define PCTL_RESERVED_1__BIT6_MASK … #define PCTL_RESERVED_1__BIT5_MASK … #define PCTL_RESERVED_1__BIT4_MASK … #define PCTL_RESERVED_1__BIT3_MASK … #define PCTL_RESERVED_1__BIT2_MASK … #define PCTL_RESERVED_1__BIT1_MASK … #define PCTL_RESERVED_1__BIT0_MASK … //PCTL_RESERVED_2 #define PCTL_RESERVED_2__WORD__SHIFT … #define PCTL_RESERVED_2__BYTE__SHIFT … #define PCTL_RESERVED_2__BIT7__SHIFT … #define PCTL_RESERVED_2__BIT6__SHIFT … #define PCTL_RESERVED_2__BIT5__SHIFT … #define PCTL_RESERVED_2__BIT4__SHIFT … #define PCTL_RESERVED_2__BIT3__SHIFT … #define PCTL_RESERVED_2__BIT2__SHIFT … #define PCTL_RESERVED_2__BIT1__SHIFT … #define PCTL_RESERVED_2__BIT0__SHIFT … #define PCTL_RESERVED_2__WORD_MASK … #define PCTL_RESERVED_2__BYTE_MASK … #define PCTL_RESERVED_2__BIT7_MASK … #define PCTL_RESERVED_2__BIT6_MASK … #define PCTL_RESERVED_2__BIT5_MASK … #define PCTL_RESERVED_2__BIT4_MASK … #define PCTL_RESERVED_2__BIT3_MASK … #define PCTL_RESERVED_2__BIT2_MASK … #define PCTL_RESERVED_2__BIT1_MASK … #define PCTL_RESERVED_2__BIT0_MASK … //PCTL_RESERVED_3 #define PCTL_RESERVED_3__WORD__SHIFT … #define PCTL_RESERVED_3__BYTE__SHIFT … #define PCTL_RESERVED_3__BIT7__SHIFT … #define PCTL_RESERVED_3__BIT6__SHIFT … #define PCTL_RESERVED_3__BIT5__SHIFT … #define PCTL_RESERVED_3__BIT4__SHIFT … #define PCTL_RESERVED_3__BIT3__SHIFT … #define PCTL_RESERVED_3__BIT2__SHIFT … #define PCTL_RESERVED_3__BIT1__SHIFT … #define PCTL_RESERVED_3__BIT0__SHIFT … #define PCTL_RESERVED_3__WORD_MASK … #define PCTL_RESERVED_3__BYTE_MASK … #define PCTL_RESERVED_3__BIT7_MASK … #define PCTL_RESERVED_3__BIT6_MASK … #define PCTL_RESERVED_3__BIT5_MASK … #define PCTL_RESERVED_3__BIT4_MASK … #define PCTL_RESERVED_3__BIT3_MASK … #define PCTL_RESERVED_3__BIT2_MASK … #define PCTL_RESERVED_3__BIT1_MASK … #define PCTL_RESERVED_3__BIT0_MASK … // addressBlock: mmhub_l1tlb_mmutcl1pfdec //MMMC_VM_MX_L1_TLB0_STATUS #define MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT … #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT … #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT … #define MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK … #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK … #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK … //MMMC_VM_MX_L1_TLB1_STATUS #define MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT … #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT … #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS__SHIFT … #define MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK … #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK … #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS_MASK … //MMMC_VM_MX_L1_TLB2_STATUS #define MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT … #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT … #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS__SHIFT … #define MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK … #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK … #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS_MASK … //MMMC_VM_MX_L1_TLB3_STATUS #define MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT … #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT … #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS__SHIFT … #define MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK … #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK … #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS_MASK … //MMMC_VM_MX_L1_TLB4_STATUS #define MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT … #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT … #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS__SHIFT … #define MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK … #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK … #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS_MASK … //MMMC_VM_MX_L1_TLB5_STATUS #define MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT … #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT … #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS__SHIFT … #define MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK … #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK … #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS_MASK … //MMMC_VM_MX_L1_TLB6_STATUS #define MMMC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT … #define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT … #define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_APERTURE_FAULTS__SHIFT … #define MMMC_VM_MX_L1_TLB6_STATUS__BUSY_MASK … #define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK … #define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_APERTURE_FAULTS_MASK … //MMMC_VM_MX_L1_TLB7_STATUS #define MMMC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT … #define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT … #define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_APERTURE_FAULTS__SHIFT … #define MMMC_VM_MX_L1_TLB7_STATUS__BUSY_MASK … #define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK … #define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_APERTURE_FAULTS_MASK … // addressBlock: mmhub_l1tlb_mmutcl1pldec //MMMC_VM_MX_L1_PERFCOUNTER0_CFG #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK … //MMMC_VM_MX_L1_PERFCOUNTER1_CFG #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK … //MMMC_VM_MX_L1_PERFCOUNTER2_CFG #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK … //MMMC_VM_MX_L1_PERFCOUNTER3_CFG #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK … //MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK … // addressBlock: mmhub_l1tlb_mmutcl1prdec //MMMC_VM_MX_L1_PERFCOUNTER_LO #define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK … //MMMC_VM_MX_L1_PERFCOUNTER_HI #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT … #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK … #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK … // addressBlock: mmhub_l1tlb_mmvmtlspfdec //MMMC_VM_MX_L1_TLS0_CNTL #define MMMC_VM_MX_L1_TLS0_CNTL__PREFETCH_COUNT__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_SNOOP_SELECT__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SYSTEM__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SNOOP__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL__DEBUG_ECO_BITS__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL__PREFETCH_COUNT_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_SNOOP_SELECT_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SYSTEM_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SNOOP_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL__DEBUG_ECO_BITS_MASK … //MMMC_VM_MX_L1_TLS0_CNTL0 #define MMMC_VM_MX_L1_TLS0_CNTL0__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL0__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL0__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL0__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL0__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL0__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL1 #define MMMC_VM_MX_L1_TLS0_CNTL1__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL1__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL1__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL1__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL1__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL1__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL2 #define MMMC_VM_MX_L1_TLS0_CNTL2__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL2__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL2__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL2__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL2__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL2__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL3 #define MMMC_VM_MX_L1_TLS0_CNTL3__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL3__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL3__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL3__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL3__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL3__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL4 #define MMMC_VM_MX_L1_TLS0_CNTL4__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL4__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL4__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL4__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL4__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL4__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL5 #define MMMC_VM_MX_L1_TLS0_CNTL5__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL5__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL5__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL5__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL5__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL5__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL6 #define MMMC_VM_MX_L1_TLS0_CNTL6__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL6__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL6__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL6__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL6__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL6__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL7 #define MMMC_VM_MX_L1_TLS0_CNTL7__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL7__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL7__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL7__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL7__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL7__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL8 #define MMMC_VM_MX_L1_TLS0_CNTL8__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL8__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL8__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL8__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL8__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL8__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL9 #define MMMC_VM_MX_L1_TLS0_CNTL9__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL9__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL9__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL9__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL9__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL9__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL10 #define MMMC_VM_MX_L1_TLS0_CNTL10__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL10__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL10__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL10__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL10__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL10__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL11 #define MMMC_VM_MX_L1_TLS0_CNTL11__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL11__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL11__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL11__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL11__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL11__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL12 #define MMMC_VM_MX_L1_TLS0_CNTL12__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL12__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL12__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL12__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL12__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL12__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL13 #define MMMC_VM_MX_L1_TLS0_CNTL13__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL13__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL13__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL13__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL13__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL13__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL14 #define MMMC_VM_MX_L1_TLS0_CNTL14__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL14__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL14__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL14__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL14__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL14__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL15 #define MMMC_VM_MX_L1_TLS0_CNTL15__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL15__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL15__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL15__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL15__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL15__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL16 #define MMMC_VM_MX_L1_TLS0_CNTL16__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL16__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL16__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL16__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL16__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL16__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL17 #define MMMC_VM_MX_L1_TLS0_CNTL17__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL17__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL17__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL17__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL17__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL17__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL18 #define MMMC_VM_MX_L1_TLS0_CNTL18__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL18__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL18__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL18__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL18__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL18__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL19 #define MMMC_VM_MX_L1_TLS0_CNTL19__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL19__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL19__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL19__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL19__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL19__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL20 #define MMMC_VM_MX_L1_TLS0_CNTL20__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL20__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL20__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL20__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL20__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL20__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL21 #define MMMC_VM_MX_L1_TLS0_CNTL21__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL21__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL21__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL21__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL21__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL21__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL22 #define MMMC_VM_MX_L1_TLS0_CNTL22__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL22__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL22__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL22__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL22__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL22__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL23 #define MMMC_VM_MX_L1_TLS0_CNTL23__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL23__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL23__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL23__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL23__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL23__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL24 #define MMMC_VM_MX_L1_TLS0_CNTL24__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL24__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL24__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL24__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL24__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL24__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL25 #define MMMC_VM_MX_L1_TLS0_CNTL25__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL25__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL25__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL25__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL25__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL25__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL26 #define MMMC_VM_MX_L1_TLS0_CNTL26__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL26__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL26__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL26__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL26__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL26__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL27 #define MMMC_VM_MX_L1_TLS0_CNTL27__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL27__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL27__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL27__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL27__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL27__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL28 #define MMMC_VM_MX_L1_TLS0_CNTL28__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL28__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL28__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL28__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL28__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL28__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL29 #define MMMC_VM_MX_L1_TLS0_CNTL29__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL29__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL29__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL29__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL29__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL29__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL30 #define MMMC_VM_MX_L1_TLS0_CNTL30__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL30__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL30__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL30__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL30__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL30__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL31 #define MMMC_VM_MX_L1_TLS0_CNTL31__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL31__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL31__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL31__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL31__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL31__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL32 #define MMMC_VM_MX_L1_TLS0_CNTL32__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL32__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL32__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL32__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL32__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL32__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL33 #define MMMC_VM_MX_L1_TLS0_CNTL33__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL33__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL33__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL33__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL33__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL33__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL34 #define MMMC_VM_MX_L1_TLS0_CNTL34__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL34__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL34__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL34__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL34__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL34__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL35 #define MMMC_VM_MX_L1_TLS0_CNTL35__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL35__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL35__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL35__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL35__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL35__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL36 #define MMMC_VM_MX_L1_TLS0_CNTL36__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL36__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL36__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL36__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL36__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL36__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_CNTL37 #define MMMC_VM_MX_L1_TLS0_CNTL37__REQ_STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL37__EN__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL37__PREFETCH_DONE__SHIFT … #define MMMC_VM_MX_L1_TLS0_CNTL37__REQ_STREAM_ID_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL37__EN_MASK … #define MMMC_VM_MX_L1_TLS0_CNTL37__PREFETCH_DONE_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32 #define MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32__START_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32__START_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32 #define MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32__START_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32__START_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32 #define MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32__END_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32__END_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32 #define MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32__END_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32__END_ADDR_HI4_MASK … //MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32 #define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32__INVALIDATE_STREAM_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32__INVALIDATE_STREAM_LO32_MASK … //MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32 #define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32__INVALIDATE_STREAM_HI6__SHIFT … #define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32__INVALIDATE_STREAM_HI6_MASK … //MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32 #define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32__INVALIDATE_REQUEST_PENDING_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32__INVALIDATE_REQUEST_PENDING_LO32_MASK … //MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32 #define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32__INVALIDATE_REQUEST_PENDING_HI6__SHIFT … #define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32__INVALIDATE_REQUEST_PENDING_HI6_MASK … //MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT … #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT … #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__VMID__SHIFT … #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT … #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK … #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK … #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK … #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__VMID_MASK … #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC_MASK … //MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32 #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK … //MMVM_L2_SAW_CNTL #define MMVM_L2_SAW_CNTL__ENABLE_L2_CACHE__SHIFT … #define MMVM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT … #define MMVM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT … #define MMVM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT … #define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT … #define MMVM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT … #define MMVM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT … #define MMVM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT … #define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT … #define MMVM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT … #define MMVM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT … #define MMVM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT … #define MMVM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT … #define MMVM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT … #define MMVM_L2_SAW_CNTL__ENABLE_L2_CACHE_MASK … #define MMVM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK … #define MMVM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK … #define MMVM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK … #define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK … #define MMVM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK … #define MMVM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK … #define MMVM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK … #define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK … #define MMVM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK … #define MMVM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION_MASK … #define MMVM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK … #define MMVM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK … #define MMVM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK … #define MMVM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK … //MMVM_L2_SAW_CNTL2 #define MMVM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT … #define MMVM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE__SHIFT … #define MMVM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT … #define MMVM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT … #define MMVM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT … #define MMVM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE__SHIFT … #define MMVM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT … #define MMVM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK … #define MMVM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE_MASK … #define MMVM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK … #define MMVM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK … #define MMVM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK … #define MMVM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE_MASK … #define MMVM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK … //MMVM_L2_SAW_CNTL3 #define MMVM_L2_SAW_CNTL3__BANK_SELECT__SHIFT … #define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT … #define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT … #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT … #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT … #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT … #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT … #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT … #define MMVM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT … #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT … #define MMVM_L2_SAW_CNTL3__BANK_SELECT_MASK … #define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE_MASK … #define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK … #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK … #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK … #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK … #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK … #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK … #define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK … #define MMVM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS_MASK … #define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK … //MMVM_L2_SAW_CNTL4 #define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT … #define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING__SHIFT … #define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK … #define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK … #define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING_MASK … //MMVM_L2_SAW_CONTEXT0_CNTL #define MMVM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … //MMVM_L2_SAW_CONTEXT0_CNTL2 #define MMVM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT … #define MMVM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK … #define MMVM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK … //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32_MASK … //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4_MASK … //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_L2_SAW_CONTEXTS_DISABLE #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK … #define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK … //MMVM_L2_SAW_PIPES_BUSY_LO32 #define MMVM_L2_SAW_PIPES_BUSY_LO32__PIPES_BUSY_LO32__SHIFT … #define MMVM_L2_SAW_PIPES_BUSY_LO32__PIPES_BUSY_LO32_MASK … //MMVM_L2_SAW_PIPES_BUSY_HI32 #define MMVM_L2_SAW_PIPES_BUSY_HI32__PIPES_BUSY_HI32__SHIFT … #define MMVM_L2_SAW_PIPES_BUSY_HI32__PIPES_BUSY_HI32_MASK … //MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__MORE_FAULTS__SHIFT … #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__ABORT_STATUS__SHIFT … #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__STREAM_ID__SHIFT … #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__MORE_FAULTS_MASK … #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__ABORT_STATUS_MASK … #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__STREAM_ID_MASK … //MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32 #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT … #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK … //MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32 #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT … #define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK … // addressBlock: mmhub_mmutcl2_mmatcl2dec //MM_ATC_L2_CNTL #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT … #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT … #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT … #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT … #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT … #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT … #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT … #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT … #define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT … #define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT … #define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT … #define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT … #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK … #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK … #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK … #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK … #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK … #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK … #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK … #define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK … #define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK … #define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK … #define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK … #define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK … //MM_ATC_L2_CNTL2 #define MM_ATC_L2_CNTL2__BANK_SELECT__SHIFT … #define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT … #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT … #define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT … #define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT … #define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT … #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT … #define MM_ATC_L2_CNTL2__BANK_SELECT_MASK … #define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK … #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK … #define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK … #define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK … #define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK … #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK … //MM_ATC_L2_CACHE_DATA0 #define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT … #define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT … #define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT … #define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT … #define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK … #define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK … #define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK … #define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK … //MM_ATC_L2_CACHE_DATA1 #define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT … #define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK … //MM_ATC_L2_CACHE_DATA2 #define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT … #define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK … //MM_ATC_L2_CNTL3 #define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT … #define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE__SHIFT … #define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE__SHIFT … #define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT … #define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT … #define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT … #define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT … #define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE_MASK … #define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE_MASK … #define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE_MASK … #define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK … #define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK … #define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK … #define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK … //MM_ATC_L2_CNTL4 #define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT … #define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE__SHIFT … #define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE__SHIFT … #define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE_MASK … #define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE_MASK … #define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE_MASK … //MM_ATC_L2_CNTL5 #define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT … #define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT … #define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK … #define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK … //MM_ATC_L2_MM_GROUP_RT_CLASSES #define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT … #define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK … //MM_ATC_L2_STATUS #define MM_ATC_L2_STATUS__BUSY__SHIFT … #define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT … #define MM_ATC_L2_STATUS__BUSY_MASK … #define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK … //MM_ATC_L2_STATUS2 #define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT … #define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT … #define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK … #define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK … //MM_ATC_L2_MISC_CG #define MM_ATC_L2_MISC_CG__OFFDLY__SHIFT … #define MM_ATC_L2_MISC_CG__ENABLE__SHIFT … #define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT … #define MM_ATC_L2_MISC_CG__OFFDLY_MASK … #define MM_ATC_L2_MISC_CG__ENABLE_MASK … #define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK … //MM_ATC_L2_MEM_POWER_LS #define MM_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT … #define MM_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT … #define MM_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK … #define MM_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK … //MM_ATC_L2_CGTT_CLK_CTRL #define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT … #define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT … #define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT … #define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT … #define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK … #define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK … #define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK … #define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK … #define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK … //MM_ATC_L2_SDPPORT_CTRL #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT … #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT … #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT … #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT … #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT … #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT … #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT … #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT … #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT … #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT … #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK … #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK … #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK … #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK … #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK … #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK … #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK … #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK … #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK … #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK … // addressBlock: mmhub_mmutcl2_mmvml2pfdec //MMVM_L2_CNTL #define MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT … #define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT … #define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT … #define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT … #define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT … #define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT … #define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT … #define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT … #define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT … #define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT … #define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT … #define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT … #define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT … #define MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK … #define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK … #define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK … #define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK … #define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK … #define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK … #define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK … #define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK … #define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK … #define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK … #define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK … #define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK … #define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK … #define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK … //MMVM_L2_CNTL2 #define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT … #define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT … #define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT … #define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT … #define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT … #define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT … #define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT … #define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK … #define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK … #define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK … #define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK … #define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK … #define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK … #define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK … //MMVM_L2_CNTL3 #define MMVM_L2_CNTL3__BANK_SELECT__SHIFT … #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT … #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT … #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT … #define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT … #define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT … #define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT … #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT … #define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT … #define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT … #define MMVM_L2_CNTL3__BANK_SELECT_MASK … #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK … #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK … #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK … #define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK … #define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK … #define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK … #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK … #define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK … #define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK … //MMVM_L2_STATUS #define MMVM_L2_STATUS__L2_BUSY__SHIFT … #define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT … #define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT … #define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT … #define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT … #define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT … #define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT … #define MMVM_L2_STATUS__L2_BUSY_MASK … #define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK … #define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK … #define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK … #define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK … #define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK … #define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK … //MMVM_DUMMY_PAGE_FAULT_CNTL #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT … #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT … #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT … #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK … #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK … #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK … //MMVM_DUMMY_PAGE_FAULT_ADDR_LO32 #define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT … #define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK … //MMVM_DUMMY_PAGE_FAULT_ADDR_HI32 #define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT … #define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK … //MMVM_INVALIDATE_CNTL #define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT … #define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT … #define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK … #define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK … //MMVM_L2_PROTECTION_FAULT_CNTL #define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK … #define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK … #define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK … #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK … #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK … //MMVM_L2_PROTECTION_FAULT_CNTL2 #define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK … #define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK … #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK … #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK … #define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK … //MMVM_L2_PROTECTION_FAULT_MM_CNTL3 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK … //MMVM_L2_PROTECTION_FAULT_MM_CNTL4 #define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK … //MMVM_L2_PROTECTION_FAULT_STATUS #define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT … #define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT … #define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT … #define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT … #define MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT … #define MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT … #define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT … #define MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT … #define MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT … #define MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT … #define MMVM_L2_PROTECTION_FAULT_STATUS__PRT__SHIFT … #define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK … #define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK … #define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK … #define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK … #define MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK … #define MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK … #define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK … #define MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK … #define MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK … #define MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK … #define MMVM_L2_PROTECTION_FAULT_STATUS__PRT_MASK … //MMVM_L2_PROTECTION_FAULT_ADDR_LO32 #define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT … #define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK … //MMVM_L2_PROTECTION_FAULT_ADDR_HI32 #define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT … #define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK … //MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT … #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK … //MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT … #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK … //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT … #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK … //MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT … #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK … //MMVM_L2_CNTL4 #define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT … #define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT … #define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT … #define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT … #define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT … #define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT … #define MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT … #define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT … #define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT … #define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK … #define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK … #define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK … #define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK … #define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK … #define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK … #define MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK … #define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK … #define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK … //MMVM_L2_MM_GROUP_RT_CLASSES #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK … #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK … //MMVM_L2_BANK_SELECT_RESERVED_CID #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT … #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT … #define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT … #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT … #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT … #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK … #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK … #define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK … #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK … #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK … #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK … //MMVM_L2_BANK_SELECT_RESERVED_CID2 #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT … #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT … #define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT … #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT … #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT … #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK … #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK … #define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK … #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK … #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK … #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK … //MMVM_L2_CACHE_PARITY_CNTL #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT … #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT … #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT … #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT … #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT … #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT … #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT … #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT … #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT … #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK … #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK … #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK … #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK … #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK … #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK … #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK … #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK … #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK … //MMVM_L2_CGTT_CLK_CTRL #define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT … #define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT … #define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT … #define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT … #define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK … #define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK … #define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK … #define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK … #define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK … //MMVM_L2_CNTL5 #define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT … #define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT … #define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT … #define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF__SHIFT … #define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT … #define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK … #define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK … #define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK … #define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF_MASK … #define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK … //MMVM_L2_GCR_CNTL #define MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT … #define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT … #define MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK … #define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK … //MMVM_L2_CGTT_BUSY_CTRL #define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT … #define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT … #define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK … #define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK … //MMVM_L2_PTE_CACHE_DUMP_CNTL #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT … #define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT … #define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT … #define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT … #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT … #define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT … #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK … #define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK … #define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK … #define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK … #define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK … #define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK … //MMVM_L2_PTE_CACHE_DUMP_READ #define MMVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT … #define MMVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK … //MMVM_L2_BANK_SELECT_MASKS #define MMVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT … #define MMVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT … #define MMVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT … #define MMVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT … #define MMVM_L2_BANK_SELECT_MASKS__MASK0_MASK … #define MMVM_L2_BANK_SELECT_MASKS__MASK1_MASK … #define MMVM_L2_BANK_SELECT_MASKS__MASK2_MASK … #define MMVM_L2_BANK_SELECT_MASKS__MASK3_MASK … //MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC #define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT … #define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT … #define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK … #define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK … //MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT … #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT … #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK … #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK … //MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT … #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT … #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK … #define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK … //MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT #define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT … #define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT … #define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK … #define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK … //MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ #define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT … #define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT … #define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK … #define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK … // addressBlock: mmhub_mmutcl2_mmvml2vcdec //MMVM_CONTEXT0_CNTL #define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT … #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT … #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT … #define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT … #define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT … #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK … #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK … #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK … #define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK … #define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK … #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … //MMVM_CONTEXT1_CNTL #define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT … #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT … #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT … #define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT … #define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT … #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK … #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK … #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK … #define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK … #define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK … #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … //MMVM_CONTEXT2_CNTL #define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT … #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT … #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT … #define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT … #define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT … #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK … #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK … #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK … #define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK … #define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK … #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … //MMVM_CONTEXT3_CNTL #define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT … #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT … #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT … #define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT … #define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT … #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK … #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK … #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK … #define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK … #define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK … #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … //MMVM_CONTEXT4_CNTL #define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT … #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT … #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT … #define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT … #define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT … #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK … #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK … #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK … #define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK … #define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK … #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … //MMVM_CONTEXT5_CNTL #define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT … #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT … #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT … #define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT … #define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT … #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK … #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK … #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK … #define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK … #define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK … #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … //MMVM_CONTEXT6_CNTL #define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT … #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT … #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT … #define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT … #define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT … #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK … #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK … #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK … #define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK … #define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK … #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … //MMVM_CONTEXT7_CNTL #define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT … #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT … #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT … #define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT … #define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT … #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK … #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK … #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK … #define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK … #define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK … #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … //MMVM_CONTEXT8_CNTL #define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT … #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT … #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT … #define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT … #define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT … #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK … #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK … #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK … #define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK … #define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK … #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … //MMVM_CONTEXT9_CNTL #define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT … #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT … #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT … #define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT … #define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT … #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK … #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK … #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK … #define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK … #define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK … #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … //MMVM_CONTEXT10_CNTL #define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT … #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT … #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT … #define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT … #define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT … #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK … #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK … #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK … #define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK … #define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK … #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … //MMVM_CONTEXT11_CNTL #define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT … #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT … #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT … #define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT … #define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT … #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK … #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK … #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK … #define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK … #define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK … #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … //MMVM_CONTEXT12_CNTL #define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT … #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT … #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT … #define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT … #define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT … #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK … #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK … #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK … #define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK … #define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK … #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … //MMVM_CONTEXT13_CNTL #define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT … #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT … #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT … #define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT … #define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT … #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK … #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK … #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK … #define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK … #define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK … #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … //MMVM_CONTEXT14_CNTL #define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT … #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT … #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT … #define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT … #define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT … #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK … #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK … #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK … #define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK … #define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK … #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … //MMVM_CONTEXT15_CNTL #define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT … #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT … #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT … #define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT … #define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT … #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT … #define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT … #define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK … #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK … #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK … #define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK … #define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK … #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … #define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK … #define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK … //MMVM_CONTEXTS_DISABLE #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK … #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK … //MMVM_INVALIDATE_ENG0_SEM #define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG1_SEM #define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG2_SEM #define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG3_SEM #define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG4_SEM #define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG5_SEM #define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG6_SEM #define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG7_SEM #define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG8_SEM #define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG9_SEM #define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG10_SEM #define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG11_SEM #define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG12_SEM #define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG13_SEM #define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG14_SEM #define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG15_SEM #define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG16_SEM #define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG17_SEM #define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG0_REQ #define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT … #define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT … #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT … #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT … #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT … #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT … #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT … #define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT … #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT … #define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK … #define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK … #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK … #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK … #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK … #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK … #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK … #define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK … #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK … //MMVM_INVALIDATE_ENG1_REQ #define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT … #define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT … #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT … #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT … #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT … #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT … #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT … #define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT … #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT … #define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK … #define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK … #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK … #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK … #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK … #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK … #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK … #define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK … #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK … //MMVM_INVALIDATE_ENG2_REQ #define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT … #define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT … #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT … #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT … #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT … #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT … #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT … #define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT … #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT … #define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK … #define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK … #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK … #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK … #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK … #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK … #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK … #define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK … #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK … //MMVM_INVALIDATE_ENG3_REQ #define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT … #define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT … #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT … #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT … #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT … #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT … #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT … #define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT … #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT … #define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK … #define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK … #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK … #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK … #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK … #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK … #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK … #define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK … #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK … //MMVM_INVALIDATE_ENG4_REQ #define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT … #define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT … #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT … #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT … #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT … #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT … #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT … #define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT … #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT … #define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK … #define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK … #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK … #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK … #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK … #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK … #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK … #define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK … #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK … //MMVM_INVALIDATE_ENG5_REQ #define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT … #define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT … #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT … #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT … #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT … #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT … #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT … #define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT … #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT … #define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK … #define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK … #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK … #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK … #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK … #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK … #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK … #define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK … #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK … //MMVM_INVALIDATE_ENG6_REQ #define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT … #define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT … #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT … #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT … #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT … #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT … #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT … #define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT … #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT … #define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK … #define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK … #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK … #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK … #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK … #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK … #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK … #define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK … #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK … //MMVM_INVALIDATE_ENG7_REQ #define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT … #define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT … #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT … #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT … #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT … #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT … #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT … #define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT … #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT … #define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK … #define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK … #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK … #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK … #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK … #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK … #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK … #define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK … #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK … //MMVM_INVALIDATE_ENG8_REQ #define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT … #define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT … #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT … #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT … #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT … #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT … #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT … #define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT … #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT … #define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK … #define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK … #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK … #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK … #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK … #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK … #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK … #define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK … #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK … //MMVM_INVALIDATE_ENG9_REQ #define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT … #define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT … #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT … #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT … #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT … #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT … #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT … #define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT … #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT … #define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK … #define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK … #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK … #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK … #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK … #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK … #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK … #define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK … #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK … //MMVM_INVALIDATE_ENG10_REQ #define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT … #define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT … #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT … #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT … #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT … #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT … #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT … #define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT … #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT … #define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK … #define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK … #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK … #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK … #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK … #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK … #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK … #define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK … #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK … //MMVM_INVALIDATE_ENG11_REQ #define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT … #define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT … #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT … #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT … #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT … #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT … #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT … #define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT … #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT … #define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK … #define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK … #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK … #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK … #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK … #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK … #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK … #define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK … #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK … //MMVM_INVALIDATE_ENG12_REQ #define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT … #define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT … #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT … #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT … #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT … #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT … #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT … #define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT … #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT … #define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK … #define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK … #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK … #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK … #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK … #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK … #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK … #define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK … #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK … //MMVM_INVALIDATE_ENG13_REQ #define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT … #define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT … #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT … #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT … #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT … #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT … #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT … #define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT … #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT … #define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK … #define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK … #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK … #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK … #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK … #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK … #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK … #define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK … #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK … //MMVM_INVALIDATE_ENG14_REQ #define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT … #define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT … #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT … #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT … #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT … #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT … #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT … #define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT … #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT … #define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK … #define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK … #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK … #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK … #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK … #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK … #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK … #define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK … #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK … //MMVM_INVALIDATE_ENG15_REQ #define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT … #define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT … #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT … #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT … #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT … #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT … #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT … #define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT … #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT … #define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK … #define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK … #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK … #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK … #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK … #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK … #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK … #define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK … #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK … //MMVM_INVALIDATE_ENG16_REQ #define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT … #define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT … #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT … #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT … #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT … #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT … #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT … #define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT … #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT … #define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK … #define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK … #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK … #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK … #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK … #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK … #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK … #define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK … #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK … //MMVM_INVALIDATE_ENG17_REQ #define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT … #define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT … #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT … #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT … #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT … #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT … #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT … #define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT … #define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT … #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT … #define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK … #define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK … #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK … #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK … #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK … #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK … #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK … #define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK … #define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK … #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK … //MMVM_INVALIDATE_ENG0_ACK #define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT … #define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK … #define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG1_ACK #define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT … #define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK … #define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG2_ACK #define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT … #define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK … #define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG3_ACK #define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT … #define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK … #define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG4_ACK #define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT … #define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK … #define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG5_ACK #define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT … #define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK … #define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG6_ACK #define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT … #define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK … #define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG7_ACK #define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT … #define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK … #define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG8_ACK #define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT … #define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK … #define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG9_ACK #define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT … #define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK … #define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG10_ACK #define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT … #define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK … #define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG11_ACK #define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT … #define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK … #define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG12_ACK #define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT … #define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK … #define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG13_ACK #define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT … #define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK … #define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG14_ACK #define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT … #define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK … #define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG15_ACK #define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT … #define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK … #define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG16_ACK #define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT … #define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK … #define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG17_ACK #define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT … #define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT … #define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK … #define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK … //MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT … #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT … #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK … #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK … //MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT … #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK … //MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT … #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT … #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK … #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK … //MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT … #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK … //MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT … #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT … #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK … #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK … //MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT … #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK … //MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT … #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT … #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK … #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK … //MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT … #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK … //MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT … #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT … #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK … #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK … //MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT … #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK … //MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT … #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT … #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK … #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK … //MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT … #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK … //MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT … #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT … #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK … #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK … //MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT … #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK … //MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT … #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT … #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK … #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK … //MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT … #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK … //MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT … #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT … #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK … #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK … //MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT … #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK … //MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT … #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT … #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK … #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK … //MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT … #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK … //MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT … #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT … #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK … #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK … //MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT … #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK … //MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT … #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT … #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK … #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK … //MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT … #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK … //MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT … #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT … #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK … #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK … //MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT … #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK … //MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT … #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT … #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK … #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK … //MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT … #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK … //MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT … #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT … #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK … #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK … //MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT … #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK … //MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT … #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT … #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK … #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK … //MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT … #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK … //MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT … #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT … #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK … #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK … //MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT … #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK … //MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT … #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT … #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK … #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK … //MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT … #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK … //MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT … #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK … //MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT … #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK … //MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT … #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK … //MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT … #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK … //MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT … #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK … //MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT … #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK … //MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT … #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK … //MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT … #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK … //MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT … #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK … //MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT … #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK … //MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT … #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK … //MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT … #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK … //MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT … #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK … //MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT … #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK … //MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT … #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK … //MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT … #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK … //MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT … #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK … //MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT … #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK … //MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT … #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK … //MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT … #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK … //MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT … #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK … //MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT … #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK … //MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT … #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK … //MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT … #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK … //MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT … #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK … //MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT … #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK … //MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT … #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK … //MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT … #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK … //MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT … #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK … //MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT … #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK … //MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT … #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK … //MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT … #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK … //MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT … #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK … //MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT … #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK … //MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT … #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK … #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK … #define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK … //MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT … #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK … //MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT … #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK … //MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT … #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK … //MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT … #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK … //MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT … #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK … //MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT … #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK … //MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT … #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK … //MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT … #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK … //MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT … #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK … //MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT … #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK … //MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT … #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK … //MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT … #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK … //MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT … #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK … //MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT … #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK … //MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT … #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK … //MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT … #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT … #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK … #define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK … // addressBlock: mmhub_mmutcl2_mmvml2pldec //MMMC_VM_L2_PERFCOUNTER0_CFG #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT … #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT … #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT … #define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT … #define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT … #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK … #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK … #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK … #define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK … #define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK … //MMMC_VM_L2_PERFCOUNTER1_CFG #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT … #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT … #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT … #define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT … #define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT … #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK … #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK … #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK … #define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK … #define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK … //MMMC_VM_L2_PERFCOUNTER2_CFG #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT … #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT … #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT … #define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT … #define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT … #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK … #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK … #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK … #define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK … #define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK … //MMMC_VM_L2_PERFCOUNTER3_CFG #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT … #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT … #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT … #define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT … #define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT … #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK … #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK … #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK … #define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK … #define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK … //MMMC_VM_L2_PERFCOUNTER4_CFG #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT … #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT … #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT … #define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT … #define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT … #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK … #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK … #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK … #define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK … #define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK … //MMMC_VM_L2_PERFCOUNTER5_CFG #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT … #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT … #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT … #define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT … #define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT … #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK … #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK … #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK … #define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK … #define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK … //MMMC_VM_L2_PERFCOUNTER6_CFG #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT … #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT … #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT … #define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT … #define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT … #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK … #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK … #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK … #define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK … #define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK … //MMMC_VM_L2_PERFCOUNTER7_CFG #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT … #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT … #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT … #define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT … #define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT … #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK … #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK … #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK … #define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK … #define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK … //MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT … #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT … #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT … #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT … #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT … #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT … #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK … #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK … #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK … #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK … #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK … #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK … //MMUTCL2_PERFCOUNTER0_CFG #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT … #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT … #define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT … #define MMUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT … #define MMUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT … #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK … #define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK … #define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK … #define MMUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK … #define MMUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK … //MMUTCL2_PERFCOUNTER1_CFG #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT … #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT … #define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT … #define MMUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT … #define MMUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT … #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK … #define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK … #define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK … #define MMUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK … #define MMUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK … //MMUTCL2_PERFCOUNTER2_CFG #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT … #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT … #define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT … #define MMUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT … #define MMUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT … #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK … #define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK … #define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK … #define MMUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK … #define MMUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK … //MMUTCL2_PERFCOUNTER3_CFG #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT … #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT … #define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT … #define MMUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT … #define MMUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT … #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK … #define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK … #define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK … #define MMUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK … #define MMUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK … //MMUTCL2_PERFCOUNTER_RSLT_CNTL #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT … #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT … #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT … #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT … #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT … #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT … #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK … #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK … #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK … #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK … #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK … #define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK … // addressBlock: mmhub_mmutcl2_mmvml2prdec //MMMC_VM_L2_PERFCOUNTER_LO #define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT … #define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK … //MMMC_VM_L2_PERFCOUNTER_HI #define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT … #define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT … #define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK … #define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK … //MMUTCL2_PERFCOUNTER_LO #define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT … #define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK … //MMUTCL2_PERFCOUNTER_HI #define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT … #define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT … #define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK … #define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK … // addressBlock: mmhub_mmutcl2_mmvmsharedhvdec //MMVM_PCIE_ATS_CNTL #define MMVM_PCIE_ATS_CNTL__STU__SHIFT … #define MMVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT … #define MMVM_PCIE_ATS_CNTL__STU_MASK … #define MMVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK … // addressBlock: mmhub_mmutcl2_mmvmsharedpfdec //MMMC_VM_NB_MMIOBASE #define MMMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT … #define MMMC_VM_NB_MMIOBASE__MMIOBASE_MASK … //MMMC_VM_NB_MMIOLIMIT #define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT … #define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK … //MMMC_VM_NB_PCI_CTRL #define MMMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT … #define MMMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK … //MMMC_VM_NB_PCI_ARB #define MMMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT … #define MMMC_VM_NB_PCI_ARB__VGA_HOLE_MASK … //MMMC_VM_NB_TOP_OF_DRAM_SLOT1 #define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT … #define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK … //MMMC_VM_NB_LOWER_TOP_OF_DRAM2 #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT … #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT … #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK … #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK … //MMMC_VM_NB_UPPER_TOP_OF_DRAM2 #define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT … #define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK … //MMMC_VM_FB_OFFSET #define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT … #define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK … //MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT … #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK … //MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT … #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK … //MMMC_VM_STEERING #define MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT … #define MMMC_VM_STEERING__DEFAULT_STEERING_MASK … //MMMC_SHARED_VIRT_RESET_REQ #define MMMC_SHARED_VIRT_RESET_REQ__VF__SHIFT … #define MMMC_SHARED_VIRT_RESET_REQ__PF__SHIFT … #define MMMC_SHARED_VIRT_RESET_REQ__VF_MASK … #define MMMC_SHARED_VIRT_RESET_REQ__PF_MASK … //MMMC_MEM_POWER_LS #define MMMC_MEM_POWER_LS__LS_SETUP__SHIFT … #define MMMC_MEM_POWER_LS__LS_HOLD__SHIFT … #define MMMC_MEM_POWER_LS__LS_SETUP_MASK … #define MMMC_MEM_POWER_LS__LS_HOLD_MASK … //MMMC_VM_CACHEABLE_DRAM_ADDRESS_START #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT … #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK … //MMMC_VM_CACHEABLE_DRAM_ADDRESS_END #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT … #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK … //MMMC_VM_LOCAL_SYSMEM_ADDRESS_START #define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT … #define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK … //MMMC_VM_LOCAL_SYSMEM_ADDRESS_END #define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT … #define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK … //MMMC_VM_APT_CNTL #define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT … #define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT … #define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT … #define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT … #define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT … #define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT … #define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK … #define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK … #define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK … #define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK … #define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK … #define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK … //MMMC_VM_LOCAL_FB_ADDRESS_START #define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT … #define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK … //MMMC_VM_LOCAL_FB_ADDRESS_END #define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT … #define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK … //MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL #define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT … #define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK … //MMUTCL2_CGTT_CLK_CTRL #define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT … #define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT … #define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT … #define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT … #define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT … #define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK … #define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK … #define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK … #define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE_MASK … #define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK … //MMMC_SHARED_ACTIVE_FCN_ID #define MMMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT … #define MMMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT … #define MMMC_SHARED_ACTIVE_FCN_ID__VFID_MASK … #define MMMC_SHARED_ACTIVE_FCN_ID__VF_MASK … //MMUTCL2_CGTT_BUSY_CTRL #define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT … #define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT … #define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK … #define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK … //MMUTCL2_HARVEST_BYPASS_GROUPS #define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT … #define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK … //MMUTCL2_GROUP_RET_FAULT_STATUS #define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT … #define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK … // addressBlock: mmhub_mmutcl2_mmvmsharedvcdec //MMMC_VM_FB_LOCATION_BASE #define MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT … #define MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK … //MMMC_VM_FB_LOCATION_TOP #define MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT … #define MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK … //MMMC_VM_AGP_TOP #define MMMC_VM_AGP_TOP__AGP_TOP__SHIFT … #define MMMC_VM_AGP_TOP__AGP_TOP_MASK … //MMMC_VM_AGP_BOT #define MMMC_VM_AGP_BOT__AGP_BOT__SHIFT … #define MMMC_VM_AGP_BOT__AGP_BOT_MASK … //MMMC_VM_AGP_BASE #define MMMC_VM_AGP_BASE__AGP_BASE__SHIFT … #define MMMC_VM_AGP_BASE__AGP_BASE_MASK … //MMMC_VM_SYSTEM_APERTURE_LOW_ADDR #define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT … #define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK … //MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR #define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT … #define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK … //MMMC_VM_MX_L1_TLB_CNTL #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT … #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT … #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT … #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT … #define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT … #define MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT … #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK … #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK … #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK … #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK … #define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK … #define MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK … // addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec //MM_ATC_L2_PERFCOUNTER_LO #define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT … #define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK … //MM_ATC_L2_PERFCOUNTER_HI #define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT … #define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT … #define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK … #define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK … // addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec //MM_ATC_L2_PERFCOUNTER0_CFG #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT … #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT … #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT … #define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT … #define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT … #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK … #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK … #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK … #define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK … #define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK … //MM_ATC_L2_PERFCOUNTER1_CFG #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT … #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT … #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT … #define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT … #define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT … #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK … #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK … #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK … #define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK … #define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK … //MM_ATC_L2_PERFCOUNTER_RSLT_CNTL #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT … #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT … #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT … #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT … #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT … #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT … #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK … #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK … #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK … #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK … #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK … #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK … // addressBlock: mmhub_mmutcl2_mmvml2pspdec //MMUTCL2_TRANSLATION_BYPASS_BY_VMID #define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT … #define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT … #define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK … #define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK … //MMVM_IOMMU_CONTROL_REGISTER #define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT … #define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK … //MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER #define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT … #define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK … //MMUTC_TRANSLATION_FAULT_CNTL0 #define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT … #define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK … //MMUTC_TRANSLATION_FAULT_CNTL1 #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT … #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT … #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT … #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT … #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK … #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK … #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK … #define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK … // addressBlock: mmhub_mmutcl2_mml2tlbpspdec //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK … // addressBlock: mmhub_mmutcl2_mmatcl2pspdec //MM_ATC_L2_IOV_MODE_CNTL #define MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN__SHIFT … #define MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN_MASK … // addressBlock: mmhub_mmutcl2_mml2tlbpfdec //MML2TLB_TLB0_STATUS #define MML2TLB_TLB0_STATUS__BUSY__SHIFT … #define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT … #define MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT … #define MML2TLB_TLB0_STATUS__BUSY_MASK … #define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK … #define MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK … //MML2TLB_TMZ_CNTL #define MML2TLB_TMZ_CNTL__TMZ_MODULATION__SHIFT … #define MML2TLB_TMZ_CNTL__TMZ_MODULATION_MASK … //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK … //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK … //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK … //MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK … #define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK … //MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ #define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT … #define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE__SHIFT … #define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK … #define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE_MASK … // addressBlock: mmhub_mmutcl2_mml2tlbpldec //MML2TLB_PERFCOUNTER0_CFG #define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT … #define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT … #define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT … #define MML2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT … #define MML2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT … #define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK … #define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK … #define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK … #define MML2TLB_PERFCOUNTER0_CFG__ENABLE_MASK … #define MML2TLB_PERFCOUNTER0_CFG__CLEAR_MASK … //MML2TLB_PERFCOUNTER1_CFG #define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT … #define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT … #define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT … #define MML2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT … #define MML2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT … #define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK … #define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK … #define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK … #define MML2TLB_PERFCOUNTER1_CFG__ENABLE_MASK … #define MML2TLB_PERFCOUNTER1_CFG__CLEAR_MASK … //MML2TLB_PERFCOUNTER2_CFG #define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT … #define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT … #define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT … #define MML2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT … #define MML2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT … #define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK … #define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK … #define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK … #define MML2TLB_PERFCOUNTER2_CFG__ENABLE_MASK … #define MML2TLB_PERFCOUNTER2_CFG__CLEAR_MASK … //MML2TLB_PERFCOUNTER3_CFG #define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT … #define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT … #define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT … #define MML2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT … #define MML2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT … #define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK … #define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK … #define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK … #define MML2TLB_PERFCOUNTER3_CFG__ENABLE_MASK … #define MML2TLB_PERFCOUNTER3_CFG__CLEAR_MASK … //MML2TLB_PERFCOUNTER_RSLT_CNTL #define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT … #define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT … #define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT … #define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT … #define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT … #define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT … #define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK … #define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK … #define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK … #define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK … #define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK … #define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK … // addressBlock: mmhub_mmutcl2_mml2tlbprdec //MML2TLB_PERFCOUNTER_LO #define MML2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT … #define MML2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK … //MML2TLB_PERFCOUNTER_HI #define MML2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT … #define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT … #define MML2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK … #define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK … #endif
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