/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef _gc_9_4_3_OFFSET_HEADER #define _gc_9_4_3_OFFSET_HEADER // addressBlock: xcd0_gc_grbmdec // base address: 0x8000 #define regGRBM_CNTL … #define regGRBM_CNTL_BASE_IDX … #define regGRBM_SKEW_CNTL … #define regGRBM_SKEW_CNTL_BASE_IDX … #define regGRBM_STATUS2 … #define regGRBM_STATUS2_BASE_IDX … #define regGRBM_PWR_CNTL … #define regGRBM_PWR_CNTL_BASE_IDX … #define regGRBM_STATUS … #define regGRBM_STATUS_BASE_IDX … #define regGRBM_STATUS_SE0 … #define regGRBM_STATUS_SE0_BASE_IDX … #define regGRBM_STATUS_SE1 … #define regGRBM_STATUS_SE1_BASE_IDX … #define regGRBM_SOFT_RESET … #define regGRBM_SOFT_RESET_BASE_IDX … #define regGRBM_GFX_CLKEN_CNTL … #define regGRBM_GFX_CLKEN_CNTL_BASE_IDX … #define regGRBM_WAIT_IDLE_CLOCKS … #define regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX … #define regGRBM_STATUS_SE2 … #define regGRBM_STATUS_SE2_BASE_IDX … #define regGRBM_STATUS_SE3 … #define regGRBM_STATUS_SE3_BASE_IDX … #define regGRBM_READ_ERROR … #define regGRBM_READ_ERROR_BASE_IDX … #define regGRBM_READ_ERROR2 … #define regGRBM_READ_ERROR2_BASE_IDX … #define regGRBM_INT_CNTL … #define regGRBM_INT_CNTL_BASE_IDX … #define regGRBM_TRAP_OP … #define regGRBM_TRAP_OP_BASE_IDX … #define regGRBM_TRAP_ADDR … #define regGRBM_TRAP_ADDR_BASE_IDX … #define regGRBM_TRAP_ADDR_MSK … #define regGRBM_TRAP_ADDR_MSK_BASE_IDX … #define regGRBM_TRAP_WD … #define regGRBM_TRAP_WD_BASE_IDX … #define regGRBM_TRAP_WD_MSK … #define regGRBM_TRAP_WD_MSK_BASE_IDX … #define regGRBM_WRITE_ERROR … #define regGRBM_WRITE_ERROR_BASE_IDX … #define regGRBM_IOV_ERROR … #define regGRBM_IOV_ERROR_BASE_IDX … #define regGRBM_CHIP_REVISION … #define regGRBM_CHIP_REVISION_BASE_IDX … #define regGRBM_GFX_CNTL … #define regGRBM_GFX_CNTL_BASE_IDX … #define regGRBM_RSMU_CFG … #define regGRBM_RSMU_CFG_BASE_IDX … #define regGRBM_IH_CREDIT … #define regGRBM_IH_CREDIT_BASE_IDX … #define regGRBM_PWR_CNTL2 … #define regGRBM_PWR_CNTL2_BASE_IDX … #define regGRBM_UTCL2_INVAL_RANGE_START … #define regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX … #define regGRBM_UTCL2_INVAL_RANGE_END … #define regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX … #define regGRBM_RSMU_READ_ERROR … #define regGRBM_RSMU_READ_ERROR_BASE_IDX … #define regGRBM_CHICKEN_BITS … #define regGRBM_CHICKEN_BITS_BASE_IDX … #define regGRBM_FENCE_RANGE0 … #define regGRBM_FENCE_RANGE0_BASE_IDX … #define regGRBM_FENCE_RANGE1 … #define regGRBM_FENCE_RANGE1_BASE_IDX … #define regGRBM_IOV_READ_ERROR … #define regGRBM_IOV_READ_ERROR_BASE_IDX … #define regGRBM_NOWHERE … #define regGRBM_NOWHERE_BASE_IDX … #define regGRBM_SCRATCH_REG0 … #define regGRBM_SCRATCH_REG0_BASE_IDX … #define regGRBM_SCRATCH_REG1 … #define regGRBM_SCRATCH_REG1_BASE_IDX … #define regGRBM_SCRATCH_REG2 … #define regGRBM_SCRATCH_REG2_BASE_IDX … #define regGRBM_SCRATCH_REG3 … #define regGRBM_SCRATCH_REG3_BASE_IDX … #define regGRBM_SCRATCH_REG4 … #define regGRBM_SCRATCH_REG4_BASE_IDX … #define regGRBM_SCRATCH_REG5 … #define regGRBM_SCRATCH_REG5_BASE_IDX … #define regGRBM_SCRATCH_REG6 … #define regGRBM_SCRATCH_REG6_BASE_IDX … #define regGRBM_SCRATCH_REG7 … #define regGRBM_SCRATCH_REG7_BASE_IDX … #define regVIOLATION_DATA_ASYNC_VF_PROG … #define regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX … // addressBlock: xcd0_gc_cpdec // base address: 0x8200 #define regCP_CPC_DEBUG_CNTL … #define regCP_CPC_DEBUG_CNTL_BASE_IDX … #define regCP_CPF_DEBUG_CNTL … #define regCP_CPF_DEBUG_CNTL_BASE_IDX … #define regCP_CPC_STATUS … #define regCP_CPC_STATUS_BASE_IDX … #define regCP_CPC_BUSY_STAT … #define regCP_CPC_BUSY_STAT_BASE_IDX … #define regCP_CPC_STALLED_STAT1 … #define regCP_CPC_STALLED_STAT1_BASE_IDX … #define regCP_CPF_STATUS … #define regCP_CPF_STATUS_BASE_IDX … #define regCP_CPF_BUSY_STAT … #define regCP_CPF_BUSY_STAT_BASE_IDX … #define regCP_CPF_STALLED_STAT1 … #define regCP_CPF_STALLED_STAT1_BASE_IDX … #define regCP_CPC_GRBM_FREE_COUNT … #define regCP_CPC_GRBM_FREE_COUNT_BASE_IDX … #define regCP_CPC_PRIV_VIOLATION_ADDR … #define regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX … #define regCP_MEC_CNTL … #define regCP_MEC_CNTL_BASE_IDX … #define regCP_MEC_ME1_HEADER_DUMP … #define regCP_MEC_ME1_HEADER_DUMP_BASE_IDX … #define regCP_MEC_ME2_HEADER_DUMP … #define regCP_MEC_ME2_HEADER_DUMP_BASE_IDX … #define regCP_CPC_SCRATCH_INDEX … #define regCP_CPC_SCRATCH_INDEX_BASE_IDX … #define regCP_CPC_SCRATCH_DATA … #define regCP_CPC_SCRATCH_DATA_BASE_IDX … #define regCP_CPF_GRBM_FREE_COUNT … #define regCP_CPF_GRBM_FREE_COUNT_BASE_IDX … #define regCP_CPC_HALT_HYST_COUNT … #define regCP_CPC_HALT_HYST_COUNT_BASE_IDX … #define regCP_CE_COMPARE_COUNT … #define regCP_CE_COMPARE_COUNT_BASE_IDX … #define regCP_CE_DE_COUNT … #define regCP_CE_DE_COUNT_BASE_IDX … #define regCP_DE_CE_COUNT … #define regCP_DE_CE_COUNT_BASE_IDX … #define regCP_DE_LAST_INVAL_COUNT … #define regCP_DE_LAST_INVAL_COUNT_BASE_IDX … #define regCP_DE_DE_COUNT … #define regCP_DE_DE_COUNT_BASE_IDX … #define regCP_STALLED_STAT3 … #define regCP_STALLED_STAT3_BASE_IDX … #define regCP_STALLED_STAT1 … #define regCP_STALLED_STAT1_BASE_IDX … #define regCP_STALLED_STAT2 … #define regCP_STALLED_STAT2_BASE_IDX … #define regCP_BUSY_STAT … #define regCP_BUSY_STAT_BASE_IDX … #define regCP_STAT … #define regCP_STAT_BASE_IDX … #define regCP_ME_HEADER_DUMP … #define regCP_ME_HEADER_DUMP_BASE_IDX … #define regCP_PFP_HEADER_DUMP … #define regCP_PFP_HEADER_DUMP_BASE_IDX … #define regCP_GRBM_FREE_COUNT … #define regCP_GRBM_FREE_COUNT_BASE_IDX … #define regCP_CE_HEADER_DUMP … #define regCP_CE_HEADER_DUMP_BASE_IDX … #define regCP_PFP_INSTR_PNTR … #define regCP_PFP_INSTR_PNTR_BASE_IDX … #define regCP_ME_INSTR_PNTR … #define regCP_ME_INSTR_PNTR_BASE_IDX … #define regCP_CE_INSTR_PNTR … #define regCP_CE_INSTR_PNTR_BASE_IDX … #define regCP_MEC1_INSTR_PNTR … #define regCP_MEC1_INSTR_PNTR_BASE_IDX … #define regCP_MEC2_INSTR_PNTR … #define regCP_MEC2_INSTR_PNTR_BASE_IDX … #define regCP_CSF_STAT … #define regCP_CSF_STAT_BASE_IDX … #define regCP_ME_CNTL … #define regCP_ME_CNTL_BASE_IDX … #define regCP_CNTX_STAT … #define regCP_CNTX_STAT_BASE_IDX … #define regCP_ME_PREEMPTION … #define regCP_ME_PREEMPTION_BASE_IDX … #define regCP_ROQ_THRESHOLDS … #define regCP_ROQ_THRESHOLDS_BASE_IDX … #define regCP_MEQ_STQ_THRESHOLD … #define regCP_MEQ_STQ_THRESHOLD_BASE_IDX … #define regCP_RB2_RPTR … #define regCP_RB2_RPTR_BASE_IDX … #define regCP_RB1_RPTR … #define regCP_RB1_RPTR_BASE_IDX … #define regCP_RB0_RPTR … #define regCP_RB0_RPTR_BASE_IDX … #define regCP_RB_RPTR … #define regCP_RB_RPTR_BASE_IDX … #define regCP_RB_WPTR_DELAY … #define regCP_RB_WPTR_DELAY_BASE_IDX … #define regCP_RB_WPTR_POLL_CNTL … #define regCP_RB_WPTR_POLL_CNTL_BASE_IDX … #define regCP_ROQ1_THRESHOLDS … #define regCP_ROQ1_THRESHOLDS_BASE_IDX … #define regCP_ROQ2_THRESHOLDS … #define regCP_ROQ2_THRESHOLDS_BASE_IDX … #define regCP_STQ_THRESHOLDS … #define regCP_STQ_THRESHOLDS_BASE_IDX … #define regCP_QUEUE_THRESHOLDS … #define regCP_QUEUE_THRESHOLDS_BASE_IDX … #define regCP_MEQ_THRESHOLDS … #define regCP_MEQ_THRESHOLDS_BASE_IDX … #define regCP_ROQ_AVAIL … #define regCP_ROQ_AVAIL_BASE_IDX … #define regCP_STQ_AVAIL … #define regCP_STQ_AVAIL_BASE_IDX … #define regCP_ROQ2_AVAIL … #define regCP_ROQ2_AVAIL_BASE_IDX … #define regCP_MEQ_AVAIL … #define regCP_MEQ_AVAIL_BASE_IDX … #define regCP_CMD_INDEX … #define regCP_CMD_INDEX_BASE_IDX … #define regCP_CMD_DATA … #define regCP_CMD_DATA_BASE_IDX … #define regCP_ROQ_RB_STAT … #define regCP_ROQ_RB_STAT_BASE_IDX … #define regCP_ROQ_IB1_STAT … #define regCP_ROQ_IB1_STAT_BASE_IDX … #define regCP_ROQ_IB2_STAT … #define regCP_ROQ_IB2_STAT_BASE_IDX … #define regCP_STQ_STAT … #define regCP_STQ_STAT_BASE_IDX … #define regCP_STQ_WR_STAT … #define regCP_STQ_WR_STAT_BASE_IDX … #define regCP_MEQ_STAT … #define regCP_MEQ_STAT_BASE_IDX … #define regCP_CEQ1_AVAIL … #define regCP_CEQ1_AVAIL_BASE_IDX … #define regCP_CEQ2_AVAIL … #define regCP_CEQ2_AVAIL_BASE_IDX … #define regCP_CE_ROQ_RB_STAT … #define regCP_CE_ROQ_RB_STAT_BASE_IDX … #define regCP_CE_ROQ_IB1_STAT … #define regCP_CE_ROQ_IB1_STAT_BASE_IDX … #define regCP_CE_ROQ_IB2_STAT … #define regCP_CE_ROQ_IB2_STAT_BASE_IDX … #define regCP_INT_STAT_DEBUG … #define regCP_INT_STAT_DEBUG_BASE_IDX … #define regCP_DEBUG_CNTL … #define regCP_DEBUG_CNTL_BASE_IDX … #define regCP_PRIV_VIOLATION_ADDR … #define regCP_PRIV_VIOLATION_ADDR_BASE_IDX … // addressBlock: xcd0_gc_padec // base address: 0x8800 #define regVGT_VTX_VECT_EJECT_REG … #define regVGT_VTX_VECT_EJECT_REG_BASE_IDX … #define regVGT_DMA_DATA_FIFO_DEPTH … #define regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX … #define regVGT_DMA_REQ_FIFO_DEPTH … #define regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX … #define regVGT_DRAW_INIT_FIFO_DEPTH … #define regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX … #define regVGT_LAST_COPY_STATE … #define regVGT_LAST_COPY_STATE_BASE_IDX … #define regVGT_CACHE_INVALIDATION … #define regVGT_CACHE_INVALIDATION_BASE_IDX … #define regVGT_RESET_DEBUG … #define regVGT_RESET_DEBUG_BASE_IDX … #define regVGT_STRMOUT_DELAY … #define regVGT_STRMOUT_DELAY_BASE_IDX … #define regVGT_FIFO_DEPTHS … #define regVGT_FIFO_DEPTHS_BASE_IDX … #define regVGT_GS_VERTEX_REUSE … #define regVGT_GS_VERTEX_REUSE_BASE_IDX … #define regVGT_MC_LAT_CNTL … #define regVGT_MC_LAT_CNTL_BASE_IDX … #define regIA_CNTL_STATUS … #define regIA_CNTL_STATUS_BASE_IDX … #define regVGT_CNTL_STATUS … #define regVGT_CNTL_STATUS_BASE_IDX … #define regWD_CNTL_STATUS … #define regWD_CNTL_STATUS_BASE_IDX … #define regCC_GC_PRIM_CONFIG … #define regCC_GC_PRIM_CONFIG_BASE_IDX … #define regGC_USER_PRIM_CONFIG … #define regGC_USER_PRIM_CONFIG_BASE_IDX … #define regWD_QOS … #define regWD_QOS_BASE_IDX … #define regWD_UTCL1_CNTL … #define regWD_UTCL1_CNTL_BASE_IDX … #define regWD_UTCL1_STATUS … #define regWD_UTCL1_STATUS_BASE_IDX … #define regIA_UTCL1_CNTL … #define regIA_UTCL1_CNTL_BASE_IDX … #define regIA_UTCL1_STATUS … #define regIA_UTCL1_STATUS_BASE_IDX … #define regVGT_SYS_CONFIG … #define regVGT_SYS_CONFIG_BASE_IDX … #define regVGT_VS_MAX_WAVE_ID … #define regVGT_VS_MAX_WAVE_ID_BASE_IDX … #define regVGT_GS_MAX_WAVE_ID … #define regVGT_GS_MAX_WAVE_ID_BASE_IDX … #define regGFX_PIPE_CONTROL … #define regGFX_PIPE_CONTROL_BASE_IDX … #define regCC_GC_SHADER_ARRAY_CONFIG … #define regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX … #define regGC_USER_SHADER_ARRAY_CONFIG … #define regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX … #define regVGT_DMA_PRIMITIVE_TYPE … #define regVGT_DMA_PRIMITIVE_TYPE_BASE_IDX … #define regVGT_DMA_CONTROL … #define regVGT_DMA_CONTROL_BASE_IDX … #define regVGT_DMA_LS_HS_CONFIG … #define regVGT_DMA_LS_HS_CONFIG_BASE_IDX … #define regWD_BUF_RESOURCE_1 … #define regWD_BUF_RESOURCE_1_BASE_IDX … #define regWD_BUF_RESOURCE_2 … #define regWD_BUF_RESOURCE_2_BASE_IDX … #define regPA_CL_CNTL_STATUS … #define regPA_CL_CNTL_STATUS_BASE_IDX … #define regPA_CL_ENHANCE … #define regPA_CL_ENHANCE_BASE_IDX … #define regPA_CL_RESET_DEBUG … #define regPA_CL_RESET_DEBUG_BASE_IDX … #define regPA_SU_CNTL_STATUS … #define regPA_SU_CNTL_STATUS_BASE_IDX … #define regPA_SC_FIFO_DEPTH_CNTL … #define regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX … #define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK … #define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX … #define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK … #define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX … #define regPA_SC_TRAP_SCREEN_HV_LOCK … #define regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX … #define regPA_SC_FORCE_EOV_MAX_CNTS … #define regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX … #define regPA_SC_BINNER_EVENT_CNTL_0 … #define regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX … #define regPA_SC_BINNER_EVENT_CNTL_1 … #define regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX … #define regPA_SC_BINNER_EVENT_CNTL_2 … #define regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX … #define regPA_SC_BINNER_EVENT_CNTL_3 … #define regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX … #define regPA_SC_BINNER_TIMEOUT_COUNTER … #define regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX … #define regPA_SC_BINNER_PERF_CNTL_0 … #define regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX … #define regPA_SC_BINNER_PERF_CNTL_1 … #define regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX … #define regPA_SC_BINNER_PERF_CNTL_2 … #define regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX … #define regPA_SC_BINNER_PERF_CNTL_3 … #define regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX … #define regPA_SC_ENHANCE_2 … #define regPA_SC_ENHANCE_2_BASE_IDX … #define regPA_SC_FIFO_SIZE … #define regPA_SC_FIFO_SIZE_BASE_IDX … #define regPA_SC_IF_FIFO_SIZE … #define regPA_SC_IF_FIFO_SIZE_BASE_IDX … #define regPA_SC_PKR_WAVE_TABLE_CNTL … #define regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX … #define regPA_UTCL1_CNTL1 … #define regPA_UTCL1_CNTL1_BASE_IDX … #define regPA_UTCL1_CNTL2 … #define regPA_UTCL1_CNTL2_BASE_IDX … #define regPA_SIDEBAND_REQUEST_DELAYS … #define regPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX … #define regPA_SC_ENHANCE … #define regPA_SC_ENHANCE_BASE_IDX … #define regPA_SC_ENHANCE_1 … #define regPA_SC_ENHANCE_1_BASE_IDX … #define regPA_SC_DSM_CNTL … #define regPA_SC_DSM_CNTL_BASE_IDX … #define regPA_SC_TILE_STEERING_CREST_OVERRIDE … #define regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX … // addressBlock: xcd0_gc_sqdec // base address: 0x8c00 #define regSQ_CONFIG … #define regSQ_CONFIG_BASE_IDX … #define regSQC_CONFIG … #define regSQC_CONFIG_BASE_IDX … #define regLDS_CONFIG … #define regLDS_CONFIG_BASE_IDX … #define regSQ_RANDOM_WAVE_PRI … #define regSQ_RANDOM_WAVE_PRI_BASE_IDX … #define regSQ_REG_CREDITS … #define regSQ_REG_CREDITS_BASE_IDX … #define regSQ_FIFO_SIZES … #define regSQ_FIFO_SIZES_BASE_IDX … #define regSQ_DSM_CNTL … #define regSQ_DSM_CNTL_BASE_IDX … #define regSQ_DSM_CNTL2 … #define regSQ_DSM_CNTL2_BASE_IDX … #define regSQ_RUNTIME_CONFIG … #define regSQ_RUNTIME_CONFIG_BASE_IDX … #define regSQ_DEBUG_STS_GLOBAL … #define regSQ_DEBUG_STS_GLOBAL_BASE_IDX … #define regSH_MEM_BASES … #define regSH_MEM_BASES_BASE_IDX … #define regSQ_TIMEOUT_CONFIG … #define regSQ_TIMEOUT_CONFIG_BASE_IDX … #define regSQ_TIMEOUT_STATUS … #define regSQ_TIMEOUT_STATUS_BASE_IDX … #define regSH_MEM_CONFIG … #define regSH_MEM_CONFIG_BASE_IDX … #define regSP_MFMA_PORTD_RD_CONFIG … #define regSP_MFMA_PORTD_RD_CONFIG_BASE_IDX … #define regSH_CAC_CONFIG … #define regSH_CAC_CONFIG_BASE_IDX … #define regSQ_DEBUG_STS_GLOBAL2 … #define regSQ_DEBUG_STS_GLOBAL2_BASE_IDX … #define regSQ_DEBUG_STS_GLOBAL3 … #define regSQ_DEBUG_STS_GLOBAL3_BASE_IDX … #define regCC_GC_SHADER_RATE_CONFIG … #define regCC_GC_SHADER_RATE_CONFIG_BASE_IDX … #define regGC_USER_SHADER_RATE_CONFIG … #define regGC_USER_SHADER_RATE_CONFIG_BASE_IDX … #define regSQ_INTERRUPT_AUTO_MASK … #define regSQ_INTERRUPT_AUTO_MASK_BASE_IDX … #define regSQ_INTERRUPT_MSG_CTRL … #define regSQ_INTERRUPT_MSG_CTRL_BASE_IDX … #define regSQ_DEBUG_PERFCOUNT_TRAP … #define regSQ_DEBUG_PERFCOUNT_TRAP_BASE_IDX … #define regSQ_UTCL1_CNTL1 … #define regSQ_UTCL1_CNTL1_BASE_IDX … #define regSQ_UTCL1_CNTL2 … #define regSQ_UTCL1_CNTL2_BASE_IDX … #define regSQ_UTCL1_STATUS … #define regSQ_UTCL1_STATUS_BASE_IDX … #define regSQ_FED_INTERRUPT_STATUS … #define regSQ_FED_INTERRUPT_STATUS_BASE_IDX … #define regSQ_CGTS_CONFIG … #define regSQ_CGTS_CONFIG_BASE_IDX … #define regSQ_SHADER_TBA_LO … #define regSQ_SHADER_TBA_LO_BASE_IDX … #define regSQ_SHADER_TBA_HI … #define regSQ_SHADER_TBA_HI_BASE_IDX … #define regSQ_SHADER_TMA_LO … #define regSQ_SHADER_TMA_LO_BASE_IDX … #define regSQ_SHADER_TMA_HI … #define regSQ_SHADER_TMA_HI_BASE_IDX … #define regSQC_DSM_CNTL … #define regSQC_DSM_CNTL_BASE_IDX … #define regSQC_DSM_CNTLA … #define regSQC_DSM_CNTLA_BASE_IDX … #define regSQC_DSM_CNTLB … #define regSQC_DSM_CNTLB_BASE_IDX … #define regSQC_DSM_CNTL2 … #define regSQC_DSM_CNTL2_BASE_IDX … #define regSQC_DSM_CNTL2A … #define regSQC_DSM_CNTL2A_BASE_IDX … #define regSQC_DSM_CNTL2B … #define regSQC_DSM_CNTL2B_BASE_IDX … #define regSQC_DSM_CNTL2E … #define regSQC_DSM_CNTL2E_BASE_IDX … #define regSQC_EDC_FUE_CNTL … #define regSQC_EDC_FUE_CNTL_BASE_IDX … #define regSQC_EDC_CNT2 … #define regSQC_EDC_CNT2_BASE_IDX … #define regSQC_EDC_CNT3 … #define regSQC_EDC_CNT3_BASE_IDX … #define regSQC_EDC_PARITY_CNT3 … #define regSQC_EDC_PARITY_CNT3_BASE_IDX … #define regSQ_DEBUG … #define regSQ_DEBUG_BASE_IDX … #define regSQ_PERF_SNAPSHOT_CTRL … #define regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX … #define regSQ_DEBUG_FOR_INTERNAL_CTRL … #define regSQ_DEBUG_FOR_INTERNAL_CTRL_BASE_IDX … #define regSQ_REG_TIMESTAMP … #define regSQ_REG_TIMESTAMP_BASE_IDX … #define regSQ_CMD_TIMESTAMP … #define regSQ_CMD_TIMESTAMP_BASE_IDX … #define regSQ_HOSTTRAP_STATUS … #define regSQ_HOSTTRAP_STATUS_BASE_IDX … #define regSQ_IND_INDEX … #define regSQ_IND_INDEX_BASE_IDX … #define regSQ_IND_DATA … #define regSQ_IND_DATA_BASE_IDX … #define regSQ_CONFIG1 … #define regSQ_CONFIG1_BASE_IDX … #define regSQ_CMD … #define regSQ_CMD_BASE_IDX … #define regSQ_TIME_HI … #define regSQ_TIME_HI_BASE_IDX … #define regSQ_TIME_LO … #define regSQ_TIME_LO_BASE_IDX … #define regSQ_DS_0 … #define regSQ_DS_0_BASE_IDX … #define regSQ_DS_1 … #define regSQ_DS_1_BASE_IDX … #define regSQ_EXP_0 … #define regSQ_EXP_0_BASE_IDX … #define regSQ_EXP_1 … #define regSQ_EXP_1_BASE_IDX … #define regSQ_FLAT_0 … #define regSQ_FLAT_0_BASE_IDX … #define regSQ_FLAT_1 … #define regSQ_FLAT_1_BASE_IDX … #define regSQ_GLBL_0 … #define regSQ_GLBL_0_BASE_IDX … #define regSQ_GLBL_1 … #define regSQ_GLBL_1_BASE_IDX … #define regSQ_INST … #define regSQ_INST_BASE_IDX … #define regSQ_MIMG_0 … #define regSQ_MIMG_0_BASE_IDX … #define regSQ_MIMG_1 … #define regSQ_MIMG_1_BASE_IDX … #define regSQ_MTBUF_0 … #define regSQ_MTBUF_0_BASE_IDX … #define regSQ_MTBUF_1 … #define regSQ_MTBUF_1_BASE_IDX … #define regSQ_MUBUF_0 … #define regSQ_MUBUF_0_BASE_IDX … #define regSQ_MUBUF_1 … #define regSQ_MUBUF_1_BASE_IDX … #define regSQ_SCRATCH_0 … #define regSQ_SCRATCH_0_BASE_IDX … #define regSQ_SCRATCH_1 … #define regSQ_SCRATCH_1_BASE_IDX … #define regSQ_SMEM_0 … #define regSQ_SMEM_0_BASE_IDX … #define regSQ_SMEM_1 … #define regSQ_SMEM_1_BASE_IDX … #define regSQ_SOP1 … #define regSQ_SOP1_BASE_IDX … #define regSQ_SOP2 … #define regSQ_SOP2_BASE_IDX … #define regSQ_SOPC … #define regSQ_SOPC_BASE_IDX … #define regSQ_SOPK … #define regSQ_SOPK_BASE_IDX … #define regSQ_SOPP … #define regSQ_SOPP_BASE_IDX … #define regSQ_VINTRP … #define regSQ_VINTRP_BASE_IDX … #define regSQ_VOP1 … #define regSQ_VOP1_BASE_IDX … #define regSQ_VOP2 … #define regSQ_VOP2_BASE_IDX … #define regSQ_VOP3P_0 … #define regSQ_VOP3P_0_BASE_IDX … #define regSQ_VOP3P_1 … #define regSQ_VOP3P_1_BASE_IDX … #define regSQ_VOP3P_MFMA_0 … #define regSQ_VOP3P_MFMA_0_BASE_IDX … #define regSQ_VOP3P_MFMA_1 … #define regSQ_VOP3P_MFMA_1_BASE_IDX … #define regSQ_VOP3_0 … #define regSQ_VOP3_0_BASE_IDX … #define regSQ_VOP3_0_SDST_ENC … #define regSQ_VOP3_0_SDST_ENC_BASE_IDX … #define regSQ_VOP3_1 … #define regSQ_VOP3_1_BASE_IDX … #define regSQ_VOPC … #define regSQ_VOPC_BASE_IDX … #define regSQ_VOP_DPP … #define regSQ_VOP_DPP_BASE_IDX … #define regSQ_VOP_SDWA … #define regSQ_VOP_SDWA_BASE_IDX … #define regSQ_VOP_SDWA_SDST_ENC … #define regSQ_VOP_SDWA_SDST_ENC_BASE_IDX … #define regSQ_LB_CTR_CTRL … #define regSQ_LB_CTR_CTRL_BASE_IDX … #define regSQ_LB_DATA0 … #define regSQ_LB_DATA0_BASE_IDX … #define regSQ_LB_DATA1 … #define regSQ_LB_DATA1_BASE_IDX … #define regSQ_LB_DATA2 … #define regSQ_LB_DATA2_BASE_IDX … #define regSQ_LB_DATA3 … #define regSQ_LB_DATA3_BASE_IDX … #define regSQ_LB_CTR_SEL … #define regSQ_LB_CTR_SEL_BASE_IDX … #define regSQ_LB_CTR0_CU … #define regSQ_LB_CTR0_CU_BASE_IDX … #define regSQ_LB_CTR1_CU … #define regSQ_LB_CTR1_CU_BASE_IDX … #define regSQ_LB_CTR2_CU … #define regSQ_LB_CTR2_CU_BASE_IDX … #define regSQ_LB_CTR3_CU … #define regSQ_LB_CTR3_CU_BASE_IDX … #define regSQC_EDC_CNT … #define regSQC_EDC_CNT_BASE_IDX … #define regSQ_EDC_SEC_CNT … #define regSQ_EDC_SEC_CNT_BASE_IDX … #define regSQ_EDC_DED_CNT … #define regSQ_EDC_DED_CNT_BASE_IDX … #define regSQ_EDC_INFO … #define regSQ_EDC_INFO_BASE_IDX … #define regSQ_EDC_CNT … #define regSQ_EDC_CNT_BASE_IDX … #define regSQ_EDC_FUE_CNTL … #define regSQ_EDC_FUE_CNTL_BASE_IDX … #define regSQ_THREAD_TRACE_WORD_CMN … #define regSQ_THREAD_TRACE_WORD_CMN_BASE_IDX … #define regSQ_THREAD_TRACE_WORD_EVENT … #define regSQ_THREAD_TRACE_WORD_EVENT_BASE_IDX … #define regSQ_THREAD_TRACE_WORD_INST … #define regSQ_THREAD_TRACE_WORD_INST_BASE_IDX … #define regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 … #define regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2_BASE_IDX … #define regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 … #define regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2_BASE_IDX … #define regSQ_THREAD_TRACE_WORD_ISSUE … #define regSQ_THREAD_TRACE_WORD_ISSUE_BASE_IDX … #define regSQ_THREAD_TRACE_WORD_MISC … #define regSQ_THREAD_TRACE_WORD_MISC_BASE_IDX … #define regSQ_THREAD_TRACE_WORD_PERF_1_OF_2 … #define regSQ_THREAD_TRACE_WORD_PERF_1_OF_2_BASE_IDX … #define regSQ_THREAD_TRACE_WORD_REG_1_OF_2 … #define regSQ_THREAD_TRACE_WORD_REG_1_OF_2_BASE_IDX … #define regSQ_THREAD_TRACE_WORD_REG_2_OF_2 … #define regSQ_THREAD_TRACE_WORD_REG_2_OF_2_BASE_IDX … #define regSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 … #define regSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2_BASE_IDX … #define regSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 … #define regSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2_BASE_IDX … #define regSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 … #define regSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2_BASE_IDX … #define regSQ_THREAD_TRACE_WORD_WAVE … #define regSQ_THREAD_TRACE_WORD_WAVE_BASE_IDX … #define regSQ_THREAD_TRACE_WORD_WAVE_START … #define regSQ_THREAD_TRACE_WORD_WAVE_START_BASE_IDX … #define regSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 … #define regSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2_BASE_IDX … #define regSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 … #define regSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2_BASE_IDX … #define regSQ_THREAD_TRACE_WORD_PERF_2_OF_2 … #define regSQ_THREAD_TRACE_WORD_PERF_2_OF_2_BASE_IDX … #define regSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 … #define regSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2_BASE_IDX … #define regSQ_WREXEC_EXEC_HI … #define regSQ_WREXEC_EXEC_HI_BASE_IDX … #define regSQ_WREXEC_EXEC_LO … #define regSQ_WREXEC_EXEC_LO_BASE_IDX … #define regSQ_BUF_RSRC_WORD0 … #define regSQ_BUF_RSRC_WORD0_BASE_IDX … #define regSQ_BUF_RSRC_WORD1 … #define regSQ_BUF_RSRC_WORD1_BASE_IDX … #define regSQ_BUF_RSRC_WORD2 … #define regSQ_BUF_RSRC_WORD2_BASE_IDX … #define regSQ_BUF_RSRC_WORD3 … #define regSQ_BUF_RSRC_WORD3_BASE_IDX … #define regSQ_IMG_RSRC_WORD0 … #define regSQ_IMG_RSRC_WORD0_BASE_IDX … #define regSQ_IMG_RSRC_WORD1 … #define regSQ_IMG_RSRC_WORD1_BASE_IDX … #define regSQ_IMG_RSRC_WORD2 … #define regSQ_IMG_RSRC_WORD2_BASE_IDX … #define regSQ_IMG_RSRC_WORD3 … #define regSQ_IMG_RSRC_WORD3_BASE_IDX … #define regSQ_IMG_RSRC_WORD4 … #define regSQ_IMG_RSRC_WORD4_BASE_IDX … #define regSQ_IMG_RSRC_WORD5 … #define regSQ_IMG_RSRC_WORD5_BASE_IDX … #define regSQ_IMG_RSRC_WORD6 … #define regSQ_IMG_RSRC_WORD6_BASE_IDX … #define regSQ_IMG_RSRC_WORD7 … #define regSQ_IMG_RSRC_WORD7_BASE_IDX … #define regSQ_IMG_SAMP_WORD0 … #define regSQ_IMG_SAMP_WORD0_BASE_IDX … #define regSQ_IMG_SAMP_WORD1 … #define regSQ_IMG_SAMP_WORD1_BASE_IDX … #define regSQ_IMG_SAMP_WORD2 … #define regSQ_IMG_SAMP_WORD2_BASE_IDX … #define regSQ_IMG_SAMP_WORD3 … #define regSQ_IMG_SAMP_WORD3_BASE_IDX … #define regSQ_FLAT_SCRATCH_WORD0 … #define regSQ_FLAT_SCRATCH_WORD0_BASE_IDX … #define regSQ_FLAT_SCRATCH_WORD1 … #define regSQ_FLAT_SCRATCH_WORD1_BASE_IDX … #define regSQ_M0_GPR_IDX_WORD … #define regSQ_M0_GPR_IDX_WORD_BASE_IDX … #define regSQC_ICACHE_UTCL1_CNTL1 … #define regSQC_ICACHE_UTCL1_CNTL1_BASE_IDX … #define regSQC_ICACHE_UTCL1_CNTL2 … #define regSQC_ICACHE_UTCL1_CNTL2_BASE_IDX … #define regSQC_DCACHE_UTCL1_CNTL1 … #define regSQC_DCACHE_UTCL1_CNTL1_BASE_IDX … #define regSQC_DCACHE_UTCL1_CNTL2 … #define regSQC_DCACHE_UTCL1_CNTL2_BASE_IDX … #define regSQC_ICACHE_UTCL1_STATUS … #define regSQC_ICACHE_UTCL1_STATUS_BASE_IDX … #define regSQC_DCACHE_UTCL1_STATUS … #define regSQC_DCACHE_UTCL1_STATUS_BASE_IDX … #define regSQC_UE_EDC_LO … #define regSQC_UE_EDC_LO_BASE_IDX … #define regSQC_UE_EDC_HI … #define regSQC_UE_EDC_HI_BASE_IDX … #define regSQC_CE_EDC_LO … #define regSQC_CE_EDC_LO_BASE_IDX … #define regSQC_CE_EDC_HI … #define regSQC_CE_EDC_HI_BASE_IDX … #define regSQ_UE_ERR_STATUS_LO … #define regSQ_UE_ERR_STATUS_LO_BASE_IDX … #define regSQ_UE_ERR_STATUS_HI … #define regSQ_UE_ERR_STATUS_HI_BASE_IDX … #define regSQ_CE_ERR_STATUS_LO … #define regSQ_CE_ERR_STATUS_LO_BASE_IDX … #define regSQ_CE_ERR_STATUS_HI … #define regSQ_CE_ERR_STATUS_HI_BASE_IDX … #define regLDS_UE_ERR_STATUS_LO … #define regLDS_UE_ERR_STATUS_LO_BASE_IDX … #define regLDS_UE_ERR_STATUS_HI … #define regLDS_UE_ERR_STATUS_HI_BASE_IDX … #define regLDS_CE_ERR_STATUS_LO … #define regLDS_CE_ERR_STATUS_LO_BASE_IDX … #define regLDS_CE_ERR_STATUS_HI … #define regLDS_CE_ERR_STATUS_HI_BASE_IDX … #define regSP0_UE_ERR_STATUS_LO … #define regSP0_UE_ERR_STATUS_LO_BASE_IDX … #define regSP0_UE_ERR_STATUS_HI … #define regSP0_UE_ERR_STATUS_HI_BASE_IDX … #define regSP0_CE_ERR_STATUS_LO … #define regSP0_CE_ERR_STATUS_LO_BASE_IDX … #define regSP0_CE_ERR_STATUS_HI … #define regSP0_CE_ERR_STATUS_HI_BASE_IDX … #define regSP1_UE_ERR_STATUS_LO … #define regSP1_UE_ERR_STATUS_LO_BASE_IDX … #define regSP1_UE_ERR_STATUS_HI … #define regSP1_UE_ERR_STATUS_HI_BASE_IDX … #define regSP1_CE_ERR_STATUS_LO … #define regSP1_CE_ERR_STATUS_LO_BASE_IDX … #define regSP1_CE_ERR_STATUS_HI … #define regSP1_CE_ERR_STATUS_HI_BASE_IDX … // addressBlock: xcd0_gc_shsdec // base address: 0x9000 #define regSX_DEBUG_BUSY … #define regSX_DEBUG_BUSY_BASE_IDX … #define regSX_DEBUG_1 … #define regSX_DEBUG_1_BASE_IDX … #define regSPI_PS_MAX_WAVE_ID … #define regSPI_PS_MAX_WAVE_ID_BASE_IDX … #define regSPI_START_PHASE … #define regSPI_START_PHASE_BASE_IDX … #define regSPI_GFX_CNTL … #define regSPI_GFX_CNTL_BASE_IDX … #define regSPI_DEBUG_READ … #define regSPI_DEBUG_READ_BASE_IDX … #define regSPI_DSM_CNTL … #define regSPI_DSM_CNTL_BASE_IDX … #define regSPI_DSM_CNTL2 … #define regSPI_DSM_CNTL2_BASE_IDX … #define regSPI_EDC_CNT … #define regSPI_EDC_CNT_BASE_IDX … #define regSPI_UE_ERR_STATUS_LO … #define regSPI_UE_ERR_STATUS_LO_BASE_IDX … #define regSPI_UE_ERR_STATUS_HI … #define regSPI_UE_ERR_STATUS_HI_BASE_IDX … #define regSPI_CE_ERR_STATUS_LO … #define regSPI_CE_ERR_STATUS_LO_BASE_IDX … #define regSPI_CE_ERR_STATUS_HI … #define regSPI_CE_ERR_STATUS_HI_BASE_IDX … #define regSPI_DEBUG_BUSY … #define regSPI_DEBUG_BUSY_BASE_IDX … #define regSPI_CONFIG_PS_CU_EN … #define regSPI_CONFIG_PS_CU_EN_BASE_IDX … #define regSPI_WF_LIFETIME_CNTL … #define regSPI_WF_LIFETIME_CNTL_BASE_IDX … #define regSPI_WF_LIFETIME_LIMIT_0 … #define regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX … #define regSPI_WF_LIFETIME_LIMIT_1 … #define regSPI_WF_LIFETIME_LIMIT_1_BASE_IDX … #define regSPI_WF_LIFETIME_LIMIT_2 … #define regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX … #define regSPI_WF_LIFETIME_LIMIT_3 … #define regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX … #define regSPI_WF_LIFETIME_LIMIT_4 … #define regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX … #define regSPI_WF_LIFETIME_LIMIT_5 … #define regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX … #define regSPI_WF_LIFETIME_LIMIT_6 … #define regSPI_WF_LIFETIME_LIMIT_6_BASE_IDX … #define regSPI_WF_LIFETIME_LIMIT_7 … #define regSPI_WF_LIFETIME_LIMIT_7_BASE_IDX … #define regSPI_WF_LIFETIME_LIMIT_8 … #define regSPI_WF_LIFETIME_LIMIT_8_BASE_IDX … #define regSPI_WF_LIFETIME_LIMIT_9 … #define regSPI_WF_LIFETIME_LIMIT_9_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_0 … #define regSPI_WF_LIFETIME_STATUS_0_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_1 … #define regSPI_WF_LIFETIME_STATUS_1_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_2 … #define regSPI_WF_LIFETIME_STATUS_2_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_3 … #define regSPI_WF_LIFETIME_STATUS_3_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_4 … #define regSPI_WF_LIFETIME_STATUS_4_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_5 … #define regSPI_WF_LIFETIME_STATUS_5_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_6 … #define regSPI_WF_LIFETIME_STATUS_6_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_7 … #define regSPI_WF_LIFETIME_STATUS_7_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_8 … #define regSPI_WF_LIFETIME_STATUS_8_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_9 … #define regSPI_WF_LIFETIME_STATUS_9_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_10 … #define regSPI_WF_LIFETIME_STATUS_10_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_11 … #define regSPI_WF_LIFETIME_STATUS_11_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_12 … #define regSPI_WF_LIFETIME_STATUS_12_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_13 … #define regSPI_WF_LIFETIME_STATUS_13_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_14 … #define regSPI_WF_LIFETIME_STATUS_14_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_15 … #define regSPI_WF_LIFETIME_STATUS_15_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_16 … #define regSPI_WF_LIFETIME_STATUS_16_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_17 … #define regSPI_WF_LIFETIME_STATUS_17_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_18 … #define regSPI_WF_LIFETIME_STATUS_18_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_19 … #define regSPI_WF_LIFETIME_STATUS_19_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_20 … #define regSPI_WF_LIFETIME_STATUS_20_BASE_IDX … #define regSPI_WF_LIFETIME_DEBUG … #define regSPI_WF_LIFETIME_DEBUG_BASE_IDX … #define regSPI_LB_CTR_CTRL … #define regSPI_LB_CTR_CTRL_BASE_IDX … #define regSPI_LB_CU_MASK … #define regSPI_LB_CU_MASK_BASE_IDX … #define regSPI_LB_DATA_REG … #define regSPI_LB_DATA_REG_BASE_IDX … #define regSPI_PG_ENABLE_STATIC_CU_MASK … #define regSPI_PG_ENABLE_STATIC_CU_MASK_BASE_IDX … #define regSPI_GDS_CREDITS … #define regSPI_GDS_CREDITS_BASE_IDX … #define regSPI_SX_EXPORT_BUFFER_SIZES … #define regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX … #define regSPI_SX_SCOREBOARD_BUFFER_SIZES … #define regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX … #define regSPI_CSQ_WF_ACTIVE_STATUS … #define regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX … #define regSPI_CSQ_WF_ACTIVE_COUNT_0 … #define regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX … #define regSPI_CSQ_WF_ACTIVE_COUNT_1 … #define regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX … #define regSPI_CSQ_WF_ACTIVE_COUNT_2 … #define regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX … #define regSPI_CSQ_WF_ACTIVE_COUNT_3 … #define regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX … #define regSPI_CSQ_WF_ACTIVE_COUNT_4 … #define regSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX … #define regSPI_CSQ_WF_ACTIVE_COUNT_5 … #define regSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX … #define regSPI_CSQ_WF_ACTIVE_COUNT_6 … #define regSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX … #define regSPI_CSQ_WF_ACTIVE_COUNT_7 … #define regSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX … #define regSPI_LB_DATA_WAVES … #define regSPI_LB_DATA_WAVES_BASE_IDX … #define regSPI_LB_DATA_PERCU_WAVE_HSGS … #define regSPI_LB_DATA_PERCU_WAVE_HSGS_BASE_IDX … #define regSPI_LB_DATA_PERCU_WAVE_VSPS … #define regSPI_LB_DATA_PERCU_WAVE_VSPS_BASE_IDX … #define regSPI_LB_DATA_PERCU_WAVE_CS … #define regSPI_LB_DATA_PERCU_WAVE_CS_BASE_IDX … #define regSPIS_DEBUG_READ … #define regSPIS_DEBUG_READ_BASE_IDX … #define regBCI_DEBUG_READ … #define regBCI_DEBUG_READ_BASE_IDX … #define regSPI_P0_TRAP_SCREEN_PSBA_LO … #define regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX … #define regSPI_P0_TRAP_SCREEN_PSBA_HI … #define regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX … #define regSPI_P0_TRAP_SCREEN_PSMA_LO … #define regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX … #define regSPI_P0_TRAP_SCREEN_PSMA_HI … #define regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX … #define regSPI_P0_TRAP_SCREEN_GPR_MIN … #define regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX … #define regSPI_P1_TRAP_SCREEN_PSBA_LO … #define regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX … #define regSPI_P1_TRAP_SCREEN_PSBA_HI … #define regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX … #define regSPI_P1_TRAP_SCREEN_PSMA_LO … #define regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX … #define regSPI_P1_TRAP_SCREEN_PSMA_HI … #define regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX … #define regSPI_P1_TRAP_SCREEN_GPR_MIN … #define regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX … // addressBlock: xcd0_gc_tpdec // base address: 0x9400 #define regTD_CNTL … #define regTD_CNTL_BASE_IDX … #define regTD_STATUS … #define regTD_STATUS_BASE_IDX … #define regTD_POWER_CNTL … #define regTD_POWER_CNTL_BASE_IDX … #define regTD_UE_EDC_LO … #define regTD_UE_EDC_LO_BASE_IDX … #define regTD_UE_EDC_HI … #define regTD_UE_EDC_HI_BASE_IDX … #define regTD_CE_EDC_LO … #define regTD_CE_EDC_LO_BASE_IDX … #define regTD_CE_EDC_HI … #define regTD_CE_EDC_HI_BASE_IDX … #define regTD_DSM_CNTL … #define regTD_DSM_CNTL_BASE_IDX … #define regTD_DSM_CNTL2 … #define regTD_DSM_CNTL2_BASE_IDX … #define regTD_SCRATCH … #define regTD_SCRATCH_BASE_IDX … #define regTA_POWER_CNTL … #define regTA_POWER_CNTL_BASE_IDX … #define regTA_CNTL … #define regTA_CNTL_BASE_IDX … #define regTA_CNTL_AUX … #define regTA_CNTL_AUX_BASE_IDX … #define regTA_FEATURE_CNTL … #define regTA_FEATURE_CNTL_BASE_IDX … #define regTA_STATUS … #define regTA_STATUS_BASE_IDX … #define regTA_SCRATCH … #define regTA_SCRATCH_BASE_IDX … #define regTA_DSM_CNTL … #define regTA_DSM_CNTL_BASE_IDX … #define regTA_DSM_CNTL2 … #define regTA_DSM_CNTL2_BASE_IDX … #define regTA_UE_EDC_LO … #define regTA_UE_EDC_LO_BASE_IDX … #define regTA_UE_EDC_HI … #define regTA_UE_EDC_HI_BASE_IDX … #define regTA_CE_EDC_LO … #define regTA_CE_EDC_LO_BASE_IDX … #define regTA_CE_EDC_HI … #define regTA_CE_EDC_HI_BASE_IDX … // addressBlock: xcd0_gc_gdsdec // base address: 0x9700 #define regGDS_CONFIG … #define regGDS_CONFIG_BASE_IDX … #define regGDS_CNTL_STATUS … #define regGDS_CNTL_STATUS_BASE_IDX … #define regGDS_ENHANCE2 … #define regGDS_ENHANCE2_BASE_IDX … #define regGDS_PROTECTION_FAULT … #define regGDS_PROTECTION_FAULT_BASE_IDX … #define regGDS_VM_PROTECTION_FAULT … #define regGDS_VM_PROTECTION_FAULT_BASE_IDX … #define regGDS_EDC_CNT … #define regGDS_EDC_CNT_BASE_IDX … #define regGDS_EDC_GRBM_CNT … #define regGDS_EDC_GRBM_CNT_BASE_IDX … #define regGDS_EDC_OA_DED … #define regGDS_EDC_OA_DED_BASE_IDX … #define regGDS_DSM_CNTL … #define regGDS_DSM_CNTL_BASE_IDX … #define regGDS_EDC_OA_PHY_CNT … #define regGDS_EDC_OA_PHY_CNT_BASE_IDX … #define regGDS_EDC_OA_PIPE_CNT … #define regGDS_EDC_OA_PIPE_CNT_BASE_IDX … #define regGDS_DSM_CNTL2 … #define regGDS_DSM_CNTL2_BASE_IDX … #define regGDS_WD_GDS_CSB … #define regGDS_WD_GDS_CSB_BASE_IDX … #define regGDS_UE_ERR_STATUS_LO … #define regGDS_UE_ERR_STATUS_LO_BASE_IDX … #define regGDS_UE_ERR_STATUS_HI … #define regGDS_UE_ERR_STATUS_HI_BASE_IDX … #define regGDS_CE_ERR_STATUS_LO … #define regGDS_CE_ERR_STATUS_LO_BASE_IDX … #define regGDS_CE_ERR_STATUS_HI … #define regGDS_CE_ERR_STATUS_HI_BASE_IDX … // addressBlock: xcd0_gc_rbdec // base address: 0x9800 #define regDB_DEBUG … #define regDB_DEBUG_BASE_IDX … #define regDB_DEBUG2 … #define regDB_DEBUG2_BASE_IDX … #define regDB_DEBUG3 … #define regDB_DEBUG3_BASE_IDX … #define regDB_DEBUG4 … #define regDB_DEBUG4_BASE_IDX … #define regDB_CREDIT_LIMIT … #define regDB_CREDIT_LIMIT_BASE_IDX … #define regDB_WATERMARKS … #define regDB_WATERMARKS_BASE_IDX … #define regDB_SUBTILE_CONTROL … #define regDB_SUBTILE_CONTROL_BASE_IDX … #define regDB_FREE_CACHELINES … #define regDB_FREE_CACHELINES_BASE_IDX … #define regDB_FIFO_DEPTH1 … #define regDB_FIFO_DEPTH1_BASE_IDX … #define regDB_FIFO_DEPTH2 … #define regDB_FIFO_DEPTH2_BASE_IDX … #define regDB_EXCEPTION_CONTROL … #define regDB_EXCEPTION_CONTROL_BASE_IDX … #define regDB_RING_CONTROL … #define regDB_RING_CONTROL_BASE_IDX … #define regDB_MEM_ARB_WATERMARKS … #define regDB_MEM_ARB_WATERMARKS_BASE_IDX … #define regDB_RMI_CACHE_POLICY … #define regDB_RMI_CACHE_POLICY_BASE_IDX … #define regDB_DFSM_CONFIG … #define regDB_DFSM_CONFIG_BASE_IDX … #define regDB_DFSM_WATERMARK … #define regDB_DFSM_WATERMARK_BASE_IDX … #define regDB_DFSM_TILES_IN_FLIGHT … #define regDB_DFSM_TILES_IN_FLIGHT_BASE_IDX … #define regDB_DFSM_PRIMS_IN_FLIGHT … #define regDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX … #define regDB_DFSM_WATCHDOG … #define regDB_DFSM_WATCHDOG_BASE_IDX … #define regDB_DFSM_FLUSH_ENABLE … #define regDB_DFSM_FLUSH_ENABLE_BASE_IDX … #define regDB_DFSM_FLUSH_AUX_EVENT … #define regDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX … #define regCC_RB_REDUNDANCY … #define regCC_RB_REDUNDANCY_BASE_IDX … #define regCC_RB_BACKEND_DISABLE … #define regCC_RB_BACKEND_DISABLE_BASE_IDX … #define regGB_ADDR_CONFIG … #define regGB_ADDR_CONFIG_BASE_IDX … #define regGB_BACKEND_MAP … #define regGB_BACKEND_MAP_BASE_IDX … #define regGB_GPU_ID … #define regGB_GPU_ID_BASE_IDX … #define regCC_RB_DAISY_CHAIN … #define regCC_RB_DAISY_CHAIN_BASE_IDX … #define regGB_ADDR_CONFIG_READ … #define regGB_ADDR_CONFIG_READ_BASE_IDX … #define regGB_TILE_MODE0 … #define regGB_TILE_MODE0_BASE_IDX … #define regGB_TILE_MODE1 … #define regGB_TILE_MODE1_BASE_IDX … #define regGB_TILE_MODE2 … #define regGB_TILE_MODE2_BASE_IDX … #define regGB_TILE_MODE3 … #define regGB_TILE_MODE3_BASE_IDX … #define regGB_TILE_MODE4 … #define regGB_TILE_MODE4_BASE_IDX … #define regGB_TILE_MODE5 … #define regGB_TILE_MODE5_BASE_IDX … #define regGB_TILE_MODE6 … #define regGB_TILE_MODE6_BASE_IDX … #define regGB_TILE_MODE7 … #define regGB_TILE_MODE7_BASE_IDX … #define regGB_TILE_MODE8 … #define regGB_TILE_MODE8_BASE_IDX … #define regGB_TILE_MODE9 … #define regGB_TILE_MODE9_BASE_IDX … #define regGB_TILE_MODE10 … #define regGB_TILE_MODE10_BASE_IDX … #define regGB_TILE_MODE11 … #define regGB_TILE_MODE11_BASE_IDX … #define regGB_TILE_MODE12 … #define regGB_TILE_MODE12_BASE_IDX … #define regGB_TILE_MODE13 … #define regGB_TILE_MODE13_BASE_IDX … #define regGB_TILE_MODE14 … #define regGB_TILE_MODE14_BASE_IDX … #define regGB_TILE_MODE15 … #define regGB_TILE_MODE15_BASE_IDX … #define regGB_TILE_MODE16 … #define regGB_TILE_MODE16_BASE_IDX … #define regGB_TILE_MODE17 … #define regGB_TILE_MODE17_BASE_IDX … #define regGB_TILE_MODE18 … #define regGB_TILE_MODE18_BASE_IDX … #define regGB_TILE_MODE19 … #define regGB_TILE_MODE19_BASE_IDX … #define regGB_TILE_MODE20 … #define regGB_TILE_MODE20_BASE_IDX … #define regGB_TILE_MODE21 … #define regGB_TILE_MODE21_BASE_IDX … #define regGB_TILE_MODE22 … #define regGB_TILE_MODE22_BASE_IDX … #define regGB_TILE_MODE23 … #define regGB_TILE_MODE23_BASE_IDX … #define regGB_TILE_MODE24 … #define regGB_TILE_MODE24_BASE_IDX … #define regGB_TILE_MODE25 … #define regGB_TILE_MODE25_BASE_IDX … #define regGB_TILE_MODE26 … #define regGB_TILE_MODE26_BASE_IDX … #define regGB_TILE_MODE27 … #define regGB_TILE_MODE27_BASE_IDX … #define regGB_TILE_MODE28 … #define regGB_TILE_MODE28_BASE_IDX … #define regGB_TILE_MODE29 … #define regGB_TILE_MODE29_BASE_IDX … #define regGB_TILE_MODE30 … #define regGB_TILE_MODE30_BASE_IDX … #define regGB_TILE_MODE31 … #define regGB_TILE_MODE31_BASE_IDX … #define regGB_MACROTILE_MODE0 … #define regGB_MACROTILE_MODE0_BASE_IDX … #define regGB_MACROTILE_MODE1 … #define regGB_MACROTILE_MODE1_BASE_IDX … #define regGB_MACROTILE_MODE2 … #define regGB_MACROTILE_MODE2_BASE_IDX … #define regGB_MACROTILE_MODE3 … #define regGB_MACROTILE_MODE3_BASE_IDX … #define regGB_MACROTILE_MODE4 … #define regGB_MACROTILE_MODE4_BASE_IDX … #define regGB_MACROTILE_MODE5 … #define regGB_MACROTILE_MODE5_BASE_IDX … #define regGB_MACROTILE_MODE6 … #define regGB_MACROTILE_MODE6_BASE_IDX … #define regGB_MACROTILE_MODE7 … #define regGB_MACROTILE_MODE7_BASE_IDX … #define regGB_MACROTILE_MODE8 … #define regGB_MACROTILE_MODE8_BASE_IDX … #define regGB_MACROTILE_MODE9 … #define regGB_MACROTILE_MODE9_BASE_IDX … #define regGB_MACROTILE_MODE10 … #define regGB_MACROTILE_MODE10_BASE_IDX … #define regGB_MACROTILE_MODE11 … #define regGB_MACROTILE_MODE11_BASE_IDX … #define regGB_MACROTILE_MODE12 … #define regGB_MACROTILE_MODE12_BASE_IDX … #define regGB_MACROTILE_MODE13 … #define regGB_MACROTILE_MODE13_BASE_IDX … #define regGB_MACROTILE_MODE14 … #define regGB_MACROTILE_MODE14_BASE_IDX … #define regGB_MACROTILE_MODE15 … #define regGB_MACROTILE_MODE15_BASE_IDX … #define regCB_HW_CONTROL … #define regCB_HW_CONTROL_BASE_IDX … #define regCB_HW_CONTROL_1 … #define regCB_HW_CONTROL_1_BASE_IDX … #define regCB_HW_CONTROL_2 … #define regCB_HW_CONTROL_2_BASE_IDX … #define regCB_HW_CONTROL_3 … #define regCB_HW_CONTROL_3_BASE_IDX … #define regCB_HW_MEM_ARBITER_RD … #define regCB_HW_MEM_ARBITER_RD_BASE_IDX … #define regCB_HW_MEM_ARBITER_WR … #define regCB_HW_MEM_ARBITER_WR_BASE_IDX … #define regCB_DCC_CONFIG … #define regCB_DCC_CONFIG_BASE_IDX … #define regGC_USER_RB_REDUNDANCY … #define regGC_USER_RB_REDUNDANCY_BASE_IDX … #define regGC_USER_RB_BACKEND_DISABLE … #define regGC_USER_RB_BACKEND_DISABLE_BASE_IDX … // addressBlock: xcd0_gc_ea_gceadec // base address: 0xa800 #define regGCEA_DRAM_RD_CLI2GRP_MAP0 … #define regGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX … #define regGCEA_DRAM_RD_CLI2GRP_MAP1 … #define regGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX … #define regGCEA_DRAM_WR_CLI2GRP_MAP0 … #define regGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX … #define regGCEA_DRAM_WR_CLI2GRP_MAP1 … #define regGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX … #define regGCEA_DRAM_RD_GRP2VC_MAP … #define regGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX … #define regGCEA_DRAM_WR_GRP2VC_MAP … #define regGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX … #define regGCEA_DRAM_RD_LAZY … #define regGCEA_DRAM_RD_LAZY_BASE_IDX … #define regGCEA_DRAM_WR_LAZY … #define regGCEA_DRAM_WR_LAZY_BASE_IDX … #define regGCEA_DRAM_RD_CAM_CNTL … #define regGCEA_DRAM_RD_CAM_CNTL_BASE_IDX … #define regGCEA_DRAM_WR_CAM_CNTL … #define regGCEA_DRAM_WR_CAM_CNTL_BASE_IDX … #define regGCEA_DRAM_PAGE_BURST … #define regGCEA_DRAM_PAGE_BURST_BASE_IDX … #define regGCEA_DRAM_RD_PRI_AGE … #define regGCEA_DRAM_RD_PRI_AGE_BASE_IDX … #define regGCEA_DRAM_WR_PRI_AGE … #define regGCEA_DRAM_WR_PRI_AGE_BASE_IDX … #define regGCEA_DRAM_RD_PRI_QUEUING … #define regGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX … #define regGCEA_DRAM_WR_PRI_QUEUING … #define regGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX … #define regGCEA_DRAM_RD_PRI_FIXED … #define regGCEA_DRAM_RD_PRI_FIXED_BASE_IDX … #define regGCEA_DRAM_WR_PRI_FIXED … #define regGCEA_DRAM_WR_PRI_FIXED_BASE_IDX … #define regGCEA_DRAM_RD_PRI_URGENCY … #define regGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX … #define regGCEA_DRAM_WR_PRI_URGENCY … #define regGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX … #define regGCEA_DRAM_RD_PRI_QUANT_PRI1 … #define regGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX … #define regGCEA_DRAM_RD_PRI_QUANT_PRI2 … #define regGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX … #define regGCEA_DRAM_RD_PRI_QUANT_PRI3 … #define regGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX … #define regGCEA_DRAM_WR_PRI_QUANT_PRI1 … #define regGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … #define regGCEA_DRAM_WR_PRI_QUANT_PRI2 … #define regGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX … #define regGCEA_DRAM_WR_PRI_QUANT_PRI3 … #define regGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX … #define regGCEA_IO_RD_CLI2GRP_MAP0 … #define regGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX … #define regGCEA_IO_RD_CLI2GRP_MAP1 … #define regGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX … #define regGCEA_IO_WR_CLI2GRP_MAP0 … #define regGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX … #define regGCEA_IO_WR_CLI2GRP_MAP1 … #define regGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX … #define regGCEA_IO_RD_COMBINE_FLUSH … #define regGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX … #define regGCEA_IO_WR_COMBINE_FLUSH … #define regGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX … #define regGCEA_IO_GROUP_BURST … #define regGCEA_IO_GROUP_BURST_BASE_IDX … #define regGCEA_IO_RD_PRI_AGE … #define regGCEA_IO_RD_PRI_AGE_BASE_IDX … #define regGCEA_IO_WR_PRI_AGE … #define regGCEA_IO_WR_PRI_AGE_BASE_IDX … #define regGCEA_IO_RD_PRI_QUEUING … #define regGCEA_IO_RD_PRI_QUEUING_BASE_IDX … #define regGCEA_IO_WR_PRI_QUEUING … #define regGCEA_IO_WR_PRI_QUEUING_BASE_IDX … #define regGCEA_IO_RD_PRI_FIXED … #define regGCEA_IO_RD_PRI_FIXED_BASE_IDX … #define regGCEA_IO_WR_PRI_FIXED … #define regGCEA_IO_WR_PRI_FIXED_BASE_IDX … #define regGCEA_IO_RD_PRI_URGENCY … #define regGCEA_IO_RD_PRI_URGENCY_BASE_IDX … #define regGCEA_IO_WR_PRI_URGENCY … #define regGCEA_IO_WR_PRI_URGENCY_BASE_IDX … #define regGCEA_IO_RD_PRI_URGENCY_MASKING … #define regGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX … #define regGCEA_IO_WR_PRI_URGENCY_MASKING … #define regGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX … #define regGCEA_IO_RD_PRI_QUANT_PRI1 … #define regGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX … #define regGCEA_IO_RD_PRI_QUANT_PRI2 … #define regGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX … #define regGCEA_IO_RD_PRI_QUANT_PRI3 … #define regGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX … #define regGCEA_IO_WR_PRI_QUANT_PRI1 … #define regGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX … #define regGCEA_IO_WR_PRI_QUANT_PRI2 … #define regGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX … #define regGCEA_IO_WR_PRI_QUANT_PRI3 … #define regGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX … #define regGCEA_SDP_ARB_DRAM … #define regGCEA_SDP_ARB_DRAM_BASE_IDX … #define regGCEA_SDP_ARB_FINAL … #define regGCEA_SDP_ARB_FINAL_BASE_IDX … #define regGCEA_SDP_DRAM_PRIORITY … #define regGCEA_SDP_DRAM_PRIORITY_BASE_IDX … #define regGCEA_SDP_IO_PRIORITY … #define regGCEA_SDP_IO_PRIORITY_BASE_IDX … #define regGCEA_SDP_CREDITS … #define regGCEA_SDP_CREDITS_BASE_IDX … #define regGCEA_SDP_TAG_RESERVE0 … #define regGCEA_SDP_TAG_RESERVE0_BASE_IDX … #define regGCEA_SDP_TAG_RESERVE1 … #define regGCEA_SDP_TAG_RESERVE1_BASE_IDX … #define regGCEA_SDP_VCC_RESERVE0 … #define regGCEA_SDP_VCC_RESERVE0_BASE_IDX … #define regGCEA_SDP_VCC_RESERVE1 … #define regGCEA_SDP_VCC_RESERVE1_BASE_IDX … #define regGCEA_SDP_VCD_RESERVE0 … #define regGCEA_SDP_VCD_RESERVE0_BASE_IDX … #define regGCEA_SDP_VCD_RESERVE1 … #define regGCEA_SDP_VCD_RESERVE1_BASE_IDX … #define regGCEA_SDP_REQ_CNTL … #define regGCEA_SDP_REQ_CNTL_BASE_IDX … #define regGCEA_MISC … #define regGCEA_MISC_BASE_IDX … #define regGCEA_LATENCY_SAMPLING … #define regGCEA_LATENCY_SAMPLING_BASE_IDX … #define regGCEA_PERFCOUNTER_LO … #define regGCEA_PERFCOUNTER_LO_BASE_IDX … #define regGCEA_PERFCOUNTER_HI … #define regGCEA_PERFCOUNTER_HI_BASE_IDX … #define regGCEA_PERFCOUNTER0_CFG … #define regGCEA_PERFCOUNTER0_CFG_BASE_IDX … #define regGCEA_PERFCOUNTER1_CFG … #define regGCEA_PERFCOUNTER1_CFG_BASE_IDX … // addressBlock: xcd0_gc_ea_gceadec2 // base address: 0x9c00 #define regGCEA_PERFCOUNTER_RSLT_CNTL … #define regGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define regGCEA_MAM_CTRL … #define regGCEA_MAM_CTRL_BASE_IDX … #define regGCEA_MAM_CTRL2 … #define regGCEA_MAM_CTRL2_BASE_IDX … #define regGCEA_UE_ERR_STATUS_LO … #define regGCEA_UE_ERR_STATUS_LO_BASE_IDX … #define regGCEA_UE_ERR_STATUS_HI … #define regGCEA_UE_ERR_STATUS_HI_BASE_IDX … #define regGCEA_DSM_CNTL … #define regGCEA_DSM_CNTL_BASE_IDX … #define regGCEA_DSM_CNTLA … #define regGCEA_DSM_CNTLA_BASE_IDX … #define regGCEA_DSM_CNTLB … #define regGCEA_DSM_CNTLB_BASE_IDX … #define regGCEA_DSM_CNTL2 … #define regGCEA_DSM_CNTL2_BASE_IDX … #define regGCEA_DSM_CNTL2A … #define regGCEA_DSM_CNTL2A_BASE_IDX … #define regGCEA_DSM_CNTL2B … #define regGCEA_DSM_CNTL2B_BASE_IDX … #define regGCEA_TCC_XBR_CREDITS … #define regGCEA_TCC_XBR_CREDITS_BASE_IDX … #define regGCEA_TCC_XBR_MAXBURST … #define regGCEA_TCC_XBR_MAXBURST_BASE_IDX … #define regGCEA_PROBE_CNTL … #define regGCEA_PROBE_CNTL_BASE_IDX … #define regGCEA_PROBE_MAP … #define regGCEA_PROBE_MAP_BASE_IDX … #define regGCEA_ERR_STATUS … #define regGCEA_ERR_STATUS_BASE_IDX … #define regGCEA_MISC2 … #define regGCEA_MISC2_BASE_IDX … #define regGCEA_SDP_BACKDOOR_CMDCREDITS0 … #define regGCEA_SDP_BACKDOOR_CMDCREDITS0_BASE_IDX … #define regGCEA_SDP_BACKDOOR_CMDCREDITS1 … #define regGCEA_SDP_BACKDOOR_CMDCREDITS1_BASE_IDX … #define regGCEA_SDP_BACKDOOR_DATACREDITS0 … #define regGCEA_SDP_BACKDOOR_DATACREDITS0_BASE_IDX … #define regGCEA_SDP_BACKDOOR_DATACREDITS1 … #define regGCEA_SDP_BACKDOOR_DATACREDITS1_BASE_IDX … #define regGCEA_SDP_BACKDOOR_MISCCREDITS … #define regGCEA_SDP_BACKDOOR_MISCCREDITS_BASE_IDX … #define regGCEA_CE_ERR_STATUS_LO … #define regGCEA_CE_ERR_STATUS_LO_BASE_IDX … #define regGCEA_CE_ERR_STATUS_HI … #define regGCEA_CE_ERR_STATUS_HI_BASE_IDX … #define regGCEA_SDP_ENABLE … #define regGCEA_SDP_ENABLE_BASE_IDX … // addressBlock: xcd0_gc_ea_pwrdec // base address: 0x3c000 #define regGCEA_ICG_CTRL … #define regGCEA_ICG_CTRL_BASE_IDX … // addressBlock: xcd0_gc_rmi_rmidec // base address: 0x9e00 #define regRMI_GENERAL_CNTL … #define regRMI_GENERAL_CNTL_BASE_IDX … #define regRMI_GENERAL_CNTL1 … #define regRMI_GENERAL_CNTL1_BASE_IDX … #define regRMI_GENERAL_STATUS … #define regRMI_GENERAL_STATUS_BASE_IDX … #define regRMI_SUBBLOCK_STATUS0 … #define regRMI_SUBBLOCK_STATUS0_BASE_IDX … #define regRMI_SUBBLOCK_STATUS1 … #define regRMI_SUBBLOCK_STATUS1_BASE_IDX … #define regRMI_SUBBLOCK_STATUS2 … #define regRMI_SUBBLOCK_STATUS2_BASE_IDX … #define regRMI_SUBBLOCK_STATUS3 … #define regRMI_SUBBLOCK_STATUS3_BASE_IDX … #define regRMI_XBAR_CONFIG … #define regRMI_XBAR_CONFIG_BASE_IDX … #define regRMI_PROBE_POP_LOGIC_CNTL … #define regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX … #define regRMI_UTC_XNACK_N_MISC_CNTL … #define regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX … #define regRMI_DEMUX_CNTL … #define regRMI_DEMUX_CNTL_BASE_IDX … #define regRMI_UTCL1_CNTL1 … #define regRMI_UTCL1_CNTL1_BASE_IDX … #define regRMI_UTCL1_CNTL2 … #define regRMI_UTCL1_CNTL2_BASE_IDX … #define regRMI_UTC_UNIT_CONFIG … #define regRMI_UTC_UNIT_CONFIG_BASE_IDX … #define regRMI_TCIW_FORMATTER0_CNTL … #define regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX … #define regRMI_TCIW_FORMATTER1_CNTL … #define regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX … #define regRMI_SCOREBOARD_CNTL … #define regRMI_SCOREBOARD_CNTL_BASE_IDX … #define regRMI_SCOREBOARD_STATUS0 … #define regRMI_SCOREBOARD_STATUS0_BASE_IDX … #define regRMI_SCOREBOARD_STATUS1 … #define regRMI_SCOREBOARD_STATUS1_BASE_IDX … #define regRMI_SCOREBOARD_STATUS2 … #define regRMI_SCOREBOARD_STATUS2_BASE_IDX … #define regRMI_XBAR_ARBITER_CONFIG … #define regRMI_XBAR_ARBITER_CONFIG_BASE_IDX … #define regRMI_XBAR_ARBITER_CONFIG_1 … #define regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX … #define regRMI_CLOCK_CNTRL … #define regRMI_CLOCK_CNTRL_BASE_IDX … #define regRMI_UTCL1_STATUS … #define regRMI_UTCL1_STATUS_BASE_IDX … #define regRMI_XNACK_DEBUG … #define regRMI_XNACK_DEBUG_BASE_IDX … #define regRMI_SPARE … #define regRMI_SPARE_BASE_IDX … #define regRMI_SPARE_1 … #define regRMI_SPARE_1_BASE_IDX … #define regRMI_SPARE_2 … #define regRMI_SPARE_2_BASE_IDX … // addressBlock: xcd0_gc_utcl2_atcl2dec // base address: 0xa000 #define regATC_L2_CNTL … #define regATC_L2_CNTL_BASE_IDX … #define regATC_L2_CNTL2 … #define regATC_L2_CNTL2_BASE_IDX … #define regATC_L2_CACHE_DATA0 … #define regATC_L2_CACHE_DATA0_BASE_IDX … #define regATC_L2_CACHE_DATA1 … #define regATC_L2_CACHE_DATA1_BASE_IDX … #define regATC_L2_CACHE_DATA2 … #define regATC_L2_CACHE_DATA2_BASE_IDX … #define regATC_L2_CACHE_DATA3 … #define regATC_L2_CACHE_DATA3_BASE_IDX … #define regATC_L2_CNTL3 … #define regATC_L2_CNTL3_BASE_IDX … #define regATC_L2_STATUS … #define regATC_L2_STATUS_BASE_IDX … #define regATC_L2_STATUS2 … #define regATC_L2_STATUS2_BASE_IDX … #define regATC_L2_MISC_CG … #define regATC_L2_MISC_CG_BASE_IDX … #define regATC_L2_MEM_POWER_LS … #define regATC_L2_MEM_POWER_LS_BASE_IDX … #define regATC_L2_CGTT_CLK_CTRL … #define regATC_L2_CGTT_CLK_CTRL_BASE_IDX … #define regATC_L2_CACHE_4K_DSM_INDEX … #define regATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX … #define regATC_L2_CACHE_32K_DSM_INDEX … #define regATC_L2_CACHE_32K_DSM_INDEX_BASE_IDX … #define regATC_L2_CACHE_2M_DSM_INDEX … #define regATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX … #define regATC_L2_CACHE_4K_DSM_CNTL … #define regATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX … #define regATC_L2_CACHE_32K_DSM_CNTL … #define regATC_L2_CACHE_32K_DSM_CNTL_BASE_IDX … #define regATC_L2_CACHE_2M_DSM_CNTL … #define regATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX … #define regATC_L2_CNTL4 … #define regATC_L2_CNTL4_BASE_IDX … #define regATC_L2_MM_GROUP_RT_CLASSES … #define regATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX … #define regATC_L2_UE_ERR_STATUS_LO … #define regATC_L2_UE_ERR_STATUS_LO_BASE_IDX … #define regATC_L2_UE_ERR_STATUS_HI … #define regATC_L2_UE_ERR_STATUS_HI_BASE_IDX … #define regATC_L2_CE_ERR_STATUS_LO … #define regATC_L2_CE_ERR_STATUS_LO_BASE_IDX … #define regATC_L2_CE_ERR_STATUS_HI … #define regATC_L2_CE_ERR_STATUS_HI_BASE_IDX … // addressBlock: xcd0_gc_utcl2_vml2pfdec // base address: 0xa080 #define regVM_L2_CNTL … #define regVM_L2_CNTL_BASE_IDX … #define regVM_L2_CNTL2 … #define regVM_L2_CNTL2_BASE_IDX … #define regVM_L2_CNTL3 … #define regVM_L2_CNTL3_BASE_IDX … #define regVM_L2_STATUS … #define regVM_L2_STATUS_BASE_IDX … #define regVM_DUMMY_PAGE_FAULT_CNTL … #define regVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX … #define regVM_DUMMY_PAGE_FAULT_ADDR_LO32 … #define regVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX … #define regVM_DUMMY_PAGE_FAULT_ADDR_HI32 … #define regVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX … #define regVM_L2_PROTECTION_FAULT_CNTL … #define regVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX … #define regVM_L2_PROTECTION_FAULT_CNTL2 … #define regVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX … #define regVM_L2_PROTECTION_FAULT_MM_CNTL3 … #define regVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX … #define regVM_L2_PROTECTION_FAULT_MM_CNTL4 … #define regVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX … #define regVM_L2_PROTECTION_FAULT_STATUS … #define regVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX … #define regVM_L2_PROTECTION_FAULT_ADDR_LO32 … #define regVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX … #define regVM_L2_PROTECTION_FAULT_ADDR_HI32 … #define regVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX … #define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 … #define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX … #define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 … #define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX … #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 … #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX … #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 … #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX … #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 … #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX … #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 … #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX … #define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 … #define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX … #define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 … #define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX … #define regVM_L2_CNTL4 … #define regVM_L2_CNTL4_BASE_IDX … #define regVM_L2_CNTL5 … #define regVM_L2_CNTL5_BASE_IDX … #define regVM_L2_MM_GROUP_RT_CLASSES … #define regVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX … #define regVM_L2_BANK_SELECT_RESERVED_CID … #define regVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX … #define regVM_L2_BANK_SELECT_RESERVED_CID2 … #define regVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX … #define regVM_L2_CACHE_PARITY_CNTL … #define regVM_L2_CACHE_PARITY_CNTL_BASE_IDX … #define regVM_L2_CGTT_CLK_CTRL … #define regVM_L2_CGTT_CLK_CTRL_BASE_IDX … #define regVM_L2_CGTT_BUSY_CTRL … #define regVM_L2_CGTT_BUSY_CTRL_BASE_IDX … #define regVML2_MEM_ECC_INDEX … #define regVML2_MEM_ECC_INDEX_BASE_IDX … #define regVML2_WALKER_MEM_ECC_INDEX … #define regVML2_WALKER_MEM_ECC_INDEX_BASE_IDX … #define regUTCL2_MEM_ECC_INDEX … #define regUTCL2_MEM_ECC_INDEX_BASE_IDX … #define regVML2_MEM_ECC_CNTL … #define regVML2_MEM_ECC_CNTL_BASE_IDX … #define regVML2_WALKER_MEM_ECC_CNTL … #define regVML2_WALKER_MEM_ECC_CNTL_BASE_IDX … #define regUTCL2_MEM_ECC_CNTL … #define regUTCL2_MEM_ECC_CNTL_BASE_IDX … #define regVML2_MEM_ECC_STATUS … #define regVML2_MEM_ECC_STATUS_BASE_IDX … #define regVML2_WALKER_MEM_ECC_STATUS … #define regVML2_WALKER_MEM_ECC_STATUS_BASE_IDX … #define regUTCL2_MEM_ECC_STATUS … #define regUTCL2_MEM_ECC_STATUS_BASE_IDX … #define regUTCL2_EDC_MODE … #define regUTCL2_EDC_MODE_BASE_IDX … #define regUTCL2_EDC_CONFIG … #define regUTCL2_EDC_CONFIG_BASE_IDX … #define regVML2_UE_ERR_STATUS_LO … #define regVML2_UE_ERR_STATUS_LO_BASE_IDX … #define regVML2_WALKER_UE_ERR_STATUS_LO … #define regVML2_WALKER_UE_ERR_STATUS_LO_BASE_IDX … #define regUTCL2_UE_ERR_STATUS_LO … #define regUTCL2_UE_ERR_STATUS_LO_BASE_IDX … #define regVML2_UE_ERR_STATUS_HI … #define regVML2_UE_ERR_STATUS_HI_BASE_IDX … #define regVML2_WALKER_UE_ERR_STATUS_HI … #define regVML2_WALKER_UE_ERR_STATUS_HI_BASE_IDX … #define regUTCL2_UE_ERR_STATUS_HI … #define regUTCL2_UE_ERR_STATUS_HI_BASE_IDX … #define regVML2_CE_ERR_STATUS_LO … #define regVML2_CE_ERR_STATUS_LO_BASE_IDX … #define regVML2_WALKER_CE_ERR_STATUS_LO … #define regVML2_WALKER_CE_ERR_STATUS_LO_BASE_IDX … #define regUTCL2_CE_ERR_STATUS_LO … #define regUTCL2_CE_ERR_STATUS_LO_BASE_IDX … #define regVML2_CE_ERR_STATUS_HI … #define regVML2_CE_ERR_STATUS_HI_BASE_IDX … #define regVML2_WALKER_CE_ERR_STATUS_HI … #define regVML2_WALKER_CE_ERR_STATUS_HI_BASE_IDX … #define regUTCL2_CE_ERR_STATUS_HI … #define regUTCL2_CE_ERR_STATUS_HI_BASE_IDX … // addressBlock: xcd0_gc_utcl2_vml2vcdec // base address: 0xa180 #define regVM_CONTEXT0_CNTL … #define regVM_CONTEXT0_CNTL_BASE_IDX … #define regVM_CONTEXT1_CNTL … #define regVM_CONTEXT1_CNTL_BASE_IDX … #define regVM_CONTEXT2_CNTL … #define regVM_CONTEXT2_CNTL_BASE_IDX … #define regVM_CONTEXT3_CNTL … #define regVM_CONTEXT3_CNTL_BASE_IDX … #define regVM_CONTEXT4_CNTL … #define regVM_CONTEXT4_CNTL_BASE_IDX … #define regVM_CONTEXT5_CNTL … #define regVM_CONTEXT5_CNTL_BASE_IDX … #define regVM_CONTEXT6_CNTL … #define regVM_CONTEXT6_CNTL_BASE_IDX … #define regVM_CONTEXT7_CNTL … #define regVM_CONTEXT7_CNTL_BASE_IDX … #define regVM_CONTEXT8_CNTL … #define regVM_CONTEXT8_CNTL_BASE_IDX … #define regVM_CONTEXT9_CNTL … #define regVM_CONTEXT9_CNTL_BASE_IDX … #define regVM_CONTEXT10_CNTL … #define regVM_CONTEXT10_CNTL_BASE_IDX … #define regVM_CONTEXT11_CNTL … #define regVM_CONTEXT11_CNTL_BASE_IDX … #define regVM_CONTEXT12_CNTL … #define regVM_CONTEXT12_CNTL_BASE_IDX … #define regVM_CONTEXT13_CNTL … #define regVM_CONTEXT13_CNTL_BASE_IDX … #define regVM_CONTEXT14_CNTL … #define regVM_CONTEXT14_CNTL_BASE_IDX … #define regVM_CONTEXT15_CNTL … #define regVM_CONTEXT15_CNTL_BASE_IDX … #define regVM_CONTEXTS_DISABLE … #define regVM_CONTEXTS_DISABLE_BASE_IDX … #define regVM_INVALIDATE_ENG0_SEM … #define regVM_INVALIDATE_ENG0_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG1_SEM … #define regVM_INVALIDATE_ENG1_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG2_SEM … #define regVM_INVALIDATE_ENG2_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG3_SEM … #define regVM_INVALIDATE_ENG3_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG4_SEM … #define regVM_INVALIDATE_ENG4_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG5_SEM … #define regVM_INVALIDATE_ENG5_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG6_SEM … #define regVM_INVALIDATE_ENG6_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG7_SEM … #define regVM_INVALIDATE_ENG7_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG8_SEM … #define regVM_INVALIDATE_ENG8_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG9_SEM … #define regVM_INVALIDATE_ENG9_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG10_SEM … #define regVM_INVALIDATE_ENG10_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG11_SEM … #define regVM_INVALIDATE_ENG11_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG12_SEM … #define regVM_INVALIDATE_ENG12_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG13_SEM … #define regVM_INVALIDATE_ENG13_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG14_SEM … #define regVM_INVALIDATE_ENG14_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG15_SEM … #define regVM_INVALIDATE_ENG15_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG16_SEM … #define regVM_INVALIDATE_ENG16_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG17_SEM … #define regVM_INVALIDATE_ENG17_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG0_REQ … #define regVM_INVALIDATE_ENG0_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG1_REQ … #define regVM_INVALIDATE_ENG1_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG2_REQ … #define regVM_INVALIDATE_ENG2_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG3_REQ … #define regVM_INVALIDATE_ENG3_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG4_REQ … #define regVM_INVALIDATE_ENG4_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG5_REQ … #define regVM_INVALIDATE_ENG5_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG6_REQ … #define regVM_INVALIDATE_ENG6_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG7_REQ … #define regVM_INVALIDATE_ENG7_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG8_REQ … #define regVM_INVALIDATE_ENG8_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG9_REQ … #define regVM_INVALIDATE_ENG9_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG10_REQ … #define regVM_INVALIDATE_ENG10_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG11_REQ … #define regVM_INVALIDATE_ENG11_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG12_REQ … #define regVM_INVALIDATE_ENG12_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG13_REQ … #define regVM_INVALIDATE_ENG13_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG14_REQ … #define regVM_INVALIDATE_ENG14_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG15_REQ … #define regVM_INVALIDATE_ENG15_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG16_REQ … #define regVM_INVALIDATE_ENG16_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG17_REQ … #define regVM_INVALIDATE_ENG17_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG0_ACK … #define regVM_INVALIDATE_ENG0_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG1_ACK … #define regVM_INVALIDATE_ENG1_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG2_ACK … #define regVM_INVALIDATE_ENG2_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG3_ACK … #define regVM_INVALIDATE_ENG3_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG4_ACK … #define regVM_INVALIDATE_ENG4_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG5_ACK … #define regVM_INVALIDATE_ENG5_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG6_ACK … #define regVM_INVALIDATE_ENG6_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG7_ACK … #define regVM_INVALIDATE_ENG7_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG8_ACK … #define regVM_INVALIDATE_ENG8_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG9_ACK … #define regVM_INVALIDATE_ENG9_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG10_ACK … #define regVM_INVALIDATE_ENG10_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG11_ACK … #define regVM_INVALIDATE_ENG11_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG12_ACK … #define regVM_INVALIDATE_ENG12_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG13_ACK … #define regVM_INVALIDATE_ENG13_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG14_ACK … #define regVM_INVALIDATE_ENG14_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG15_ACK … #define regVM_INVALIDATE_ENG15_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG16_ACK … #define regVM_INVALIDATE_ENG16_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG17_ACK … #define regVM_INVALIDATE_ENG17_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX … #define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … // addressBlock: xcd0_gc_utcl2_vmsharedpfdec // base address: 0xa500 #define regMC_VM_NB_MMIOBASE … #define regMC_VM_NB_MMIOBASE_BASE_IDX … #define regMC_VM_NB_MMIOLIMIT … #define regMC_VM_NB_MMIOLIMIT_BASE_IDX … #define regMC_VM_NB_PCI_CTRL … #define regMC_VM_NB_PCI_CTRL_BASE_IDX … #define regMC_VM_NB_PCI_ARB … #define regMC_VM_NB_PCI_ARB_BASE_IDX … #define regMC_VM_NB_TOP_OF_DRAM_SLOT1 … #define regMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX … #define regMC_VM_NB_LOWER_TOP_OF_DRAM2 … #define regMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX … #define regMC_VM_NB_UPPER_TOP_OF_DRAM2 … #define regMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX … #define regMC_VM_FB_OFFSET … #define regMC_VM_FB_OFFSET_BASE_IDX … #define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB … #define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX … #define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB … #define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX … #define regMC_VM_STEERING … #define regMC_VM_STEERING_BASE_IDX … #define regMC_SHARED_VIRT_RESET_REQ … #define regMC_SHARED_VIRT_RESET_REQ_BASE_IDX … #define regMC_MEM_POWER_LS … #define regMC_MEM_POWER_LS_BASE_IDX … #define regMC_VM_CACHEABLE_DRAM_ADDRESS_START … #define regMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX … #define regMC_VM_CACHEABLE_DRAM_ADDRESS_END … #define regMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX … #define regMC_VM_APT_CNTL … #define regMC_VM_APT_CNTL_BASE_IDX … #define regMC_VM_LOCAL_HBM_ADDRESS_START … #define regMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX … #define regMC_VM_LOCAL_HBM_ADDRESS_END … #define regMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX … #define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL … #define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX … #define regUTCL2_CGTT_CLK_CTRL … #define regUTCL2_CGTT_CLK_CTRL_BASE_IDX … #define regMC_VM_XGMI_LFB_CNTL … #define regMC_VM_XGMI_LFB_CNTL_BASE_IDX … #define regMC_VM_XGMI_LFB_SIZE … #define regMC_VM_XGMI_LFB_SIZE_BASE_IDX … #define regMC_VM_CACHEABLE_DRAM_CNTL … #define regMC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX … #define regMC_VM_HOST_MAPPING … #define regMC_VM_HOST_MAPPING_BASE_IDX … // addressBlock: xcd0_gc_utcl2_vmsharedvcdec // base address: 0xa570 #define regMC_VM_FB_LOCATION_BASE … #define regMC_VM_FB_LOCATION_BASE_BASE_IDX … #define regMC_VM_FB_LOCATION_TOP … #define regMC_VM_FB_LOCATION_TOP_BASE_IDX … #define regMC_VM_AGP_TOP … #define regMC_VM_AGP_TOP_BASE_IDX … #define regMC_VM_AGP_BOT … #define regMC_VM_AGP_BOT_BASE_IDX … #define regMC_VM_AGP_BASE … #define regMC_VM_AGP_BASE_BASE_IDX … #define regMC_VM_SYSTEM_APERTURE_LOW_ADDR … #define regMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX … #define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR … #define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX … #define regMC_VM_MX_L1_TLB_CNTL … #define regMC_VM_MX_L1_TLB_CNTL_BASE_IDX … // addressBlock: xcd0_gc_utcl2_l2tlbdec // base address: 0xa5b0 #define regL2TLB_TLB0_STATUS … #define regL2TLB_TLB0_STATUS_BASE_IDX … #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO … #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX … #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI … #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX … #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO … #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX … #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI … #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX … // addressBlock: xcd0_gc_tcdec // base address: 0xac00 #define regTCP_INVALIDATE … #define regTCP_INVALIDATE_BASE_IDX … #define regTCP_STATUS … #define regTCP_STATUS_BASE_IDX … #define regTCP_CNTL … #define regTCP_CNTL_BASE_IDX … #define regTCP_CHAN_STEER_0 … #define regTCP_CHAN_STEER_0_BASE_IDX … #define regTCP_CHAN_STEER_1 … #define regTCP_CHAN_STEER_1_BASE_IDX … #define regTCP_ADDR_CONFIG … #define regTCP_ADDR_CONFIG_BASE_IDX … #define regTCP_CREDIT … #define regTCP_CREDIT_BASE_IDX … #define regTCP_BUFFER_ADDR_HASH_CNTL … #define regTCP_BUFFER_ADDR_HASH_CNTL_BASE_IDX … #define regTC_CFG_L1_LOAD_POLICY0 … #define regTC_CFG_L1_LOAD_POLICY0_BASE_IDX … #define regTC_CFG_L1_LOAD_POLICY1 … #define regTC_CFG_L1_LOAD_POLICY1_BASE_IDX … #define regTC_CFG_L1_STORE_POLICY … #define regTC_CFG_L1_STORE_POLICY_BASE_IDX … #define regTC_CFG_L2_LOAD_POLICY0 … #define regTC_CFG_L2_LOAD_POLICY0_BASE_IDX … #define regTC_CFG_L2_LOAD_POLICY1 … #define regTC_CFG_L2_LOAD_POLICY1_BASE_IDX … #define regTC_CFG_L2_STORE_POLICY0 … #define regTC_CFG_L2_STORE_POLICY0_BASE_IDX … #define regTC_CFG_L2_STORE_POLICY1 … #define regTC_CFG_L2_STORE_POLICY1_BASE_IDX … #define regTC_CFG_L2_ATOMIC_POLICY … #define regTC_CFG_L2_ATOMIC_POLICY_BASE_IDX … #define regTC_CFG_L1_VOLATILE … #define regTC_CFG_L1_VOLATILE_BASE_IDX … #define regTC_CFG_L2_VOLATILE … #define regTC_CFG_L2_VOLATILE_BASE_IDX … #define regTCP_UE_EDC_HI_REG … #define regTCP_UE_EDC_HI_REG_BASE_IDX … #define regTCP_UE_EDC_LO_REG … #define regTCP_UE_EDC_LO_REG_BASE_IDX … #define regTCP_CE_EDC_HI_REG … #define regTCP_CE_EDC_HI_REG_BASE_IDX … #define regTCP_CE_EDC_LO_REG … #define regTCP_CE_EDC_LO_REG_BASE_IDX … #define regTCI_UE_EDC_HI_REG … #define regTCI_UE_EDC_HI_REG_BASE_IDX … #define regTCI_UE_EDC_LO_REG … #define regTCI_UE_EDC_LO_REG_BASE_IDX … #define regTCI_CE_EDC_HI_REG … #define regTCI_CE_EDC_HI_REG_BASE_IDX … #define regTCI_CE_EDC_LO_REG … #define regTCI_CE_EDC_LO_REG_BASE_IDX … #define regTCI_MISC … #define regTCI_MISC_BASE_IDX … #define regTCI_CNTL_3 … #define regTCI_CNTL_3_BASE_IDX … #define regTCI_DSM_CNTL … #define regTCI_DSM_CNTL_BASE_IDX … #define regTCI_DSM_CNTL2 … #define regTCI_DSM_CNTL2_BASE_IDX … #define regTCI_STATUS … #define regTCI_STATUS_BASE_IDX … #define regTCI_CNTL_1 … #define regTCI_CNTL_1_BASE_IDX … #define regTCI_CNTL_2 … #define regTCI_CNTL_2_BASE_IDX … #define regTCC_CTRL … #define regTCC_CTRL_BASE_IDX … #define regTCC_CTRL2 … #define regTCC_CTRL2_BASE_IDX … #define regTCC_DSM_CNTL … #define regTCC_DSM_CNTL_BASE_IDX … #define regTCC_DSM_CNTLA … #define regTCC_DSM_CNTLA_BASE_IDX … #define regTCC_DSM_CNTL2 … #define regTCC_DSM_CNTL2_BASE_IDX … #define regTCC_DSM_CNTL2A … #define regTCC_DSM_CNTL2A_BASE_IDX … #define regTCC_DSM_CNTL2B … #define regTCC_DSM_CNTL2B_BASE_IDX … #define regTCC_WBINVL2 … #define regTCC_WBINVL2_BASE_IDX … #define regTCC_SOFT_RESET … #define regTCC_SOFT_RESET_BASE_IDX … #define regTCC_DSM_CNTL3 … #define regTCC_DSM_CNTL3_BASE_IDX … #define regTCA_CTRL … #define regTCA_CTRL_BASE_IDX … #define regTCA_BURST_MASK … #define regTCA_BURST_MASK_BASE_IDX … #define regTCA_BURST_CTRL … #define regTCA_BURST_CTRL_BASE_IDX … #define regTCA_DSM_CNTL … #define regTCA_DSM_CNTL_BASE_IDX … #define regTCA_DSM_CNTL2 … #define regTCA_DSM_CNTL2_BASE_IDX … #define regTCX_CTRL … #define regTCX_CTRL_BASE_IDX … #define regTCX_DSM_CNTL … #define regTCX_DSM_CNTL_BASE_IDX … #define regTCX_DSM_CNTL2 … #define regTCX_DSM_CNTL2_BASE_IDX … #define regTCA_UE_ERR_STATUS_LO … #define regTCA_UE_ERR_STATUS_LO_BASE_IDX … #define regTCA_UE_ERR_STATUS_HI … #define regTCA_UE_ERR_STATUS_HI_BASE_IDX … #define regTCX_UE_ERR_STATUS_LO … #define regTCX_UE_ERR_STATUS_LO_BASE_IDX … #define regTCX_UE_ERR_STATUS_HI … #define regTCX_UE_ERR_STATUS_HI_BASE_IDX … #define regTCX_CE_ERR_STATUS_LO … #define regTCX_CE_ERR_STATUS_LO_BASE_IDX … #define regTCX_CE_ERR_STATUS_HI … #define regTCX_CE_ERR_STATUS_HI_BASE_IDX … #define regTCC_UE_ERR_STATUS_LO … #define regTCC_UE_ERR_STATUS_LO_BASE_IDX … #define regTCC_UE_ERR_STATUS_HI … #define regTCC_UE_ERR_STATUS_HI_BASE_IDX … #define regTCC_CE_ERR_STATUS_LO … #define regTCC_CE_ERR_STATUS_LO_BASE_IDX … #define regTCC_CE_ERR_STATUS_HI … #define regTCC_CE_ERR_STATUS_HI_BASE_IDX … // addressBlock: xcd0_gc_shdec // base address: 0xb000 #define regSPI_SHADER_PGM_RSRC3_PS … #define regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX … #define regSPI_SHADER_PGM_LO_PS … #define regSPI_SHADER_PGM_LO_PS_BASE_IDX … #define regSPI_SHADER_PGM_HI_PS … #define regSPI_SHADER_PGM_HI_PS_BASE_IDX … #define regSPI_SHADER_PGM_RSRC1_PS … #define regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX … #define regSPI_SHADER_PGM_RSRC2_PS … #define regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_0 … #define regSPI_SHADER_USER_DATA_PS_0_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_1 … #define regSPI_SHADER_USER_DATA_PS_1_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_2 … #define regSPI_SHADER_USER_DATA_PS_2_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_3 … #define regSPI_SHADER_USER_DATA_PS_3_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_4 … #define regSPI_SHADER_USER_DATA_PS_4_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_5 … #define regSPI_SHADER_USER_DATA_PS_5_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_6 … #define regSPI_SHADER_USER_DATA_PS_6_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_7 … #define regSPI_SHADER_USER_DATA_PS_7_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_8 … #define regSPI_SHADER_USER_DATA_PS_8_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_9 … #define regSPI_SHADER_USER_DATA_PS_9_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_10 … #define regSPI_SHADER_USER_DATA_PS_10_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_11 … #define regSPI_SHADER_USER_DATA_PS_11_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_12 … #define regSPI_SHADER_USER_DATA_PS_12_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_13 … #define regSPI_SHADER_USER_DATA_PS_13_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_14 … #define regSPI_SHADER_USER_DATA_PS_14_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_15 … #define regSPI_SHADER_USER_DATA_PS_15_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_16 … #define regSPI_SHADER_USER_DATA_PS_16_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_17 … #define regSPI_SHADER_USER_DATA_PS_17_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_18 … #define regSPI_SHADER_USER_DATA_PS_18_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_19 … #define regSPI_SHADER_USER_DATA_PS_19_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_20 … #define regSPI_SHADER_USER_DATA_PS_20_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_21 … #define regSPI_SHADER_USER_DATA_PS_21_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_22 … #define regSPI_SHADER_USER_DATA_PS_22_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_23 … #define regSPI_SHADER_USER_DATA_PS_23_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_24 … #define regSPI_SHADER_USER_DATA_PS_24_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_25 … #define regSPI_SHADER_USER_DATA_PS_25_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_26 … #define regSPI_SHADER_USER_DATA_PS_26_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_27 … #define regSPI_SHADER_USER_DATA_PS_27_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_28 … #define regSPI_SHADER_USER_DATA_PS_28_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_29 … #define regSPI_SHADER_USER_DATA_PS_29_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_30 … #define regSPI_SHADER_USER_DATA_PS_30_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_31 … #define regSPI_SHADER_USER_DATA_PS_31_BASE_IDX … #define regSPI_SHADER_PGM_RSRC3_VS … #define regSPI_SHADER_PGM_RSRC3_VS_BASE_IDX … #define regSPI_SHADER_LATE_ALLOC_VS … #define regSPI_SHADER_LATE_ALLOC_VS_BASE_IDX … #define regSPI_SHADER_PGM_LO_VS … #define regSPI_SHADER_PGM_LO_VS_BASE_IDX … #define regSPI_SHADER_PGM_HI_VS … #define regSPI_SHADER_PGM_HI_VS_BASE_IDX … #define regSPI_SHADER_PGM_RSRC1_VS … #define regSPI_SHADER_PGM_RSRC1_VS_BASE_IDX … #define regSPI_SHADER_PGM_RSRC2_VS … #define regSPI_SHADER_PGM_RSRC2_VS_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_0 … #define regSPI_SHADER_USER_DATA_VS_0_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_1 … #define regSPI_SHADER_USER_DATA_VS_1_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_2 … #define regSPI_SHADER_USER_DATA_VS_2_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_3 … #define regSPI_SHADER_USER_DATA_VS_3_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_4 … #define regSPI_SHADER_USER_DATA_VS_4_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_5 … #define regSPI_SHADER_USER_DATA_VS_5_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_6 … #define regSPI_SHADER_USER_DATA_VS_6_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_7 … #define regSPI_SHADER_USER_DATA_VS_7_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_8 … #define regSPI_SHADER_USER_DATA_VS_8_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_9 … #define regSPI_SHADER_USER_DATA_VS_9_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_10 … #define regSPI_SHADER_USER_DATA_VS_10_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_11 … #define regSPI_SHADER_USER_DATA_VS_11_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_12 … #define regSPI_SHADER_USER_DATA_VS_12_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_13 … #define regSPI_SHADER_USER_DATA_VS_13_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_14 … #define regSPI_SHADER_USER_DATA_VS_14_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_15 … #define regSPI_SHADER_USER_DATA_VS_15_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_16 … #define regSPI_SHADER_USER_DATA_VS_16_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_17 … #define regSPI_SHADER_USER_DATA_VS_17_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_18 … #define regSPI_SHADER_USER_DATA_VS_18_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_19 … #define regSPI_SHADER_USER_DATA_VS_19_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_20 … #define regSPI_SHADER_USER_DATA_VS_20_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_21 … #define regSPI_SHADER_USER_DATA_VS_21_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_22 … #define regSPI_SHADER_USER_DATA_VS_22_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_23 … #define regSPI_SHADER_USER_DATA_VS_23_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_24 … #define regSPI_SHADER_USER_DATA_VS_24_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_25 … #define regSPI_SHADER_USER_DATA_VS_25_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_26 … #define regSPI_SHADER_USER_DATA_VS_26_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_27 … #define regSPI_SHADER_USER_DATA_VS_27_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_28 … #define regSPI_SHADER_USER_DATA_VS_28_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_29 … #define regSPI_SHADER_USER_DATA_VS_29_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_30 … #define regSPI_SHADER_USER_DATA_VS_30_BASE_IDX … #define regSPI_SHADER_USER_DATA_VS_31 … #define regSPI_SHADER_USER_DATA_VS_31_BASE_IDX … #define regSPI_SHADER_PGM_RSRC2_GS_VS … #define regSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX … #define regSPI_SHADER_PGM_RSRC4_GS … #define regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX … #define regSPI_SHADER_USER_DATA_ADDR_LO_GS … #define regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX … #define regSPI_SHADER_USER_DATA_ADDR_HI_GS … #define regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX … #define regSPI_SHADER_PGM_LO_ES … #define regSPI_SHADER_PGM_LO_ES_BASE_IDX … #define regSPI_SHADER_PGM_HI_ES … #define regSPI_SHADER_PGM_HI_ES_BASE_IDX … #define regSPI_SHADER_PGM_RSRC3_GS … #define regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX … #define regSPI_SHADER_PGM_LO_GS … #define regSPI_SHADER_PGM_LO_GS_BASE_IDX … #define regSPI_SHADER_PGM_HI_GS … #define regSPI_SHADER_PGM_HI_GS_BASE_IDX … #define regSPI_SHADER_PGM_RSRC1_GS … #define regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX … #define regSPI_SHADER_PGM_RSRC2_GS … #define regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_0 … #define regSPI_SHADER_USER_DATA_ES_0_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_1 … #define regSPI_SHADER_USER_DATA_ES_1_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_2 … #define regSPI_SHADER_USER_DATA_ES_2_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_3 … #define regSPI_SHADER_USER_DATA_ES_3_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_4 … #define regSPI_SHADER_USER_DATA_ES_4_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_5 … #define regSPI_SHADER_USER_DATA_ES_5_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_6 … #define regSPI_SHADER_USER_DATA_ES_6_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_7 … #define regSPI_SHADER_USER_DATA_ES_7_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_8 … #define regSPI_SHADER_USER_DATA_ES_8_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_9 … #define regSPI_SHADER_USER_DATA_ES_9_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_10 … #define regSPI_SHADER_USER_DATA_ES_10_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_11 … #define regSPI_SHADER_USER_DATA_ES_11_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_12 … #define regSPI_SHADER_USER_DATA_ES_12_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_13 … #define regSPI_SHADER_USER_DATA_ES_13_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_14 … #define regSPI_SHADER_USER_DATA_ES_14_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_15 … #define regSPI_SHADER_USER_DATA_ES_15_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_16 … #define regSPI_SHADER_USER_DATA_ES_16_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_17 … #define regSPI_SHADER_USER_DATA_ES_17_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_18 … #define regSPI_SHADER_USER_DATA_ES_18_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_19 … #define regSPI_SHADER_USER_DATA_ES_19_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_20 … #define regSPI_SHADER_USER_DATA_ES_20_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_21 … #define regSPI_SHADER_USER_DATA_ES_21_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_22 … #define regSPI_SHADER_USER_DATA_ES_22_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_23 … #define regSPI_SHADER_USER_DATA_ES_23_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_24 … #define regSPI_SHADER_USER_DATA_ES_24_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_25 … #define regSPI_SHADER_USER_DATA_ES_25_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_26 … #define regSPI_SHADER_USER_DATA_ES_26_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_27 … #define regSPI_SHADER_USER_DATA_ES_27_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_28 … #define regSPI_SHADER_USER_DATA_ES_28_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_29 … #define regSPI_SHADER_USER_DATA_ES_29_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_30 … #define regSPI_SHADER_USER_DATA_ES_30_BASE_IDX … #define regSPI_SHADER_USER_DATA_ES_31 … #define regSPI_SHADER_USER_DATA_ES_31_BASE_IDX … #define regSPI_SHADER_PGM_RSRC4_HS … #define regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX … #define regSPI_SHADER_USER_DATA_ADDR_LO_HS … #define regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX … #define regSPI_SHADER_USER_DATA_ADDR_HI_HS … #define regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX … #define regSPI_SHADER_PGM_LO_LS … #define regSPI_SHADER_PGM_LO_LS_BASE_IDX … #define regSPI_SHADER_PGM_HI_LS … #define regSPI_SHADER_PGM_HI_LS_BASE_IDX … #define regSPI_SHADER_PGM_RSRC3_HS … #define regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX … #define regSPI_SHADER_PGM_LO_HS … #define regSPI_SHADER_PGM_LO_HS_BASE_IDX … #define regSPI_SHADER_PGM_HI_HS … #define regSPI_SHADER_PGM_HI_HS_BASE_IDX … #define regSPI_SHADER_PGM_RSRC1_HS … #define regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX … #define regSPI_SHADER_PGM_RSRC2_HS … #define regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_0 … #define regSPI_SHADER_USER_DATA_LS_0_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_1 … #define regSPI_SHADER_USER_DATA_LS_1_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_2 … #define regSPI_SHADER_USER_DATA_LS_2_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_3 … #define regSPI_SHADER_USER_DATA_LS_3_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_4 … #define regSPI_SHADER_USER_DATA_LS_4_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_5 … #define regSPI_SHADER_USER_DATA_LS_5_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_6 … #define regSPI_SHADER_USER_DATA_LS_6_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_7 … #define regSPI_SHADER_USER_DATA_LS_7_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_8 … #define regSPI_SHADER_USER_DATA_LS_8_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_9 … #define regSPI_SHADER_USER_DATA_LS_9_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_10 … #define regSPI_SHADER_USER_DATA_LS_10_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_11 … #define regSPI_SHADER_USER_DATA_LS_11_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_12 … #define regSPI_SHADER_USER_DATA_LS_12_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_13 … #define regSPI_SHADER_USER_DATA_LS_13_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_14 … #define regSPI_SHADER_USER_DATA_LS_14_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_15 … #define regSPI_SHADER_USER_DATA_LS_15_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_16 … #define regSPI_SHADER_USER_DATA_LS_16_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_17 … #define regSPI_SHADER_USER_DATA_LS_17_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_18 … #define regSPI_SHADER_USER_DATA_LS_18_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_19 … #define regSPI_SHADER_USER_DATA_LS_19_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_20 … #define regSPI_SHADER_USER_DATA_LS_20_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_21 … #define regSPI_SHADER_USER_DATA_LS_21_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_22 … #define regSPI_SHADER_USER_DATA_LS_22_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_23 … #define regSPI_SHADER_USER_DATA_LS_23_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_24 … #define regSPI_SHADER_USER_DATA_LS_24_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_25 … #define regSPI_SHADER_USER_DATA_LS_25_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_26 … #define regSPI_SHADER_USER_DATA_LS_26_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_27 … #define regSPI_SHADER_USER_DATA_LS_27_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_28 … #define regSPI_SHADER_USER_DATA_LS_28_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_29 … #define regSPI_SHADER_USER_DATA_LS_29_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_30 … #define regSPI_SHADER_USER_DATA_LS_30_BASE_IDX … #define regSPI_SHADER_USER_DATA_LS_31 … #define regSPI_SHADER_USER_DATA_LS_31_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_0 … #define regSPI_SHADER_USER_DATA_COMMON_0_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_1 … #define regSPI_SHADER_USER_DATA_COMMON_1_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_2 … #define regSPI_SHADER_USER_DATA_COMMON_2_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_3 … #define regSPI_SHADER_USER_DATA_COMMON_3_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_4 … #define regSPI_SHADER_USER_DATA_COMMON_4_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_5 … #define regSPI_SHADER_USER_DATA_COMMON_5_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_6 … #define regSPI_SHADER_USER_DATA_COMMON_6_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_7 … #define regSPI_SHADER_USER_DATA_COMMON_7_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_8 … #define regSPI_SHADER_USER_DATA_COMMON_8_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_9 … #define regSPI_SHADER_USER_DATA_COMMON_9_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_10 … #define regSPI_SHADER_USER_DATA_COMMON_10_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_11 … #define regSPI_SHADER_USER_DATA_COMMON_11_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_12 … #define regSPI_SHADER_USER_DATA_COMMON_12_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_13 … #define regSPI_SHADER_USER_DATA_COMMON_13_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_14 … #define regSPI_SHADER_USER_DATA_COMMON_14_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_15 … #define regSPI_SHADER_USER_DATA_COMMON_15_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_16 … #define regSPI_SHADER_USER_DATA_COMMON_16_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_17 … #define regSPI_SHADER_USER_DATA_COMMON_17_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_18 … #define regSPI_SHADER_USER_DATA_COMMON_18_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_19 … #define regSPI_SHADER_USER_DATA_COMMON_19_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_20 … #define regSPI_SHADER_USER_DATA_COMMON_20_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_21 … #define regSPI_SHADER_USER_DATA_COMMON_21_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_22 … #define regSPI_SHADER_USER_DATA_COMMON_22_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_23 … #define regSPI_SHADER_USER_DATA_COMMON_23_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_24 … #define regSPI_SHADER_USER_DATA_COMMON_24_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_25 … #define regSPI_SHADER_USER_DATA_COMMON_25_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_26 … #define regSPI_SHADER_USER_DATA_COMMON_26_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_27 … #define regSPI_SHADER_USER_DATA_COMMON_27_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_28 … #define regSPI_SHADER_USER_DATA_COMMON_28_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_29 … #define regSPI_SHADER_USER_DATA_COMMON_29_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_30 … #define regSPI_SHADER_USER_DATA_COMMON_30_BASE_IDX … #define regSPI_SHADER_USER_DATA_COMMON_31 … #define regSPI_SHADER_USER_DATA_COMMON_31_BASE_IDX … #define regCOMPUTE_DISPATCH_INITIATOR … #define regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX … #define regCOMPUTE_DIM_X … #define regCOMPUTE_DIM_X_BASE_IDX … #define regCOMPUTE_DIM_Y … #define regCOMPUTE_DIM_Y_BASE_IDX … #define regCOMPUTE_DIM_Z … #define regCOMPUTE_DIM_Z_BASE_IDX … #define regCOMPUTE_START_X … #define regCOMPUTE_START_X_BASE_IDX … #define regCOMPUTE_START_Y … #define regCOMPUTE_START_Y_BASE_IDX … #define regCOMPUTE_START_Z … #define regCOMPUTE_START_Z_BASE_IDX … #define regCOMPUTE_NUM_THREAD_X … #define regCOMPUTE_NUM_THREAD_X_BASE_IDX … #define regCOMPUTE_NUM_THREAD_Y … #define regCOMPUTE_NUM_THREAD_Y_BASE_IDX … #define regCOMPUTE_NUM_THREAD_Z … #define regCOMPUTE_NUM_THREAD_Z_BASE_IDX … #define regCOMPUTE_PIPELINESTAT_ENABLE … #define regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX … #define regCOMPUTE_PERFCOUNT_ENABLE … #define regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX … #define regCOMPUTE_PGM_LO … #define regCOMPUTE_PGM_LO_BASE_IDX … #define regCOMPUTE_PGM_HI … #define regCOMPUTE_PGM_HI_BASE_IDX … #define regCOMPUTE_DISPATCH_PKT_ADDR_LO … #define regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX … #define regCOMPUTE_DISPATCH_PKT_ADDR_HI … #define regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX … #define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO … #define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX … #define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI … #define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX … #define regCOMPUTE_PGM_RSRC1 … #define regCOMPUTE_PGM_RSRC1_BASE_IDX … #define regCOMPUTE_PGM_RSRC2 … #define regCOMPUTE_PGM_RSRC2_BASE_IDX … #define regCOMPUTE_VMID … #define regCOMPUTE_VMID_BASE_IDX … #define regCOMPUTE_RESOURCE_LIMITS … #define regCOMPUTE_RESOURCE_LIMITS_BASE_IDX … #define regCOMPUTE_STATIC_THREAD_MGMT_SE0 … #define regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX … #define regCOMPUTE_STATIC_THREAD_MGMT_SE1 … #define regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX … #define regCOMPUTE_TMPRING_SIZE … #define regCOMPUTE_TMPRING_SIZE_BASE_IDX … #define regCOMPUTE_STATIC_THREAD_MGMT_SE2 … #define regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX … #define regCOMPUTE_STATIC_THREAD_MGMT_SE3 … #define regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX … #define regCOMPUTE_RESTART_X … #define regCOMPUTE_RESTART_X_BASE_IDX … #define regCOMPUTE_RESTART_Y … #define regCOMPUTE_RESTART_Y_BASE_IDX … #define regCOMPUTE_RESTART_Z … #define regCOMPUTE_RESTART_Z_BASE_IDX … #define regCOMPUTE_THREAD_TRACE_ENABLE … #define regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX … #define regCOMPUTE_MISC_RESERVED … #define regCOMPUTE_MISC_RESERVED_BASE_IDX … #define regCOMPUTE_DISPATCH_ID … #define regCOMPUTE_DISPATCH_ID_BASE_IDX … #define regCOMPUTE_THREADGROUP_ID … #define regCOMPUTE_THREADGROUP_ID_BASE_IDX … #define regCOMPUTE_RELAUNCH … #define regCOMPUTE_RELAUNCH_BASE_IDX … #define regCOMPUTE_WAVE_RESTORE_ADDR_LO … #define regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX … #define regCOMPUTE_WAVE_RESTORE_ADDR_HI … #define regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX … #define regCOMPUTE_TG_CHUNK_SIZE … #define regCOMPUTE_TG_CHUNK_SIZE_BASE_IDX … #define regCOMPUTE_SHADER_CHKSUM … #define regCOMPUTE_SHADER_CHKSUM_BASE_IDX … #define regCOMPUTE_PGM_RSRC3 … #define regCOMPUTE_PGM_RSRC3_BASE_IDX … #define regCOMPUTE_USER_DATA_0 … #define regCOMPUTE_USER_DATA_0_BASE_IDX … #define regCOMPUTE_USER_DATA_1 … #define regCOMPUTE_USER_DATA_1_BASE_IDX … #define regCOMPUTE_USER_DATA_2 … #define regCOMPUTE_USER_DATA_2_BASE_IDX … #define regCOMPUTE_USER_DATA_3 … #define regCOMPUTE_USER_DATA_3_BASE_IDX … #define regCOMPUTE_USER_DATA_4 … #define regCOMPUTE_USER_DATA_4_BASE_IDX … #define regCOMPUTE_USER_DATA_5 … #define regCOMPUTE_USER_DATA_5_BASE_IDX … #define regCOMPUTE_USER_DATA_6 … #define regCOMPUTE_USER_DATA_6_BASE_IDX … #define regCOMPUTE_USER_DATA_7 … #define regCOMPUTE_USER_DATA_7_BASE_IDX … #define regCOMPUTE_USER_DATA_8 … #define regCOMPUTE_USER_DATA_8_BASE_IDX … #define regCOMPUTE_USER_DATA_9 … #define regCOMPUTE_USER_DATA_9_BASE_IDX … #define regCOMPUTE_USER_DATA_10 … #define regCOMPUTE_USER_DATA_10_BASE_IDX … #define regCOMPUTE_USER_DATA_11 … #define regCOMPUTE_USER_DATA_11_BASE_IDX … #define regCOMPUTE_USER_DATA_12 … #define regCOMPUTE_USER_DATA_12_BASE_IDX … #define regCOMPUTE_USER_DATA_13 … #define regCOMPUTE_USER_DATA_13_BASE_IDX … #define regCOMPUTE_USER_DATA_14 … #define regCOMPUTE_USER_DATA_14_BASE_IDX … #define regCOMPUTE_USER_DATA_15 … #define regCOMPUTE_USER_DATA_15_BASE_IDX … #define regCOMPUTE_DISPATCH_END … #define regCOMPUTE_DISPATCH_END_BASE_IDX … #define regCOMPUTE_NOWHERE … #define regCOMPUTE_NOWHERE_BASE_IDX … // addressBlock: xcd0_gc_cppdec // base address: 0xc080 #define regCP_DFY_CNTL … #define regCP_DFY_CNTL_BASE_IDX … #define regCP_DFY_STAT … #define regCP_DFY_STAT_BASE_IDX … #define regCP_DFY_ADDR_HI … #define regCP_DFY_ADDR_HI_BASE_IDX … #define regCP_DFY_ADDR_LO … #define regCP_DFY_ADDR_LO_BASE_IDX … #define regCP_DFY_DATA_0 … #define regCP_DFY_DATA_0_BASE_IDX … #define regCP_DFY_DATA_1 … #define regCP_DFY_DATA_1_BASE_IDX … #define regCP_DFY_DATA_2 … #define regCP_DFY_DATA_2_BASE_IDX … #define regCP_DFY_DATA_3 … #define regCP_DFY_DATA_3_BASE_IDX … #define regCP_DFY_DATA_4 … #define regCP_DFY_DATA_4_BASE_IDX … #define regCP_DFY_DATA_5 … #define regCP_DFY_DATA_5_BASE_IDX … #define regCP_DFY_DATA_6 … #define regCP_DFY_DATA_6_BASE_IDX … #define regCP_DFY_DATA_7 … #define regCP_DFY_DATA_7_BASE_IDX … #define regCP_DFY_DATA_8 … #define regCP_DFY_DATA_8_BASE_IDX … #define regCP_DFY_DATA_9 … #define regCP_DFY_DATA_9_BASE_IDX … #define regCP_DFY_DATA_10 … #define regCP_DFY_DATA_10_BASE_IDX … #define regCP_DFY_DATA_11 … #define regCP_DFY_DATA_11_BASE_IDX … #define regCP_DFY_DATA_12 … #define regCP_DFY_DATA_12_BASE_IDX … #define regCP_DFY_DATA_13 … #define regCP_DFY_DATA_13_BASE_IDX … #define regCP_DFY_DATA_14 … #define regCP_DFY_DATA_14_BASE_IDX … #define regCP_DFY_DATA_15 … #define regCP_DFY_DATA_15_BASE_IDX … #define regCP_DFY_CMD … #define regCP_DFY_CMD_BASE_IDX … #define regCP_EOPQ_WAIT_TIME … #define regCP_EOPQ_WAIT_TIME_BASE_IDX … #define regCP_CPC_MGCG_SYNC_CNTL … #define regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX … #define regCPC_INT_INFO … #define regCPC_INT_INFO_BASE_IDX … #define regCP_VIRT_STATUS … #define regCP_VIRT_STATUS_BASE_IDX … #define regCPC_INT_ADDR … #define regCPC_INT_ADDR_BASE_IDX … #define regCPC_INT_PASID … #define regCPC_INT_PASID_BASE_IDX … #define regCP_GFX_ERROR … #define regCP_GFX_ERROR_BASE_IDX … #define regCPG_UTCL1_CNTL … #define regCPG_UTCL1_CNTL_BASE_IDX … #define regCPC_UTCL1_CNTL … #define regCPC_UTCL1_CNTL_BASE_IDX … #define regCPF_UTCL1_CNTL … #define regCPF_UTCL1_CNTL_BASE_IDX … #define regCP_AQL_SMM_STATUS … #define regCP_AQL_SMM_STATUS_BASE_IDX … #define regCP_RB0_BASE … #define regCP_RB0_BASE_BASE_IDX … #define regCP_RB_BASE … #define regCP_RB_BASE_BASE_IDX … #define regCP_RB0_CNTL … #define regCP_RB0_CNTL_BASE_IDX … #define regCP_RB_CNTL … #define regCP_RB_CNTL_BASE_IDX … #define regCP_RB_RPTR_WR … #define regCP_RB_RPTR_WR_BASE_IDX … #define regCP_RB0_RPTR_ADDR … #define regCP_RB0_RPTR_ADDR_BASE_IDX … #define regCP_RB_RPTR_ADDR … #define regCP_RB_RPTR_ADDR_BASE_IDX … #define regCP_RB0_RPTR_ADDR_HI … #define regCP_RB0_RPTR_ADDR_HI_BASE_IDX … #define regCP_RB_RPTR_ADDR_HI … #define regCP_RB_RPTR_ADDR_HI_BASE_IDX … #define regCP_RB0_BUFSZ_MASK … #define regCP_RB0_BUFSZ_MASK_BASE_IDX … #define regCP_RB_BUFSZ_MASK … #define regCP_RB_BUFSZ_MASK_BASE_IDX … #define regCP_RB_WPTR_POLL_ADDR_LO … #define regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define regCP_RB_WPTR_POLL_ADDR_HI … #define regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define regGC_PRIV_MODE … #define regGC_PRIV_MODE_BASE_IDX … #define regCP_INT_CNTL … #define regCP_INT_CNTL_BASE_IDX … #define regCP_INT_STATUS … #define regCP_INT_STATUS_BASE_IDX … #define regCP_DEVICE_ID … #define regCP_DEVICE_ID_BASE_IDX … #define regCP_ME0_PIPE_PRIORITY_CNTS … #define regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX … #define regCP_RING_PRIORITY_CNTS … #define regCP_RING_PRIORITY_CNTS_BASE_IDX … #define regCP_ME0_PIPE0_PRIORITY … #define regCP_ME0_PIPE0_PRIORITY_BASE_IDX … #define regCP_RING0_PRIORITY … #define regCP_RING0_PRIORITY_BASE_IDX … #define regCP_ME0_PIPE1_PRIORITY … #define regCP_ME0_PIPE1_PRIORITY_BASE_IDX … #define regCP_RING1_PRIORITY … #define regCP_RING1_PRIORITY_BASE_IDX … #define regCP_ME0_PIPE2_PRIORITY … #define regCP_ME0_PIPE2_PRIORITY_BASE_IDX … #define regCP_RING2_PRIORITY … #define regCP_RING2_PRIORITY_BASE_IDX … #define regCP_FATAL_ERROR … #define regCP_FATAL_ERROR_BASE_IDX … #define regCP_RB_VMID … #define regCP_RB_VMID_BASE_IDX … #define regCP_ME0_PIPE0_VMID … #define regCP_ME0_PIPE0_VMID_BASE_IDX … #define regCP_ME0_PIPE1_VMID … #define regCP_ME0_PIPE1_VMID_BASE_IDX … #define regCP_RB0_WPTR … #define regCP_RB0_WPTR_BASE_IDX … #define regCP_RB_WPTR … #define regCP_RB_WPTR_BASE_IDX … #define regCP_RB0_WPTR_HI … #define regCP_RB0_WPTR_HI_BASE_IDX … #define regCP_RB_WPTR_HI … #define regCP_RB_WPTR_HI_BASE_IDX … #define regCP_RB1_WPTR … #define regCP_RB1_WPTR_BASE_IDX … #define regCP_RB1_WPTR_HI … #define regCP_RB1_WPTR_HI_BASE_IDX … #define regCP_RB2_WPTR … #define regCP_RB2_WPTR_BASE_IDX … #define regCP_RB_DOORBELL_CONTROL … #define regCP_RB_DOORBELL_CONTROL_BASE_IDX … #define regCP_RB_DOORBELL_RANGE_LOWER … #define regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX … #define regCP_RB_DOORBELL_RANGE_UPPER … #define regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX … #define regCP_MEC_DOORBELL_RANGE_LOWER … #define regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX … #define regCP_MEC_DOORBELL_RANGE_UPPER … #define regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX … #define regCPG_UTCL1_ERROR … #define regCPG_UTCL1_ERROR_BASE_IDX … #define regCPC_UTCL1_ERROR … #define regCPC_UTCL1_ERROR_BASE_IDX … #define regCP_RB1_BASE … #define regCP_RB1_BASE_BASE_IDX … #define regCP_RB1_CNTL … #define regCP_RB1_CNTL_BASE_IDX … #define regCP_RB1_RPTR_ADDR … #define regCP_RB1_RPTR_ADDR_BASE_IDX … #define regCP_RB1_RPTR_ADDR_HI … #define regCP_RB1_RPTR_ADDR_HI_BASE_IDX … #define regCP_RB2_BASE … #define regCP_RB2_BASE_BASE_IDX … #define regCP_RB2_CNTL … #define regCP_RB2_CNTL_BASE_IDX … #define regCP_RB2_RPTR_ADDR … #define regCP_RB2_RPTR_ADDR_BASE_IDX … #define regCP_RB2_RPTR_ADDR_HI … #define regCP_RB2_RPTR_ADDR_HI_BASE_IDX … #define regCP_RB0_ACTIVE … #define regCP_RB0_ACTIVE_BASE_IDX … #define regCP_RB_ACTIVE … #define regCP_RB_ACTIVE_BASE_IDX … #define regCP_INT_CNTL_RING0 … #define regCP_INT_CNTL_RING0_BASE_IDX … #define regCP_INT_CNTL_RING1 … #define regCP_INT_CNTL_RING1_BASE_IDX … #define regCP_INT_CNTL_RING2 … #define regCP_INT_CNTL_RING2_BASE_IDX … #define regCP_INT_STATUS_RING0 … #define regCP_INT_STATUS_RING0_BASE_IDX … #define regCP_INT_STATUS_RING1 … #define regCP_INT_STATUS_RING1_BASE_IDX … #define regCP_INT_STATUS_RING2 … #define regCP_INT_STATUS_RING2_BASE_IDX … #define regCP_ME_F32_INTERRUPT … #define regCP_ME_F32_INTERRUPT_BASE_IDX … #define regCP_PFP_F32_INTERRUPT … #define regCP_PFP_F32_INTERRUPT_BASE_IDX … #define regCP_CE_F32_INTERRUPT … #define regCP_CE_F32_INTERRUPT_BASE_IDX … #define regCP_MEC1_F32_INTERRUPT … #define regCP_MEC1_F32_INTERRUPT_BASE_IDX … #define regCP_MEC2_F32_INTERRUPT … #define regCP_MEC2_F32_INTERRUPT_BASE_IDX … #define regCP_PWR_CNTL … #define regCP_PWR_CNTL_BASE_IDX … #define regCP_MEM_SLP_CNTL … #define regCP_MEM_SLP_CNTL_BASE_IDX … #define regCP_ECC_DMA_FIRST_OCCURRENCE … #define regCP_ECC_DMA_FIRST_OCCURRENCE_BASE_IDX … #define regCP_ECC_FIRSTOCCURRENCE … #define regCP_ECC_FIRSTOCCURRENCE_BASE_IDX … #define regCP_ECC_FIRSTOCCURRENCE_RING0 … #define regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX … #define regCP_ECC_FIRSTOCCURRENCE_RING1 … #define regCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX … #define regCP_ECC_FIRSTOCCURRENCE_RING2 … #define regCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX … #define regGB_EDC_MODE … #define regGB_EDC_MODE_BASE_IDX … #define regCP_DEBUG … #define regCP_DEBUG_BASE_IDX … #define regCP_CPF_DEBUG … #define regCP_CPF_DEBUG_BASE_IDX … #define regCP_CPC_DEBUG … #define regCP_CPC_DEBUG_BASE_IDX … #define regCP_CPC_DEBUG_2 … #define regCP_CPC_DEBUG_2_BASE_IDX … #define regCP_PQ_WPTR_POLL_CNTL … #define regCP_PQ_WPTR_POLL_CNTL_BASE_IDX … #define regCP_PQ_WPTR_POLL_CNTL1 … #define regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX … #define regCP_ME1_PIPE0_INT_CNTL … #define regCP_ME1_PIPE0_INT_CNTL_BASE_IDX … #define regCP_ME1_PIPE1_INT_CNTL … #define regCP_ME1_PIPE1_INT_CNTL_BASE_IDX … #define regCP_ME1_PIPE2_INT_CNTL … #define regCP_ME1_PIPE2_INT_CNTL_BASE_IDX … #define regCP_ME1_PIPE3_INT_CNTL … #define regCP_ME1_PIPE3_INT_CNTL_BASE_IDX … #define regCP_ME2_PIPE0_INT_CNTL … #define regCP_ME2_PIPE0_INT_CNTL_BASE_IDX … #define regCP_ME2_PIPE1_INT_CNTL … #define regCP_ME2_PIPE1_INT_CNTL_BASE_IDX … #define regCP_ME2_PIPE2_INT_CNTL … #define regCP_ME2_PIPE2_INT_CNTL_BASE_IDX … #define regCP_ME2_PIPE3_INT_CNTL … #define regCP_ME2_PIPE3_INT_CNTL_BASE_IDX … #define regCP_ME1_PIPE0_INT_STATUS … #define regCP_ME1_PIPE0_INT_STATUS_BASE_IDX … #define regCP_ME1_PIPE1_INT_STATUS … #define regCP_ME1_PIPE1_INT_STATUS_BASE_IDX … #define regCP_ME1_PIPE2_INT_STATUS … #define regCP_ME1_PIPE2_INT_STATUS_BASE_IDX … #define regCP_ME1_PIPE3_INT_STATUS … #define regCP_ME1_PIPE3_INT_STATUS_BASE_IDX … #define regCP_ME2_PIPE0_INT_STATUS … #define regCP_ME2_PIPE0_INT_STATUS_BASE_IDX … #define regCP_ME2_PIPE1_INT_STATUS … #define regCP_ME2_PIPE1_INT_STATUS_BASE_IDX … #define regCP_ME2_PIPE2_INT_STATUS … #define regCP_ME2_PIPE2_INT_STATUS_BASE_IDX … #define regCP_ME2_PIPE3_INT_STATUS … #define regCP_ME2_PIPE3_INT_STATUS_BASE_IDX … #define regCP_ME1_INT_STAT_DEBUG … #define regCP_ME1_INT_STAT_DEBUG_BASE_IDX … #define regCP_ME2_INT_STAT_DEBUG … #define regCP_ME2_INT_STAT_DEBUG_BASE_IDX … #define regCC_GC_EDC_CONFIG … #define regCC_GC_EDC_CONFIG_BASE_IDX … #define regCP_ME1_PIPE_PRIORITY_CNTS … #define regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX … #define regCP_ME1_PIPE0_PRIORITY … #define regCP_ME1_PIPE0_PRIORITY_BASE_IDX … #define regCP_ME1_PIPE1_PRIORITY … #define regCP_ME1_PIPE1_PRIORITY_BASE_IDX … #define regCP_ME1_PIPE2_PRIORITY … #define regCP_ME1_PIPE2_PRIORITY_BASE_IDX … #define regCP_ME1_PIPE3_PRIORITY … #define regCP_ME1_PIPE3_PRIORITY_BASE_IDX … #define regCP_ME2_PIPE_PRIORITY_CNTS … #define regCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX … #define regCP_ME2_PIPE0_PRIORITY … #define regCP_ME2_PIPE0_PRIORITY_BASE_IDX … #define regCP_ME2_PIPE1_PRIORITY … #define regCP_ME2_PIPE1_PRIORITY_BASE_IDX … #define regCP_ME2_PIPE2_PRIORITY … #define regCP_ME2_PIPE2_PRIORITY_BASE_IDX … #define regCP_ME2_PIPE3_PRIORITY … #define regCP_ME2_PIPE3_PRIORITY_BASE_IDX … #define regCP_CE_PRGRM_CNTR_START … #define regCP_CE_PRGRM_CNTR_START_BASE_IDX … #define regCP_PFP_PRGRM_CNTR_START … #define regCP_PFP_PRGRM_CNTR_START_BASE_IDX … #define regCP_ME_PRGRM_CNTR_START … #define regCP_ME_PRGRM_CNTR_START_BASE_IDX … #define regCP_MEC1_PRGRM_CNTR_START … #define regCP_MEC1_PRGRM_CNTR_START_BASE_IDX … #define regCP_MEC2_PRGRM_CNTR_START … #define regCP_MEC2_PRGRM_CNTR_START_BASE_IDX … #define regCP_CE_INTR_ROUTINE_START … #define regCP_CE_INTR_ROUTINE_START_BASE_IDX … #define regCP_PFP_INTR_ROUTINE_START … #define regCP_PFP_INTR_ROUTINE_START_BASE_IDX … #define regCP_ME_INTR_ROUTINE_START … #define regCP_ME_INTR_ROUTINE_START_BASE_IDX … #define regCP_MEC1_INTR_ROUTINE_START … #define regCP_MEC1_INTR_ROUTINE_START_BASE_IDX … #define regCP_MEC2_INTR_ROUTINE_START … #define regCP_MEC2_INTR_ROUTINE_START_BASE_IDX … #define regCP_CONTEXT_CNTL … #define regCP_CONTEXT_CNTL_BASE_IDX … #define regCP_MAX_CONTEXT … #define regCP_MAX_CONTEXT_BASE_IDX … #define regCP_IQ_WAIT_TIME1 … #define regCP_IQ_WAIT_TIME1_BASE_IDX … #define regCP_IQ_WAIT_TIME2 … #define regCP_IQ_WAIT_TIME2_BASE_IDX … #define regCP_RB0_BASE_HI … #define regCP_RB0_BASE_HI_BASE_IDX … #define regCP_RB1_BASE_HI … #define regCP_RB1_BASE_HI_BASE_IDX … #define regCP_VMID_RESET … #define regCP_VMID_RESET_BASE_IDX … #define regCPC_INT_CNTL … #define regCPC_INT_CNTL_BASE_IDX … #define regCPC_INT_STATUS … #define regCPC_INT_STATUS_BASE_IDX … #define regCP_VMID_PREEMPT … #define regCP_VMID_PREEMPT_BASE_IDX … #define regCPC_INT_CNTX_ID … #define regCPC_INT_CNTX_ID_BASE_IDX … #define regCP_PQ_STATUS … #define regCP_PQ_STATUS_BASE_IDX … #define regCP_CPC_IC_BASE_LO … #define regCP_CPC_IC_BASE_LO_BASE_IDX … #define regCP_CPC_IC_BASE_HI … #define regCP_CPC_IC_BASE_HI_BASE_IDX … #define regCP_CPC_IC_BASE_CNTL … #define regCP_CPC_IC_BASE_CNTL_BASE_IDX … #define regCP_CPC_IC_OP_CNTL … #define regCP_CPC_IC_OP_CNTL_BASE_IDX … #define regCP_MEC1_F32_INT_DIS … #define regCP_MEC1_F32_INT_DIS_BASE_IDX … #define regCP_MEC2_F32_INT_DIS … #define regCP_MEC2_F32_INT_DIS_BASE_IDX … #define regCP_VMID_STATUS … #define regCP_VMID_STATUS_BASE_IDX … #define regCPC_UE_ERR_STATUS_LO … #define regCPC_UE_ERR_STATUS_LO_BASE_IDX … #define regCPC_UE_ERR_STATUS_HI … #define regCPC_UE_ERR_STATUS_HI_BASE_IDX … #define regCPC_CE_ERR_STATUS_LO … #define regCPC_CE_ERR_STATUS_LO_BASE_IDX … #define regCPC_CE_ERR_STATUS_HI … #define regCPC_CE_ERR_STATUS_HI_BASE_IDX … #define regCPF_UE_ERR_STATUS_LO … #define regCPF_UE_ERR_STATUS_LO_BASE_IDX … #define regCPF_UE_ERR_STATUS_HI … #define regCPF_UE_ERR_STATUS_HI_BASE_IDX … #define regCPF_CE_ERR_STATUS_LO … #define regCPF_CE_ERR_STATUS_LO_BASE_IDX … #define regCPF_CE_ERR_STATUS_HI … #define regCPF_CE_ERR_STATUS_HI_BASE_IDX … #define regCPG_UE_ERR_STATUS_LO … #define regCPG_UE_ERR_STATUS_LO_BASE_IDX … #define regCPG_UE_ERR_STATUS_HI … #define regCPG_UE_ERR_STATUS_HI_BASE_IDX … #define regCPG_CE_ERR_STATUS_LO … #define regCPG_CE_ERR_STATUS_LO_BASE_IDX … #define regCPG_CE_ERR_STATUS_HI … #define regCPG_CE_ERR_STATUS_HI_BASE_IDX … // addressBlock: xcd0_gc_cppdec2 // base address: 0xc600 #define regCP_RB_DOORBELL_CONTROL_SCH_0 … #define regCP_RB_DOORBELL_CONTROL_SCH_0_BASE_IDX … #define regCP_RB_DOORBELL_CONTROL_SCH_1 … #define regCP_RB_DOORBELL_CONTROL_SCH_1_BASE_IDX … #define regCP_RB_DOORBELL_CONTROL_SCH_2 … #define regCP_RB_DOORBELL_CONTROL_SCH_2_BASE_IDX … #define regCP_RB_DOORBELL_CONTROL_SCH_3 … #define regCP_RB_DOORBELL_CONTROL_SCH_3_BASE_IDX … #define regCP_RB_DOORBELL_CONTROL_SCH_4 … #define regCP_RB_DOORBELL_CONTROL_SCH_4_BASE_IDX … #define regCP_RB_DOORBELL_CONTROL_SCH_5 … #define regCP_RB_DOORBELL_CONTROL_SCH_5_BASE_IDX … #define regCP_RB_DOORBELL_CONTROL_SCH_6 … #define regCP_RB_DOORBELL_CONTROL_SCH_6_BASE_IDX … #define regCP_RB_DOORBELL_CONTROL_SCH_7 … #define regCP_RB_DOORBELL_CONTROL_SCH_7_BASE_IDX … #define regCP_RB_DOORBELL_CLEAR … #define regCP_RB_DOORBELL_CLEAR_BASE_IDX … #define regCP_CPF_DSM_CNTL … #define regCP_CPF_DSM_CNTL_BASE_IDX … #define regCP_CPG_DSM_CNTL … #define regCP_CPG_DSM_CNTL_BASE_IDX … #define regCP_CPC_DSM_CNTL … #define regCP_CPC_DSM_CNTL_BASE_IDX … #define regCP_CPF_DSM_CNTL2 … #define regCP_CPF_DSM_CNTL2_BASE_IDX … #define regCP_CPG_DSM_CNTL2 … #define regCP_CPG_DSM_CNTL2_BASE_IDX … #define regCP_CPC_DSM_CNTL2 … #define regCP_CPC_DSM_CNTL2_BASE_IDX … #define regCP_CPF_DSM_CNTL2A … #define regCP_CPF_DSM_CNTL2A_BASE_IDX … #define regCP_CPG_DSM_CNTL2A … #define regCP_CPG_DSM_CNTL2A_BASE_IDX … #define regCP_CPC_DSM_CNTL2A … #define regCP_CPC_DSM_CNTL2A_BASE_IDX … #define regCP_EDC_FUE_CNTL … #define regCP_EDC_FUE_CNTL_BASE_IDX … #define regCP_GFX_MQD_CONTROL … #define regCP_GFX_MQD_CONTROL_BASE_IDX … #define regCP_GFX_MQD_BASE_ADDR … #define regCP_GFX_MQD_BASE_ADDR_BASE_IDX … #define regCP_GFX_MQD_BASE_ADDR_HI … #define regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX … #define regCP_RB_STATUS … #define regCP_RB_STATUS_BASE_IDX … #define regCPG_UTCL1_STATUS … #define regCPG_UTCL1_STATUS_BASE_IDX … #define regCPC_UTCL1_STATUS … #define regCPC_UTCL1_STATUS_BASE_IDX … #define regCPF_UTCL1_STATUS … #define regCPF_UTCL1_STATUS_BASE_IDX … #define regCP_SD_CNTL … #define regCP_SD_CNTL_BASE_IDX … #define regCP_SOFT_RESET_CNTL … #define regCP_SOFT_RESET_CNTL_BASE_IDX … #define regCP_CPC_GFX_CNTL … #define regCP_CPC_GFX_CNTL_BASE_IDX … // addressBlock: xcd0_gc_spipdec // base address: 0xc700 #define regSPI_ARB_PRIORITY … #define regSPI_ARB_PRIORITY_BASE_IDX … #define regSPI_ARB_CYCLES_0 … #define regSPI_ARB_CYCLES_0_BASE_IDX … #define regSPI_ARB_CYCLES_1 … #define regSPI_ARB_CYCLES_1_BASE_IDX … #define regSPI_CDBG_SYS_GFX … #define regSPI_CDBG_SYS_GFX_BASE_IDX … #define regSPI_CDBG_SYS_HP3D … #define regSPI_CDBG_SYS_HP3D_BASE_IDX … #define regSPI_CDBG_SYS_CS0 … #define regSPI_CDBG_SYS_CS0_BASE_IDX … #define regSPI_CDBG_SYS_CS1 … #define regSPI_CDBG_SYS_CS1_BASE_IDX … #define regSPI_WCL_PIPE_PERCENT_GFX … #define regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX … #define regSPI_WCL_PIPE_PERCENT_HP3D … #define regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX … #define regSPI_WCL_PIPE_PERCENT_CS0 … #define regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX … #define regSPI_WCL_PIPE_PERCENT_CS1 … #define regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX … #define regSPI_WCL_PIPE_PERCENT_CS2 … #define regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX … #define regSPI_WCL_PIPE_PERCENT_CS3 … #define regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX … #define regSPI_WCL_PIPE_PERCENT_CS4 … #define regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX … #define regSPI_WCL_PIPE_PERCENT_CS5 … #define regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX … #define regSPI_WCL_PIPE_PERCENT_CS6 … #define regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX … #define regSPI_WCL_PIPE_PERCENT_CS7 … #define regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX … #define regSPI_GDBG_WAVE_CNTL … #define regSPI_GDBG_WAVE_CNTL_BASE_IDX … #define regSPI_GDBG_TRAP_CONFIG … #define regSPI_GDBG_TRAP_CONFIG_BASE_IDX … #define regSPI_GDBG_PER_VMID_CNTL … #define regSPI_GDBG_PER_VMID_CNTL_BASE_IDX … #define regSPI_GDBG_WAVE_CNTL3 … #define regSPI_GDBG_WAVE_CNTL3_BASE_IDX … #define regSPI_SCRATCH_ADDR_CHECK … #define regSPI_SCRATCH_ADDR_CHECK_BASE_IDX … #define regSPI_SCRATCH_ADDR_STATUS … #define regSPI_SCRATCH_ADDR_STATUS_BASE_IDX … #define regSPI_RESET_DEBUG … #define regSPI_RESET_DEBUG_BASE_IDX … #define regSPI_COMPUTE_QUEUE_RESET … #define regSPI_COMPUTE_QUEUE_RESET_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_0 … #define regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_1 … #define regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_2 … #define regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_3 … #define regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_4 … #define regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_5 … #define regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_6 … #define regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_7 … #define regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_8 … #define regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_9 … #define regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_0 … #define regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_1 … #define regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_2 … #define regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_3 … #define regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_4 … #define regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_5 … #define regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_6 … #define regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_7 … #define regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_8 … #define regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_9 … #define regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_10 … #define regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_11 … #define regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_10 … #define regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_11 … #define regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_12 … #define regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_13 … #define regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_14 … #define regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_15 … #define regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_12 … #define regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_13 … #define regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_14 … #define regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_15 … #define regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX … #define regSPI_COMPUTE_WF_CTX_SAVE … #define regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX … #define regSPI_ARB_CNTL_0 … #define regSPI_ARB_CNTL_0_BASE_IDX … // addressBlock: xcd0_gc_cpphqddec // base address: 0xc800 #define regCP_HQD_GFX_CONTROL … #define regCP_HQD_GFX_CONTROL_BASE_IDX … #define regCP_HQD_GFX_STATUS … #define regCP_HQD_GFX_STATUS_BASE_IDX … #define regCP_HPD_ROQ_OFFSETS … #define regCP_HPD_ROQ_OFFSETS_BASE_IDX … #define regCP_HPD_STATUS0 … #define regCP_HPD_STATUS0_BASE_IDX … #define regCP_HPD_UTCL1_CNTL … #define regCP_HPD_UTCL1_CNTL_BASE_IDX … #define regCP_HPD_UTCL1_ERROR … #define regCP_HPD_UTCL1_ERROR_BASE_IDX … #define regCP_HPD_UTCL1_ERROR_ADDR … #define regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX … #define regCP_MQD_BASE_ADDR … #define regCP_MQD_BASE_ADDR_BASE_IDX … #define regCP_MQD_BASE_ADDR_HI … #define regCP_MQD_BASE_ADDR_HI_BASE_IDX … #define regCP_HQD_ACTIVE … #define regCP_HQD_ACTIVE_BASE_IDX … #define regCP_HQD_VMID … #define regCP_HQD_VMID_BASE_IDX … #define regCP_HQD_PERSISTENT_STATE … #define regCP_HQD_PERSISTENT_STATE_BASE_IDX … #define regCP_HQD_PIPE_PRIORITY … #define regCP_HQD_PIPE_PRIORITY_BASE_IDX … #define regCP_HQD_QUEUE_PRIORITY … #define regCP_HQD_QUEUE_PRIORITY_BASE_IDX … #define regCP_HQD_QUANTUM … #define regCP_HQD_QUANTUM_BASE_IDX … #define regCP_HQD_PQ_BASE … #define regCP_HQD_PQ_BASE_BASE_IDX … #define regCP_HQD_PQ_BASE_HI … #define regCP_HQD_PQ_BASE_HI_BASE_IDX … #define regCP_HQD_PQ_RPTR … #define regCP_HQD_PQ_RPTR_BASE_IDX … #define regCP_HQD_PQ_RPTR_REPORT_ADDR … #define regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX … #define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI … #define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX … #define regCP_HQD_PQ_WPTR_POLL_ADDR … #define regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX … #define regCP_HQD_PQ_WPTR_POLL_ADDR_HI … #define regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX … #define regCP_HQD_PQ_DOORBELL_CONTROL … #define regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX … #define regCP_HQD_PQ_CONTROL … #define regCP_HQD_PQ_CONTROL_BASE_IDX … #define regCP_HQD_IB_BASE_ADDR … #define regCP_HQD_IB_BASE_ADDR_BASE_IDX … #define regCP_HQD_IB_BASE_ADDR_HI … #define regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX … #define regCP_HQD_IB_RPTR … #define regCP_HQD_IB_RPTR_BASE_IDX … #define regCP_HQD_IB_CONTROL … #define regCP_HQD_IB_CONTROL_BASE_IDX … #define regCP_HQD_IQ_TIMER … #define regCP_HQD_IQ_TIMER_BASE_IDX … #define regCP_HQD_IQ_RPTR … #define regCP_HQD_IQ_RPTR_BASE_IDX … #define regCP_HQD_DEQUEUE_REQUEST … #define regCP_HQD_DEQUEUE_REQUEST_BASE_IDX … #define regCP_HQD_DMA_OFFLOAD … #define regCP_HQD_DMA_OFFLOAD_BASE_IDX … #define regCP_HQD_OFFLOAD … #define regCP_HQD_OFFLOAD_BASE_IDX … #define regCP_HQD_SEMA_CMD … #define regCP_HQD_SEMA_CMD_BASE_IDX … #define regCP_HQD_MSG_TYPE … #define regCP_HQD_MSG_TYPE_BASE_IDX … #define regCP_HQD_ATOMIC0_PREOP_LO … #define regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX … #define regCP_HQD_ATOMIC0_PREOP_HI … #define regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX … #define regCP_HQD_ATOMIC1_PREOP_LO … #define regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX … #define regCP_HQD_ATOMIC1_PREOP_HI … #define regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX … #define regCP_HQD_HQ_SCHEDULER0 … #define regCP_HQD_HQ_SCHEDULER0_BASE_IDX … #define regCP_HQD_HQ_STATUS0 … #define regCP_HQD_HQ_STATUS0_BASE_IDX … #define regCP_HQD_HQ_CONTROL0 … #define regCP_HQD_HQ_CONTROL0_BASE_IDX … #define regCP_HQD_HQ_SCHEDULER1 … #define regCP_HQD_HQ_SCHEDULER1_BASE_IDX … #define regCP_MQD_CONTROL … #define regCP_MQD_CONTROL_BASE_IDX … #define regCP_HQD_HQ_STATUS1 … #define regCP_HQD_HQ_STATUS1_BASE_IDX … #define regCP_HQD_HQ_CONTROL1 … #define regCP_HQD_HQ_CONTROL1_BASE_IDX … #define regCP_HQD_EOP_BASE_ADDR … #define regCP_HQD_EOP_BASE_ADDR_BASE_IDX … #define regCP_HQD_EOP_BASE_ADDR_HI … #define regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX … #define regCP_HQD_EOP_CONTROL … #define regCP_HQD_EOP_CONTROL_BASE_IDX … #define regCP_HQD_EOP_RPTR … #define regCP_HQD_EOP_RPTR_BASE_IDX … #define regCP_HQD_EOP_WPTR … #define regCP_HQD_EOP_WPTR_BASE_IDX … #define regCP_HQD_EOP_EVENTS … #define regCP_HQD_EOP_EVENTS_BASE_IDX … #define regCP_HQD_CTX_SAVE_BASE_ADDR_LO … #define regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX … #define regCP_HQD_CTX_SAVE_BASE_ADDR_HI … #define regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX … #define regCP_HQD_CTX_SAVE_CONTROL … #define regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX … #define regCP_HQD_CNTL_STACK_OFFSET … #define regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX … #define regCP_HQD_CNTL_STACK_SIZE … #define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX … #define regCP_HQD_WG_STATE_OFFSET … #define regCP_HQD_WG_STATE_OFFSET_BASE_IDX … #define regCP_HQD_CTX_SAVE_SIZE … #define regCP_HQD_CTX_SAVE_SIZE_BASE_IDX … #define regCP_HQD_GDS_RESOURCE_STATE … #define regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX … #define regCP_HQD_ERROR … #define regCP_HQD_ERROR_BASE_IDX … #define regCP_HQD_EOP_WPTR_MEM … #define regCP_HQD_EOP_WPTR_MEM_BASE_IDX … #define regCP_HQD_AQL_CONTROL … #define regCP_HQD_AQL_CONTROL_BASE_IDX … #define regCP_HQD_PQ_WPTR_LO … #define regCP_HQD_PQ_WPTR_LO_BASE_IDX … #define regCP_HQD_PQ_WPTR_HI … #define regCP_HQD_PQ_WPTR_HI_BASE_IDX … #define regCP_HQD_AQL_CONTROL_1 … #define regCP_HQD_AQL_CONTROL_1_BASE_IDX … #define regCP_HQD_AQL_DISPATCH_ID … #define regCP_HQD_AQL_DISPATCH_ID_BASE_IDX … #define regCP_HQD_AQL_DISPATCH_ID_HI … #define regCP_HQD_AQL_DISPATCH_ID_HI_BASE_IDX … // addressBlock: xcd0_gc_tcpdec // base address: 0xca80 #define regTCP_WATCH0_ADDR_H … #define regTCP_WATCH0_ADDR_H_BASE_IDX … #define regTCP_WATCH0_ADDR_L … #define regTCP_WATCH0_ADDR_L_BASE_IDX … #define regTCP_WATCH0_CNTL … #define regTCP_WATCH0_CNTL_BASE_IDX … #define regTCP_WATCH1_ADDR_H … #define regTCP_WATCH1_ADDR_H_BASE_IDX … #define regTCP_WATCH1_ADDR_L … #define regTCP_WATCH1_ADDR_L_BASE_IDX … #define regTCP_WATCH1_CNTL … #define regTCP_WATCH1_CNTL_BASE_IDX … #define regTCP_WATCH2_ADDR_H … #define regTCP_WATCH2_ADDR_H_BASE_IDX … #define regTCP_WATCH2_ADDR_L … #define regTCP_WATCH2_ADDR_L_BASE_IDX … #define regTCP_WATCH2_CNTL … #define regTCP_WATCH2_CNTL_BASE_IDX … #define regTCP_WATCH3_ADDR_H … #define regTCP_WATCH3_ADDR_H_BASE_IDX … #define regTCP_WATCH3_ADDR_L … #define regTCP_WATCH3_ADDR_L_BASE_IDX … #define regTCP_WATCH3_CNTL … #define regTCP_WATCH3_CNTL_BASE_IDX … #define regTCP_GATCL1_CNTL … #define regTCP_GATCL1_CNTL_BASE_IDX … #define regTCP_ATC_EDC_GATCL1_CNT … #define regTCP_ATC_EDC_GATCL1_CNT_BASE_IDX … #define regTCP_GATCL1_DSM_CNTL … #define regTCP_GATCL1_DSM_CNTL_BASE_IDX … #define regTCP_DSM_CNTL … #define regTCP_DSM_CNTL_BASE_IDX … #define regTCP_CNTL2 … #define regTCP_CNTL2_BASE_IDX … #define regTCP_UTCL1_CNTL1 … #define regTCP_UTCL1_CNTL1_BASE_IDX … #define regTCP_UTCL1_CNTL2 … #define regTCP_UTCL1_CNTL2_BASE_IDX … #define regTCP_UTCL1_STATUS … #define regTCP_UTCL1_STATUS_BASE_IDX … #define regTCP_DSM_CNTL2 … #define regTCP_DSM_CNTL2_BASE_IDX … #define regTCP_PERFCOUNTER_FILTER … #define regTCP_PERFCOUNTER_FILTER_BASE_IDX … #define regTCP_PERFCOUNTER_FILTER_EN … #define regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX … // addressBlock: xcd0_gc_gdspdec // base address: 0xcc00 #define regGDS_VMID0_BASE … #define regGDS_VMID0_BASE_BASE_IDX … #define regGDS_VMID0_SIZE … #define regGDS_VMID0_SIZE_BASE_IDX … #define regGDS_VMID1_BASE … #define regGDS_VMID1_BASE_BASE_IDX … #define regGDS_VMID1_SIZE … #define regGDS_VMID1_SIZE_BASE_IDX … #define regGDS_VMID2_BASE … #define regGDS_VMID2_BASE_BASE_IDX … #define regGDS_VMID2_SIZE … #define regGDS_VMID2_SIZE_BASE_IDX … #define regGDS_VMID3_BASE … #define regGDS_VMID3_BASE_BASE_IDX … #define regGDS_VMID3_SIZE … #define regGDS_VMID3_SIZE_BASE_IDX … #define regGDS_VMID4_BASE … #define regGDS_VMID4_BASE_BASE_IDX … #define regGDS_VMID4_SIZE … #define regGDS_VMID4_SIZE_BASE_IDX … #define regGDS_VMID5_BASE … #define regGDS_VMID5_BASE_BASE_IDX … #define regGDS_VMID5_SIZE … #define regGDS_VMID5_SIZE_BASE_IDX … #define regGDS_VMID6_BASE … #define regGDS_VMID6_BASE_BASE_IDX … #define regGDS_VMID6_SIZE … #define regGDS_VMID6_SIZE_BASE_IDX … #define regGDS_VMID7_BASE … #define regGDS_VMID7_BASE_BASE_IDX … #define regGDS_VMID7_SIZE … #define regGDS_VMID7_SIZE_BASE_IDX … #define regGDS_VMID8_BASE … #define regGDS_VMID8_BASE_BASE_IDX … #define regGDS_VMID8_SIZE … #define regGDS_VMID8_SIZE_BASE_IDX … #define regGDS_VMID9_BASE … #define regGDS_VMID9_BASE_BASE_IDX … #define regGDS_VMID9_SIZE … #define regGDS_VMID9_SIZE_BASE_IDX … #define regGDS_VMID10_BASE … #define regGDS_VMID10_BASE_BASE_IDX … #define regGDS_VMID10_SIZE … #define regGDS_VMID10_SIZE_BASE_IDX … #define regGDS_VMID11_BASE … #define regGDS_VMID11_BASE_BASE_IDX … #define regGDS_VMID11_SIZE … #define regGDS_VMID11_SIZE_BASE_IDX … #define regGDS_VMID12_BASE … #define regGDS_VMID12_BASE_BASE_IDX … #define regGDS_VMID12_SIZE … #define regGDS_VMID12_SIZE_BASE_IDX … #define regGDS_VMID13_BASE … #define regGDS_VMID13_BASE_BASE_IDX … #define regGDS_VMID13_SIZE … #define regGDS_VMID13_SIZE_BASE_IDX … #define regGDS_VMID14_BASE … #define regGDS_VMID14_BASE_BASE_IDX … #define regGDS_VMID14_SIZE … #define regGDS_VMID14_SIZE_BASE_IDX … #define regGDS_VMID15_BASE … #define regGDS_VMID15_BASE_BASE_IDX … #define regGDS_VMID15_SIZE … #define regGDS_VMID15_SIZE_BASE_IDX … #define regGDS_GWS_VMID0 … #define regGDS_GWS_VMID0_BASE_IDX … #define regGDS_GWS_VMID1 … #define regGDS_GWS_VMID1_BASE_IDX … #define regGDS_GWS_VMID2 … #define regGDS_GWS_VMID2_BASE_IDX … #define regGDS_GWS_VMID3 … #define regGDS_GWS_VMID3_BASE_IDX … #define regGDS_GWS_VMID4 … #define regGDS_GWS_VMID4_BASE_IDX … #define regGDS_GWS_VMID5 … #define regGDS_GWS_VMID5_BASE_IDX … #define regGDS_GWS_VMID6 … #define regGDS_GWS_VMID6_BASE_IDX … #define regGDS_GWS_VMID7 … #define regGDS_GWS_VMID7_BASE_IDX … #define regGDS_GWS_VMID8 … #define regGDS_GWS_VMID8_BASE_IDX … #define regGDS_GWS_VMID9 … #define regGDS_GWS_VMID9_BASE_IDX … #define regGDS_GWS_VMID10 … #define regGDS_GWS_VMID10_BASE_IDX … #define regGDS_GWS_VMID11 … #define regGDS_GWS_VMID11_BASE_IDX … #define regGDS_GWS_VMID12 … #define regGDS_GWS_VMID12_BASE_IDX … #define regGDS_GWS_VMID13 … #define regGDS_GWS_VMID13_BASE_IDX … #define regGDS_GWS_VMID14 … #define regGDS_GWS_VMID14_BASE_IDX … #define regGDS_GWS_VMID15 … #define regGDS_GWS_VMID15_BASE_IDX … #define regGDS_OA_VMID0 … #define regGDS_OA_VMID0_BASE_IDX … #define regGDS_OA_VMID1 … #define regGDS_OA_VMID1_BASE_IDX … #define regGDS_OA_VMID2 … #define regGDS_OA_VMID2_BASE_IDX … #define regGDS_OA_VMID3 … #define regGDS_OA_VMID3_BASE_IDX … #define regGDS_OA_VMID4 … #define regGDS_OA_VMID4_BASE_IDX … #define regGDS_OA_VMID5 … #define regGDS_OA_VMID5_BASE_IDX … #define regGDS_OA_VMID6 … #define regGDS_OA_VMID6_BASE_IDX … #define regGDS_OA_VMID7 … #define regGDS_OA_VMID7_BASE_IDX … #define regGDS_OA_VMID8 … #define regGDS_OA_VMID8_BASE_IDX … #define regGDS_OA_VMID9 … #define regGDS_OA_VMID9_BASE_IDX … #define regGDS_OA_VMID10 … #define regGDS_OA_VMID10_BASE_IDX … #define regGDS_OA_VMID11 … #define regGDS_OA_VMID11_BASE_IDX … #define regGDS_OA_VMID12 … #define regGDS_OA_VMID12_BASE_IDX … #define regGDS_OA_VMID13 … #define regGDS_OA_VMID13_BASE_IDX … #define regGDS_OA_VMID14 … #define regGDS_OA_VMID14_BASE_IDX … #define regGDS_OA_VMID15 … #define regGDS_OA_VMID15_BASE_IDX … #define regGDS_GWS_RESET0 … #define regGDS_GWS_RESET0_BASE_IDX … #define regGDS_GWS_RESET1 … #define regGDS_GWS_RESET1_BASE_IDX … #define regGDS_GWS_RESOURCE_RESET … #define regGDS_GWS_RESOURCE_RESET_BASE_IDX … #define regGDS_COMPUTE_MAX_WAVE_ID … #define regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX … #define regGDS_OA_RESET_MASK … #define regGDS_OA_RESET_MASK_BASE_IDX … #define regGDS_OA_RESET … #define regGDS_OA_RESET_BASE_IDX … #define regGDS_ENHANCE … #define regGDS_ENHANCE_BASE_IDX … #define regGDS_OA_CGPG_RESTORE … #define regGDS_OA_CGPG_RESTORE_BASE_IDX … #define regGDS_CS_CTXSW_STATUS … #define regGDS_CS_CTXSW_STATUS_BASE_IDX … #define regGDS_CS_CTXSW_CNT0 … #define regGDS_CS_CTXSW_CNT0_BASE_IDX … #define regGDS_CS_CTXSW_CNT1 … #define regGDS_CS_CTXSW_CNT1_BASE_IDX … #define regGDS_CS_CTXSW_CNT2 … #define regGDS_CS_CTXSW_CNT2_BASE_IDX … #define regGDS_CS_CTXSW_CNT3 … #define regGDS_CS_CTXSW_CNT3_BASE_IDX … #define regGDS_GFX_CTXSW_STATUS … #define regGDS_GFX_CTXSW_STATUS_BASE_IDX … #define regGDS_VS_CTXSW_CNT0 … #define regGDS_VS_CTXSW_CNT0_BASE_IDX … #define regGDS_VS_CTXSW_CNT1 … #define regGDS_VS_CTXSW_CNT1_BASE_IDX … #define regGDS_VS_CTXSW_CNT2 … #define regGDS_VS_CTXSW_CNT2_BASE_IDX … #define regGDS_VS_CTXSW_CNT3 … #define regGDS_VS_CTXSW_CNT3_BASE_IDX … #define regGDS_PS0_CTXSW_CNT0 … #define regGDS_PS0_CTXSW_CNT0_BASE_IDX … #define regGDS_PS0_CTXSW_CNT1 … #define regGDS_PS0_CTXSW_CNT1_BASE_IDX … #define regGDS_PS0_CTXSW_CNT2 … #define regGDS_PS0_CTXSW_CNT2_BASE_IDX … #define regGDS_PS0_CTXSW_CNT3 … #define regGDS_PS0_CTXSW_CNT3_BASE_IDX … #define regGDS_PS1_CTXSW_CNT0 … #define regGDS_PS1_CTXSW_CNT0_BASE_IDX … #define regGDS_PS1_CTXSW_CNT1 … #define regGDS_PS1_CTXSW_CNT1_BASE_IDX … #define regGDS_PS1_CTXSW_CNT2 … #define regGDS_PS1_CTXSW_CNT2_BASE_IDX … #define regGDS_PS1_CTXSW_CNT3 … #define regGDS_PS1_CTXSW_CNT3_BASE_IDX … #define regGDS_PS2_CTXSW_CNT0 … #define regGDS_PS2_CTXSW_CNT0_BASE_IDX … #define regGDS_PS2_CTXSW_CNT1 … #define regGDS_PS2_CTXSW_CNT1_BASE_IDX … #define regGDS_PS2_CTXSW_CNT2 … #define regGDS_PS2_CTXSW_CNT2_BASE_IDX … #define regGDS_PS2_CTXSW_CNT3 … #define regGDS_PS2_CTXSW_CNT3_BASE_IDX … #define regGDS_PS3_CTXSW_CNT0 … #define regGDS_PS3_CTXSW_CNT0_BASE_IDX … #define regGDS_PS3_CTXSW_CNT1 … #define regGDS_PS3_CTXSW_CNT1_BASE_IDX … #define regGDS_PS3_CTXSW_CNT2 … #define regGDS_PS3_CTXSW_CNT2_BASE_IDX … #define regGDS_PS3_CTXSW_CNT3 … #define regGDS_PS3_CTXSW_CNT3_BASE_IDX … #define regGDS_PS4_CTXSW_CNT0 … #define regGDS_PS4_CTXSW_CNT0_BASE_IDX … #define regGDS_PS4_CTXSW_CNT1 … #define regGDS_PS4_CTXSW_CNT1_BASE_IDX … #define regGDS_PS4_CTXSW_CNT2 … #define regGDS_PS4_CTXSW_CNT2_BASE_IDX … #define regGDS_PS4_CTXSW_CNT3 … #define regGDS_PS4_CTXSW_CNT3_BASE_IDX … #define regGDS_PS5_CTXSW_CNT0 … #define regGDS_PS5_CTXSW_CNT0_BASE_IDX … #define regGDS_PS5_CTXSW_CNT1 … #define regGDS_PS5_CTXSW_CNT1_BASE_IDX … #define regGDS_PS5_CTXSW_CNT2 … #define regGDS_PS5_CTXSW_CNT2_BASE_IDX … #define regGDS_PS5_CTXSW_CNT3 … #define regGDS_PS5_CTXSW_CNT3_BASE_IDX … #define regGDS_PS6_CTXSW_CNT0 … #define regGDS_PS6_CTXSW_CNT0_BASE_IDX … #define regGDS_PS6_CTXSW_CNT1 … #define regGDS_PS6_CTXSW_CNT1_BASE_IDX … #define regGDS_PS6_CTXSW_CNT2 … #define regGDS_PS6_CTXSW_CNT2_BASE_IDX … #define regGDS_PS6_CTXSW_CNT3 … #define regGDS_PS6_CTXSW_CNT3_BASE_IDX … #define regGDS_PS7_CTXSW_CNT0 … #define regGDS_PS7_CTXSW_CNT0_BASE_IDX … #define regGDS_PS7_CTXSW_CNT1 … #define regGDS_PS7_CTXSW_CNT1_BASE_IDX … #define regGDS_PS7_CTXSW_CNT2 … #define regGDS_PS7_CTXSW_CNT2_BASE_IDX … #define regGDS_PS7_CTXSW_CNT3 … #define regGDS_PS7_CTXSW_CNT3_BASE_IDX … #define regGDS_GS_CTXSW_CNT0 … #define regGDS_GS_CTXSW_CNT0_BASE_IDX … #define regGDS_GS_CTXSW_CNT1 … #define regGDS_GS_CTXSW_CNT1_BASE_IDX … #define regGDS_GS_CTXSW_CNT2 … #define regGDS_GS_CTXSW_CNT2_BASE_IDX … #define regGDS_GS_CTXSW_CNT3 … #define regGDS_GS_CTXSW_CNT3_BASE_IDX … // addressBlock: xcd0_gc_rasdec // base address: 0xce00 #define regRAS_SIGNATURE_CONTROL … #define regRAS_SIGNATURE_CONTROL_BASE_IDX … #define regRAS_SIGNATURE_MASK … #define regRAS_SIGNATURE_MASK_BASE_IDX … #define regRAS_SX_SIGNATURE0 … #define regRAS_SX_SIGNATURE0_BASE_IDX … #define regRAS_SX_SIGNATURE1 … #define regRAS_SX_SIGNATURE1_BASE_IDX … #define regRAS_SX_SIGNATURE2 … #define regRAS_SX_SIGNATURE2_BASE_IDX … #define regRAS_SX_SIGNATURE3 … #define regRAS_SX_SIGNATURE3_BASE_IDX … #define regRAS_DB_SIGNATURE0 … #define regRAS_DB_SIGNATURE0_BASE_IDX … #define regRAS_PA_SIGNATURE0 … #define regRAS_PA_SIGNATURE0_BASE_IDX … #define regRAS_VGT_SIGNATURE0 … #define regRAS_VGT_SIGNATURE0_BASE_IDX … #define regRAS_SQ_SIGNATURE0 … #define regRAS_SQ_SIGNATURE0_BASE_IDX … #define regRAS_SC_SIGNATURE0 … #define regRAS_SC_SIGNATURE0_BASE_IDX … #define regRAS_SC_SIGNATURE1 … #define regRAS_SC_SIGNATURE1_BASE_IDX … #define regRAS_SC_SIGNATURE2 … #define regRAS_SC_SIGNATURE2_BASE_IDX … #define regRAS_SC_SIGNATURE3 … #define regRAS_SC_SIGNATURE3_BASE_IDX … #define regRAS_SC_SIGNATURE4 … #define regRAS_SC_SIGNATURE4_BASE_IDX … #define regRAS_SC_SIGNATURE5 … #define regRAS_SC_SIGNATURE5_BASE_IDX … #define regRAS_SC_SIGNATURE6 … #define regRAS_SC_SIGNATURE6_BASE_IDX … #define regRAS_SC_SIGNATURE7 … #define regRAS_SC_SIGNATURE7_BASE_IDX … #define regRAS_IA_SIGNATURE0 … #define regRAS_IA_SIGNATURE0_BASE_IDX … #define regRAS_IA_SIGNATURE1 … #define regRAS_IA_SIGNATURE1_BASE_IDX … #define regRAS_SPI_SIGNATURE0 … #define regRAS_SPI_SIGNATURE0_BASE_IDX … #define regRAS_SPI_SIGNATURE1 … #define regRAS_SPI_SIGNATURE1_BASE_IDX … #define regRAS_TA_SIGNATURE0 … #define regRAS_TA_SIGNATURE0_BASE_IDX … #define regRAS_TD_SIGNATURE0 … #define regRAS_TD_SIGNATURE0_BASE_IDX … #define regRAS_CB_SIGNATURE0 … #define regRAS_CB_SIGNATURE0_BASE_IDX … #define regRAS_BCI_SIGNATURE0 … #define regRAS_BCI_SIGNATURE0_BASE_IDX … #define regRAS_BCI_SIGNATURE1 … #define regRAS_BCI_SIGNATURE1_BASE_IDX … #define regRAS_TA_SIGNATURE1 … #define regRAS_TA_SIGNATURE1_BASE_IDX … // addressBlock: xcd0_gc_gfxdec0 // base address: 0x28000 #define regDB_RENDER_CONTROL … #define regDB_RENDER_CONTROL_BASE_IDX … #define regDB_COUNT_CONTROL … #define regDB_COUNT_CONTROL_BASE_IDX … #define regDB_DEPTH_VIEW … #define regDB_DEPTH_VIEW_BASE_IDX … #define regDB_RENDER_OVERRIDE … #define regDB_RENDER_OVERRIDE_BASE_IDX … #define regDB_RENDER_OVERRIDE2 … #define regDB_RENDER_OVERRIDE2_BASE_IDX … #define regDB_HTILE_DATA_BASE … #define regDB_HTILE_DATA_BASE_BASE_IDX … #define regDB_HTILE_DATA_BASE_HI … #define regDB_HTILE_DATA_BASE_HI_BASE_IDX … #define regDB_DEPTH_SIZE … #define regDB_DEPTH_SIZE_BASE_IDX … #define regDB_DEPTH_BOUNDS_MIN … #define regDB_DEPTH_BOUNDS_MIN_BASE_IDX … #define regDB_DEPTH_BOUNDS_MAX … #define regDB_DEPTH_BOUNDS_MAX_BASE_IDX … #define regDB_STENCIL_CLEAR … #define regDB_STENCIL_CLEAR_BASE_IDX … #define regDB_DEPTH_CLEAR … #define regDB_DEPTH_CLEAR_BASE_IDX … #define regPA_SC_SCREEN_SCISSOR_TL … #define regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX … #define regPA_SC_SCREEN_SCISSOR_BR … #define regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX … #define regDB_Z_INFO … #define regDB_Z_INFO_BASE_IDX … #define regDB_STENCIL_INFO … #define regDB_STENCIL_INFO_BASE_IDX … #define regDB_Z_READ_BASE … #define regDB_Z_READ_BASE_BASE_IDX … #define regDB_Z_READ_BASE_HI … #define regDB_Z_READ_BASE_HI_BASE_IDX … #define regDB_STENCIL_READ_BASE … #define regDB_STENCIL_READ_BASE_BASE_IDX … #define regDB_STENCIL_READ_BASE_HI … #define regDB_STENCIL_READ_BASE_HI_BASE_IDX … #define regDB_Z_WRITE_BASE … #define regDB_Z_WRITE_BASE_BASE_IDX … #define regDB_Z_WRITE_BASE_HI … #define regDB_Z_WRITE_BASE_HI_BASE_IDX … #define regDB_STENCIL_WRITE_BASE … #define regDB_STENCIL_WRITE_BASE_BASE_IDX … #define regDB_STENCIL_WRITE_BASE_HI … #define regDB_STENCIL_WRITE_BASE_HI_BASE_IDX … #define regDB_DFSM_CONTROL … #define regDB_DFSM_CONTROL_BASE_IDX … #define regDB_Z_INFO2 … #define regDB_Z_INFO2_BASE_IDX … #define regDB_STENCIL_INFO2 … #define regDB_STENCIL_INFO2_BASE_IDX … #define regCOHER_DEST_BASE_HI_0 … #define regCOHER_DEST_BASE_HI_0_BASE_IDX … #define regCOHER_DEST_BASE_HI_1 … #define regCOHER_DEST_BASE_HI_1_BASE_IDX … #define regCOHER_DEST_BASE_HI_2 … #define regCOHER_DEST_BASE_HI_2_BASE_IDX … #define regCOHER_DEST_BASE_HI_3 … #define regCOHER_DEST_BASE_HI_3_BASE_IDX … #define regCOHER_DEST_BASE_2 … #define regCOHER_DEST_BASE_2_BASE_IDX … #define regCOHER_DEST_BASE_3 … #define regCOHER_DEST_BASE_3_BASE_IDX … #define regPA_SC_WINDOW_OFFSET … #define regPA_SC_WINDOW_OFFSET_BASE_IDX … #define regPA_SC_WINDOW_SCISSOR_TL … #define regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX … #define regPA_SC_WINDOW_SCISSOR_BR … #define regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX … #define regPA_SC_CLIPRECT_RULE … #define regPA_SC_CLIPRECT_RULE_BASE_IDX … #define regPA_SC_CLIPRECT_0_TL … #define regPA_SC_CLIPRECT_0_TL_BASE_IDX … #define regPA_SC_CLIPRECT_0_BR … #define regPA_SC_CLIPRECT_0_BR_BASE_IDX … #define regPA_SC_CLIPRECT_1_TL … #define regPA_SC_CLIPRECT_1_TL_BASE_IDX … #define regPA_SC_CLIPRECT_1_BR … #define regPA_SC_CLIPRECT_1_BR_BASE_IDX … #define regPA_SC_CLIPRECT_2_TL … #define regPA_SC_CLIPRECT_2_TL_BASE_IDX … #define regPA_SC_CLIPRECT_2_BR … #define regPA_SC_CLIPRECT_2_BR_BASE_IDX … #define regPA_SC_CLIPRECT_3_TL … #define regPA_SC_CLIPRECT_3_TL_BASE_IDX … #define regPA_SC_CLIPRECT_3_BR … #define regPA_SC_CLIPRECT_3_BR_BASE_IDX … #define regPA_SC_EDGERULE … #define regPA_SC_EDGERULE_BASE_IDX … #define regPA_SU_HARDWARE_SCREEN_OFFSET … #define regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX … #define regCB_TARGET_MASK … #define regCB_TARGET_MASK_BASE_IDX … #define regCB_SHADER_MASK … #define regCB_SHADER_MASK_BASE_IDX … #define regPA_SC_GENERIC_SCISSOR_TL … #define regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX … #define regPA_SC_GENERIC_SCISSOR_BR … #define regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX … #define regCOHER_DEST_BASE_0 … #define regCOHER_DEST_BASE_0_BASE_IDX … #define regCOHER_DEST_BASE_1 … #define regCOHER_DEST_BASE_1_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_0_TL … #define regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_0_BR … #define regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_1_TL … #define regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_1_BR … #define regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_2_TL … #define regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_2_BR … #define regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_3_TL … #define regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_3_BR … #define regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_4_TL … #define regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_4_BR … #define regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_5_TL … #define regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_5_BR … #define regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_6_TL … #define regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_6_BR … #define regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_7_TL … #define regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_7_BR … #define regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_8_TL … #define regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_8_BR … #define regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_9_TL … #define regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_9_BR … #define regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_10_TL … #define regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_10_BR … #define regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_11_TL … #define regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_11_BR … #define regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_12_TL … #define regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_12_BR … #define regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_13_TL … #define regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_13_BR … #define regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_14_TL … #define regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_14_BR … #define regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_15_TL … #define regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_15_BR … #define regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX … #define regPA_SC_VPORT_ZMIN_0 … #define regPA_SC_VPORT_ZMIN_0_BASE_IDX … #define regPA_SC_VPORT_ZMAX_0 … #define regPA_SC_VPORT_ZMAX_0_BASE_IDX … #define regPA_SC_VPORT_ZMIN_1 … #define regPA_SC_VPORT_ZMIN_1_BASE_IDX … #define regPA_SC_VPORT_ZMAX_1 … #define regPA_SC_VPORT_ZMAX_1_BASE_IDX … #define regPA_SC_VPORT_ZMIN_2 … #define regPA_SC_VPORT_ZMIN_2_BASE_IDX … #define regPA_SC_VPORT_ZMAX_2 … #define regPA_SC_VPORT_ZMAX_2_BASE_IDX … #define regPA_SC_VPORT_ZMIN_3 … #define regPA_SC_VPORT_ZMIN_3_BASE_IDX … #define regPA_SC_VPORT_ZMAX_3 … #define regPA_SC_VPORT_ZMAX_3_BASE_IDX … #define regPA_SC_VPORT_ZMIN_4 … #define regPA_SC_VPORT_ZMIN_4_BASE_IDX … #define regPA_SC_VPORT_ZMAX_4 … #define regPA_SC_VPORT_ZMAX_4_BASE_IDX … #define regPA_SC_VPORT_ZMIN_5 … #define regPA_SC_VPORT_ZMIN_5_BASE_IDX … #define regPA_SC_VPORT_ZMAX_5 … #define regPA_SC_VPORT_ZMAX_5_BASE_IDX … #define regPA_SC_VPORT_ZMIN_6 … #define regPA_SC_VPORT_ZMIN_6_BASE_IDX … #define regPA_SC_VPORT_ZMAX_6 … #define regPA_SC_VPORT_ZMAX_6_BASE_IDX … #define regPA_SC_VPORT_ZMIN_7 … #define regPA_SC_VPORT_ZMIN_7_BASE_IDX … #define regPA_SC_VPORT_ZMAX_7 … #define regPA_SC_VPORT_ZMAX_7_BASE_IDX … #define regPA_SC_VPORT_ZMIN_8 … #define regPA_SC_VPORT_ZMIN_8_BASE_IDX … #define regPA_SC_VPORT_ZMAX_8 … #define regPA_SC_VPORT_ZMAX_8_BASE_IDX … #define regPA_SC_VPORT_ZMIN_9 … #define regPA_SC_VPORT_ZMIN_9_BASE_IDX … #define regPA_SC_VPORT_ZMAX_9 … #define regPA_SC_VPORT_ZMAX_9_BASE_IDX … #define regPA_SC_VPORT_ZMIN_10 … #define regPA_SC_VPORT_ZMIN_10_BASE_IDX … #define regPA_SC_VPORT_ZMAX_10 … #define regPA_SC_VPORT_ZMAX_10_BASE_IDX … #define regPA_SC_VPORT_ZMIN_11 … #define regPA_SC_VPORT_ZMIN_11_BASE_IDX … #define regPA_SC_VPORT_ZMAX_11 … #define regPA_SC_VPORT_ZMAX_11_BASE_IDX … #define regPA_SC_VPORT_ZMIN_12 … #define regPA_SC_VPORT_ZMIN_12_BASE_IDX … #define regPA_SC_VPORT_ZMAX_12 … #define regPA_SC_VPORT_ZMAX_12_BASE_IDX … #define regPA_SC_VPORT_ZMIN_13 … #define regPA_SC_VPORT_ZMIN_13_BASE_IDX … #define regPA_SC_VPORT_ZMAX_13 … #define regPA_SC_VPORT_ZMAX_13_BASE_IDX … #define regPA_SC_VPORT_ZMIN_14 … #define regPA_SC_VPORT_ZMIN_14_BASE_IDX … #define regPA_SC_VPORT_ZMAX_14 … #define regPA_SC_VPORT_ZMAX_14_BASE_IDX … #define regPA_SC_VPORT_ZMIN_15 … #define regPA_SC_VPORT_ZMIN_15_BASE_IDX … #define regPA_SC_VPORT_ZMAX_15 … #define regPA_SC_VPORT_ZMAX_15_BASE_IDX … #define regPA_SC_RASTER_CONFIG … #define regPA_SC_RASTER_CONFIG_BASE_IDX … #define regPA_SC_RASTER_CONFIG_1 … #define regPA_SC_RASTER_CONFIG_1_BASE_IDX … #define regPA_SC_SCREEN_EXTENT_CONTROL … #define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX … #define regPA_SC_TILE_STEERING_OVERRIDE … #define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX … #define regCP_PERFMON_CNTX_CNTL … #define regCP_PERFMON_CNTX_CNTL_BASE_IDX … #define regCP_PIPEID … #define regCP_PIPEID_BASE_IDX … #define regCP_RINGID … #define regCP_RINGID_BASE_IDX … #define regCP_VMID … #define regCP_VMID_BASE_IDX … #define regPA_SC_RIGHT_VERT_GRID … #define regPA_SC_RIGHT_VERT_GRID_BASE_IDX … #define regPA_SC_LEFT_VERT_GRID … #define regPA_SC_LEFT_VERT_GRID_BASE_IDX … #define regPA_SC_HORIZ_GRID … #define regPA_SC_HORIZ_GRID_BASE_IDX … #define regVGT_MULTI_PRIM_IB_RESET_INDX … #define regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX … #define regCB_BLEND_RED … #define regCB_BLEND_RED_BASE_IDX … #define regCB_BLEND_GREEN … #define regCB_BLEND_GREEN_BASE_IDX … #define regCB_BLEND_BLUE … #define regCB_BLEND_BLUE_BASE_IDX … #define regCB_BLEND_ALPHA … #define regCB_BLEND_ALPHA_BASE_IDX … #define regCB_DCC_CONTROL … #define regCB_DCC_CONTROL_BASE_IDX … #define regDB_STENCIL_CONTROL … #define regDB_STENCIL_CONTROL_BASE_IDX … #define regDB_STENCILREFMASK … #define regDB_STENCILREFMASK_BASE_IDX … #define regDB_STENCILREFMASK_BF … #define regDB_STENCILREFMASK_BF_BASE_IDX … #define regPA_CL_VPORT_XSCALE … #define regPA_CL_VPORT_XSCALE_BASE_IDX … #define regPA_CL_VPORT_XOFFSET … #define regPA_CL_VPORT_XOFFSET_BASE_IDX … #define regPA_CL_VPORT_YSCALE … #define regPA_CL_VPORT_YSCALE_BASE_IDX … #define regPA_CL_VPORT_YOFFSET … #define regPA_CL_VPORT_YOFFSET_BASE_IDX … #define regPA_CL_VPORT_ZSCALE … #define regPA_CL_VPORT_ZSCALE_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET … #define regPA_CL_VPORT_ZOFFSET_BASE_IDX … #define regPA_CL_VPORT_XSCALE_1 … #define regPA_CL_VPORT_XSCALE_1_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_1 … #define regPA_CL_VPORT_XOFFSET_1_BASE_IDX … #define regPA_CL_VPORT_YSCALE_1 … #define regPA_CL_VPORT_YSCALE_1_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_1 … #define regPA_CL_VPORT_YOFFSET_1_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_1 … #define regPA_CL_VPORT_ZSCALE_1_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_1 … #define regPA_CL_VPORT_ZOFFSET_1_BASE_IDX … #define regPA_CL_VPORT_XSCALE_2 … #define regPA_CL_VPORT_XSCALE_2_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_2 … #define regPA_CL_VPORT_XOFFSET_2_BASE_IDX … #define regPA_CL_VPORT_YSCALE_2 … #define regPA_CL_VPORT_YSCALE_2_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_2 … #define regPA_CL_VPORT_YOFFSET_2_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_2 … #define regPA_CL_VPORT_ZSCALE_2_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_2 … #define regPA_CL_VPORT_ZOFFSET_2_BASE_IDX … #define regPA_CL_VPORT_XSCALE_3 … #define regPA_CL_VPORT_XSCALE_3_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_3 … #define regPA_CL_VPORT_XOFFSET_3_BASE_IDX … #define regPA_CL_VPORT_YSCALE_3 … #define regPA_CL_VPORT_YSCALE_3_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_3 … #define regPA_CL_VPORT_YOFFSET_3_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_3 … #define regPA_CL_VPORT_ZSCALE_3_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_3 … #define regPA_CL_VPORT_ZOFFSET_3_BASE_IDX … #define regPA_CL_VPORT_XSCALE_4 … #define regPA_CL_VPORT_XSCALE_4_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_4 … #define regPA_CL_VPORT_XOFFSET_4_BASE_IDX … #define regPA_CL_VPORT_YSCALE_4 … #define regPA_CL_VPORT_YSCALE_4_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_4 … #define regPA_CL_VPORT_YOFFSET_4_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_4 … #define regPA_CL_VPORT_ZSCALE_4_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_4 … #define regPA_CL_VPORT_ZOFFSET_4_BASE_IDX … #define regPA_CL_VPORT_XSCALE_5 … #define regPA_CL_VPORT_XSCALE_5_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_5 … #define regPA_CL_VPORT_XOFFSET_5_BASE_IDX … #define regPA_CL_VPORT_YSCALE_5 … #define regPA_CL_VPORT_YSCALE_5_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_5 … #define regPA_CL_VPORT_YOFFSET_5_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_5 … #define regPA_CL_VPORT_ZSCALE_5_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_5 … #define regPA_CL_VPORT_ZOFFSET_5_BASE_IDX … #define regPA_CL_VPORT_XSCALE_6 … #define regPA_CL_VPORT_XSCALE_6_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_6 … #define regPA_CL_VPORT_XOFFSET_6_BASE_IDX … #define regPA_CL_VPORT_YSCALE_6 … #define regPA_CL_VPORT_YSCALE_6_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_6 … #define regPA_CL_VPORT_YOFFSET_6_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_6 … #define regPA_CL_VPORT_ZSCALE_6_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_6 … #define regPA_CL_VPORT_ZOFFSET_6_BASE_IDX … #define regPA_CL_VPORT_XSCALE_7 … #define regPA_CL_VPORT_XSCALE_7_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_7 … #define regPA_CL_VPORT_XOFFSET_7_BASE_IDX … #define regPA_CL_VPORT_YSCALE_7 … #define regPA_CL_VPORT_YSCALE_7_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_7 … #define regPA_CL_VPORT_YOFFSET_7_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_7 … #define regPA_CL_VPORT_ZSCALE_7_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_7 … #define regPA_CL_VPORT_ZOFFSET_7_BASE_IDX … #define regPA_CL_VPORT_XSCALE_8 … #define regPA_CL_VPORT_XSCALE_8_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_8 … #define regPA_CL_VPORT_XOFFSET_8_BASE_IDX … #define regPA_CL_VPORT_YSCALE_8 … #define regPA_CL_VPORT_YSCALE_8_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_8 … #define regPA_CL_VPORT_YOFFSET_8_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_8 … #define regPA_CL_VPORT_ZSCALE_8_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_8 … #define regPA_CL_VPORT_ZOFFSET_8_BASE_IDX … #define regPA_CL_VPORT_XSCALE_9 … #define regPA_CL_VPORT_XSCALE_9_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_9 … #define regPA_CL_VPORT_XOFFSET_9_BASE_IDX … #define regPA_CL_VPORT_YSCALE_9 … #define regPA_CL_VPORT_YSCALE_9_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_9 … #define regPA_CL_VPORT_YOFFSET_9_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_9 … #define regPA_CL_VPORT_ZSCALE_9_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_9 … #define regPA_CL_VPORT_ZOFFSET_9_BASE_IDX … #define regPA_CL_VPORT_XSCALE_10 … #define regPA_CL_VPORT_XSCALE_10_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_10 … #define regPA_CL_VPORT_XOFFSET_10_BASE_IDX … #define regPA_CL_VPORT_YSCALE_10 … #define regPA_CL_VPORT_YSCALE_10_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_10 … #define regPA_CL_VPORT_YOFFSET_10_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_10 … #define regPA_CL_VPORT_ZSCALE_10_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_10 … #define regPA_CL_VPORT_ZOFFSET_10_BASE_IDX … #define regPA_CL_VPORT_XSCALE_11 … #define regPA_CL_VPORT_XSCALE_11_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_11 … #define regPA_CL_VPORT_XOFFSET_11_BASE_IDX … #define regPA_CL_VPORT_YSCALE_11 … #define regPA_CL_VPORT_YSCALE_11_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_11 … #define regPA_CL_VPORT_YOFFSET_11_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_11 … #define regPA_CL_VPORT_ZSCALE_11_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_11 … #define regPA_CL_VPORT_ZOFFSET_11_BASE_IDX … #define regPA_CL_VPORT_XSCALE_12 … #define regPA_CL_VPORT_XSCALE_12_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_12 … #define regPA_CL_VPORT_XOFFSET_12_BASE_IDX … #define regPA_CL_VPORT_YSCALE_12 … #define regPA_CL_VPORT_YSCALE_12_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_12 … #define regPA_CL_VPORT_YOFFSET_12_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_12 … #define regPA_CL_VPORT_ZSCALE_12_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_12 … #define regPA_CL_VPORT_ZOFFSET_12_BASE_IDX … #define regPA_CL_VPORT_XSCALE_13 … #define regPA_CL_VPORT_XSCALE_13_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_13 … #define regPA_CL_VPORT_XOFFSET_13_BASE_IDX … #define regPA_CL_VPORT_YSCALE_13 … #define regPA_CL_VPORT_YSCALE_13_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_13 … #define regPA_CL_VPORT_YOFFSET_13_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_13 … #define regPA_CL_VPORT_ZSCALE_13_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_13 … #define regPA_CL_VPORT_ZOFFSET_13_BASE_IDX … #define regPA_CL_VPORT_XSCALE_14 … #define regPA_CL_VPORT_XSCALE_14_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_14 … #define regPA_CL_VPORT_XOFFSET_14_BASE_IDX … #define regPA_CL_VPORT_YSCALE_14 … #define regPA_CL_VPORT_YSCALE_14_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_14 … #define regPA_CL_VPORT_YOFFSET_14_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_14 … #define regPA_CL_VPORT_ZSCALE_14_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_14 … #define regPA_CL_VPORT_ZOFFSET_14_BASE_IDX … #define regPA_CL_VPORT_XSCALE_15 … #define regPA_CL_VPORT_XSCALE_15_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_15 … #define regPA_CL_VPORT_XOFFSET_15_BASE_IDX … #define regPA_CL_VPORT_YSCALE_15 … #define regPA_CL_VPORT_YSCALE_15_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_15 … #define regPA_CL_VPORT_YOFFSET_15_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_15 … #define regPA_CL_VPORT_ZSCALE_15_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_15 … #define regPA_CL_VPORT_ZOFFSET_15_BASE_IDX … #define regPA_CL_UCP_0_X … #define regPA_CL_UCP_0_X_BASE_IDX … #define regPA_CL_UCP_0_Y … #define regPA_CL_UCP_0_Y_BASE_IDX … #define regPA_CL_UCP_0_Z … #define regPA_CL_UCP_0_Z_BASE_IDX … #define regPA_CL_UCP_0_W … #define regPA_CL_UCP_0_W_BASE_IDX … #define regPA_CL_UCP_1_X … #define regPA_CL_UCP_1_X_BASE_IDX … #define regPA_CL_UCP_1_Y … #define regPA_CL_UCP_1_Y_BASE_IDX … #define regPA_CL_UCP_1_Z … #define regPA_CL_UCP_1_Z_BASE_IDX … #define regPA_CL_UCP_1_W … #define regPA_CL_UCP_1_W_BASE_IDX … #define regPA_CL_UCP_2_X … #define regPA_CL_UCP_2_X_BASE_IDX … #define regPA_CL_UCP_2_Y … #define regPA_CL_UCP_2_Y_BASE_IDX … #define regPA_CL_UCP_2_Z … #define regPA_CL_UCP_2_Z_BASE_IDX … #define regPA_CL_UCP_2_W … #define regPA_CL_UCP_2_W_BASE_IDX … #define regPA_CL_UCP_3_X … #define regPA_CL_UCP_3_X_BASE_IDX … #define regPA_CL_UCP_3_Y … #define regPA_CL_UCP_3_Y_BASE_IDX … #define regPA_CL_UCP_3_Z … #define regPA_CL_UCP_3_Z_BASE_IDX … #define regPA_CL_UCP_3_W … #define regPA_CL_UCP_3_W_BASE_IDX … #define regPA_CL_UCP_4_X … #define regPA_CL_UCP_4_X_BASE_IDX … #define regPA_CL_UCP_4_Y … #define regPA_CL_UCP_4_Y_BASE_IDX … #define regPA_CL_UCP_4_Z … #define regPA_CL_UCP_4_Z_BASE_IDX … #define regPA_CL_UCP_4_W … #define regPA_CL_UCP_4_W_BASE_IDX … #define regPA_CL_UCP_5_X … #define regPA_CL_UCP_5_X_BASE_IDX … #define regPA_CL_UCP_5_Y … #define regPA_CL_UCP_5_Y_BASE_IDX … #define regPA_CL_UCP_5_Z … #define regPA_CL_UCP_5_Z_BASE_IDX … #define regPA_CL_UCP_5_W … #define regPA_CL_UCP_5_W_BASE_IDX … #define regPA_CL_PROG_NEAR_CLIP_Z … #define regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX … #define regSPI_PS_INPUT_CNTL_0 … #define regSPI_PS_INPUT_CNTL_0_BASE_IDX … #define regSPI_PS_INPUT_CNTL_1 … #define regSPI_PS_INPUT_CNTL_1_BASE_IDX … #define regSPI_PS_INPUT_CNTL_2 … #define regSPI_PS_INPUT_CNTL_2_BASE_IDX … #define regSPI_PS_INPUT_CNTL_3 … #define regSPI_PS_INPUT_CNTL_3_BASE_IDX … #define regSPI_PS_INPUT_CNTL_4 … #define regSPI_PS_INPUT_CNTL_4_BASE_IDX … #define regSPI_PS_INPUT_CNTL_5 … #define regSPI_PS_INPUT_CNTL_5_BASE_IDX … #define regSPI_PS_INPUT_CNTL_6 … #define regSPI_PS_INPUT_CNTL_6_BASE_IDX … #define regSPI_PS_INPUT_CNTL_7 … #define regSPI_PS_INPUT_CNTL_7_BASE_IDX … #define regSPI_PS_INPUT_CNTL_8 … #define regSPI_PS_INPUT_CNTL_8_BASE_IDX … #define regSPI_PS_INPUT_CNTL_9 … #define regSPI_PS_INPUT_CNTL_9_BASE_IDX … #define regSPI_PS_INPUT_CNTL_10 … #define regSPI_PS_INPUT_CNTL_10_BASE_IDX … #define regSPI_PS_INPUT_CNTL_11 … #define regSPI_PS_INPUT_CNTL_11_BASE_IDX … #define regSPI_PS_INPUT_CNTL_12 … #define regSPI_PS_INPUT_CNTL_12_BASE_IDX … #define regSPI_PS_INPUT_CNTL_13 … #define regSPI_PS_INPUT_CNTL_13_BASE_IDX … #define regSPI_PS_INPUT_CNTL_14 … #define regSPI_PS_INPUT_CNTL_14_BASE_IDX … #define regSPI_PS_INPUT_CNTL_15 … #define regSPI_PS_INPUT_CNTL_15_BASE_IDX … #define regSPI_PS_INPUT_CNTL_16 … #define regSPI_PS_INPUT_CNTL_16_BASE_IDX … #define regSPI_PS_INPUT_CNTL_17 … #define regSPI_PS_INPUT_CNTL_17_BASE_IDX … #define regSPI_PS_INPUT_CNTL_18 … #define regSPI_PS_INPUT_CNTL_18_BASE_IDX … #define regSPI_PS_INPUT_CNTL_19 … #define regSPI_PS_INPUT_CNTL_19_BASE_IDX … #define regSPI_PS_INPUT_CNTL_20 … #define regSPI_PS_INPUT_CNTL_20_BASE_IDX … #define regSPI_PS_INPUT_CNTL_21 … #define regSPI_PS_INPUT_CNTL_21_BASE_IDX … #define regSPI_PS_INPUT_CNTL_22 … #define regSPI_PS_INPUT_CNTL_22_BASE_IDX … #define regSPI_PS_INPUT_CNTL_23 … #define regSPI_PS_INPUT_CNTL_23_BASE_IDX … #define regSPI_PS_INPUT_CNTL_24 … #define regSPI_PS_INPUT_CNTL_24_BASE_IDX … #define regSPI_PS_INPUT_CNTL_25 … #define regSPI_PS_INPUT_CNTL_25_BASE_IDX … #define regSPI_PS_INPUT_CNTL_26 … #define regSPI_PS_INPUT_CNTL_26_BASE_IDX … #define regSPI_PS_INPUT_CNTL_27 … #define regSPI_PS_INPUT_CNTL_27_BASE_IDX … #define regSPI_PS_INPUT_CNTL_28 … #define regSPI_PS_INPUT_CNTL_28_BASE_IDX … #define regSPI_PS_INPUT_CNTL_29 … #define regSPI_PS_INPUT_CNTL_29_BASE_IDX … #define regSPI_PS_INPUT_CNTL_30 … #define regSPI_PS_INPUT_CNTL_30_BASE_IDX … #define regSPI_PS_INPUT_CNTL_31 … #define regSPI_PS_INPUT_CNTL_31_BASE_IDX … #define regSPI_VS_OUT_CONFIG … #define regSPI_VS_OUT_CONFIG_BASE_IDX … #define regSPI_PS_INPUT_ENA … #define regSPI_PS_INPUT_ENA_BASE_IDX … #define regSPI_PS_INPUT_ADDR … #define regSPI_PS_INPUT_ADDR_BASE_IDX … #define regSPI_INTERP_CONTROL_0 … #define regSPI_INTERP_CONTROL_0_BASE_IDX … #define regSPI_PS_IN_CONTROL … #define regSPI_PS_IN_CONTROL_BASE_IDX … #define regSPI_BARYC_CNTL … #define regSPI_BARYC_CNTL_BASE_IDX … #define regSPI_TMPRING_SIZE … #define regSPI_TMPRING_SIZE_BASE_IDX … #define regSPI_SHADER_POS_FORMAT … #define regSPI_SHADER_POS_FORMAT_BASE_IDX … #define regSPI_SHADER_Z_FORMAT … #define regSPI_SHADER_Z_FORMAT_BASE_IDX … #define regSPI_SHADER_COL_FORMAT … #define regSPI_SHADER_COL_FORMAT_BASE_IDX … #define regCB_BLEND0_CONTROL … #define regCB_BLEND0_CONTROL_BASE_IDX … #define regCB_BLEND1_CONTROL … #define regCB_BLEND1_CONTROL_BASE_IDX … #define regCB_BLEND2_CONTROL … #define regCB_BLEND2_CONTROL_BASE_IDX … #define regCB_BLEND3_CONTROL … #define regCB_BLEND3_CONTROL_BASE_IDX … #define regCB_BLEND4_CONTROL … #define regCB_BLEND4_CONTROL_BASE_IDX … #define regCB_BLEND5_CONTROL … #define regCB_BLEND5_CONTROL_BASE_IDX … #define regCB_BLEND6_CONTROL … #define regCB_BLEND6_CONTROL_BASE_IDX … #define regCB_BLEND7_CONTROL … #define regCB_BLEND7_CONTROL_BASE_IDX … #define regCB_MRT0_EPITCH … #define regCB_MRT0_EPITCH_BASE_IDX … #define regCB_MRT1_EPITCH … #define regCB_MRT1_EPITCH_BASE_IDX … #define regCB_MRT2_EPITCH … #define regCB_MRT2_EPITCH_BASE_IDX … #define regCB_MRT3_EPITCH … #define regCB_MRT3_EPITCH_BASE_IDX … #define regCB_MRT4_EPITCH … #define regCB_MRT4_EPITCH_BASE_IDX … #define regCB_MRT5_EPITCH … #define regCB_MRT5_EPITCH_BASE_IDX … #define regCB_MRT6_EPITCH … #define regCB_MRT6_EPITCH_BASE_IDX … #define regCB_MRT7_EPITCH … #define regCB_MRT7_EPITCH_BASE_IDX … #define regCS_COPY_STATE … #define regCS_COPY_STATE_BASE_IDX … #define regGFX_COPY_STATE … #define regGFX_COPY_STATE_BASE_IDX … #define regPA_CL_POINT_X_RAD … #define regPA_CL_POINT_X_RAD_BASE_IDX … #define regPA_CL_POINT_Y_RAD … #define regPA_CL_POINT_Y_RAD_BASE_IDX … #define regPA_CL_POINT_SIZE … #define regPA_CL_POINT_SIZE_BASE_IDX … #define regPA_CL_POINT_CULL_RAD … #define regPA_CL_POINT_CULL_RAD_BASE_IDX … #define regVGT_DMA_BASE_HI … #define regVGT_DMA_BASE_HI_BASE_IDX … #define regVGT_DMA_BASE … #define regVGT_DMA_BASE_BASE_IDX … #define regVGT_DRAW_INITIATOR … #define regVGT_DRAW_INITIATOR_BASE_IDX … #define regVGT_IMMED_DATA … #define regVGT_IMMED_DATA_BASE_IDX … #define regVGT_EVENT_ADDRESS_REG … #define regVGT_EVENT_ADDRESS_REG_BASE_IDX … #define regDB_DEPTH_CONTROL … #define regDB_DEPTH_CONTROL_BASE_IDX … #define regDB_EQAA … #define regDB_EQAA_BASE_IDX … #define regCB_COLOR_CONTROL … #define regCB_COLOR_CONTROL_BASE_IDX … #define regDB_SHADER_CONTROL … #define regDB_SHADER_CONTROL_BASE_IDX … #define regPA_CL_CLIP_CNTL … #define regPA_CL_CLIP_CNTL_BASE_IDX … #define regPA_SU_SC_MODE_CNTL … #define regPA_SU_SC_MODE_CNTL_BASE_IDX … #define regPA_CL_VTE_CNTL … #define regPA_CL_VTE_CNTL_BASE_IDX … #define regPA_CL_VS_OUT_CNTL … #define regPA_CL_VS_OUT_CNTL_BASE_IDX … #define regPA_CL_NANINF_CNTL … #define regPA_CL_NANINF_CNTL_BASE_IDX … #define regPA_SU_LINE_STIPPLE_CNTL … #define regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX … #define regPA_SU_LINE_STIPPLE_SCALE … #define regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX … #define regPA_SU_PRIM_FILTER_CNTL … #define regPA_SU_PRIM_FILTER_CNTL_BASE_IDX … #define regPA_SU_SMALL_PRIM_FILTER_CNTL … #define regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX … #define regPA_CL_OBJPRIM_ID_CNTL … #define regPA_CL_OBJPRIM_ID_CNTL_BASE_IDX … #define regPA_CL_NGG_CNTL … #define regPA_CL_NGG_CNTL_BASE_IDX … #define regPA_SU_OVER_RASTERIZATION_CNTL … #define regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX … #define regPA_STEREO_CNTL … #define regPA_STEREO_CNTL_BASE_IDX … #define regPA_SU_POINT_SIZE … #define regPA_SU_POINT_SIZE_BASE_IDX … #define regPA_SU_POINT_MINMAX … #define regPA_SU_POINT_MINMAX_BASE_IDX … #define regPA_SU_LINE_CNTL … #define regPA_SU_LINE_CNTL_BASE_IDX … #define regPA_SC_LINE_STIPPLE … #define regPA_SC_LINE_STIPPLE_BASE_IDX … #define regVGT_OUTPUT_PATH_CNTL … #define regVGT_OUTPUT_PATH_CNTL_BASE_IDX … #define regVGT_HOS_CNTL … #define regVGT_HOS_CNTL_BASE_IDX … #define regVGT_HOS_MAX_TESS_LEVEL … #define regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX … #define regVGT_HOS_MIN_TESS_LEVEL … #define regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX … #define regVGT_HOS_REUSE_DEPTH … #define regVGT_HOS_REUSE_DEPTH_BASE_IDX … #define regVGT_GROUP_PRIM_TYPE … #define regVGT_GROUP_PRIM_TYPE_BASE_IDX … #define regVGT_GROUP_FIRST_DECR … #define regVGT_GROUP_FIRST_DECR_BASE_IDX … #define regVGT_GROUP_DECR … #define regVGT_GROUP_DECR_BASE_IDX … #define regVGT_GROUP_VECT_0_CNTL … #define regVGT_GROUP_VECT_0_CNTL_BASE_IDX … #define regVGT_GROUP_VECT_1_CNTL … #define regVGT_GROUP_VECT_1_CNTL_BASE_IDX … #define regVGT_GROUP_VECT_0_FMT_CNTL … #define regVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX … #define regVGT_GROUP_VECT_1_FMT_CNTL … #define regVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX … #define regVGT_GS_MODE … #define regVGT_GS_MODE_BASE_IDX … #define regVGT_GS_ONCHIP_CNTL … #define regVGT_GS_ONCHIP_CNTL_BASE_IDX … #define regPA_SC_MODE_CNTL_0 … #define regPA_SC_MODE_CNTL_0_BASE_IDX … #define regPA_SC_MODE_CNTL_1 … #define regPA_SC_MODE_CNTL_1_BASE_IDX … #define regVGT_ENHANCE … #define regVGT_ENHANCE_BASE_IDX … #define regVGT_GS_PER_ES … #define regVGT_GS_PER_ES_BASE_IDX … #define regVGT_ES_PER_GS … #define regVGT_ES_PER_GS_BASE_IDX … #define regVGT_GS_PER_VS … #define regVGT_GS_PER_VS_BASE_IDX … #define regVGT_GSVS_RING_OFFSET_1 … #define regVGT_GSVS_RING_OFFSET_1_BASE_IDX … #define regVGT_GSVS_RING_OFFSET_2 … #define regVGT_GSVS_RING_OFFSET_2_BASE_IDX … #define regVGT_GSVS_RING_OFFSET_3 … #define regVGT_GSVS_RING_OFFSET_3_BASE_IDX … #define regVGT_GS_OUT_PRIM_TYPE … #define regVGT_GS_OUT_PRIM_TYPE_BASE_IDX … #define regIA_ENHANCE … #define regIA_ENHANCE_BASE_IDX … #define regVGT_DMA_SIZE … #define regVGT_DMA_SIZE_BASE_IDX … #define regVGT_DMA_MAX_SIZE … #define regVGT_DMA_MAX_SIZE_BASE_IDX … #define regVGT_DMA_INDEX_TYPE … #define regVGT_DMA_INDEX_TYPE_BASE_IDX … #define regWD_ENHANCE … #define regWD_ENHANCE_BASE_IDX … #define regVGT_PRIMITIVEID_EN … #define regVGT_PRIMITIVEID_EN_BASE_IDX … #define regVGT_DMA_NUM_INSTANCES … #define regVGT_DMA_NUM_INSTANCES_BASE_IDX … #define regVGT_PRIMITIVEID_RESET … #define regVGT_PRIMITIVEID_RESET_BASE_IDX … #define regVGT_EVENT_INITIATOR … #define regVGT_EVENT_INITIATOR_BASE_IDX … #define regVGT_GS_MAX_PRIMS_PER_SUBGROUP … #define regVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX … #define regVGT_DRAW_PAYLOAD_CNTL … #define regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX … #define regVGT_INSTANCE_STEP_RATE_0 … #define regVGT_INSTANCE_STEP_RATE_0_BASE_IDX … #define regVGT_INSTANCE_STEP_RATE_1 … #define regVGT_INSTANCE_STEP_RATE_1_BASE_IDX … #define regIA_MULTI_VGT_PARAM_BC … #define regIA_MULTI_VGT_PARAM_BC_BASE_IDX … #define regVGT_ESGS_RING_ITEMSIZE … #define regVGT_ESGS_RING_ITEMSIZE_BASE_IDX … #define regVGT_GSVS_RING_ITEMSIZE … #define regVGT_GSVS_RING_ITEMSIZE_BASE_IDX … #define regVGT_REUSE_OFF … #define regVGT_REUSE_OFF_BASE_IDX … #define regVGT_VTX_CNT_EN … #define regVGT_VTX_CNT_EN_BASE_IDX … #define regDB_HTILE_SURFACE … #define regDB_HTILE_SURFACE_BASE_IDX … #define regDB_SRESULTS_COMPARE_STATE0 … #define regDB_SRESULTS_COMPARE_STATE0_BASE_IDX … #define regDB_SRESULTS_COMPARE_STATE1 … #define regDB_SRESULTS_COMPARE_STATE1_BASE_IDX … #define regDB_PRELOAD_CONTROL … #define regDB_PRELOAD_CONTROL_BASE_IDX … #define regVGT_STRMOUT_BUFFER_SIZE_0 … #define regVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX … #define regVGT_STRMOUT_VTX_STRIDE_0 … #define regVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX … #define regVGT_STRMOUT_BUFFER_OFFSET_0 … #define regVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX … #define regVGT_STRMOUT_BUFFER_SIZE_1 … #define regVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX … #define regVGT_STRMOUT_VTX_STRIDE_1 … #define regVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX … #define regVGT_STRMOUT_BUFFER_OFFSET_1 … #define regVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX … #define regVGT_STRMOUT_BUFFER_SIZE_2 … #define regVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX … #define regVGT_STRMOUT_VTX_STRIDE_2 … #define regVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX … #define regVGT_STRMOUT_BUFFER_OFFSET_2 … #define regVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX … #define regVGT_STRMOUT_BUFFER_SIZE_3 … #define regVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX … #define regVGT_STRMOUT_VTX_STRIDE_3 … #define regVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX … #define regVGT_STRMOUT_BUFFER_OFFSET_3 … #define regVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX … #define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET … #define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX … #define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE … #define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX … #define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE … #define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX … #define regVGT_GS_MAX_VERT_OUT … #define regVGT_GS_MAX_VERT_OUT_BASE_IDX … #define regVGT_TESS_DISTRIBUTION … #define regVGT_TESS_DISTRIBUTION_BASE_IDX … #define regVGT_SHADER_STAGES_EN … #define regVGT_SHADER_STAGES_EN_BASE_IDX … #define regVGT_LS_HS_CONFIG … #define regVGT_LS_HS_CONFIG_BASE_IDX … #define regVGT_GS_VERT_ITEMSIZE … #define regVGT_GS_VERT_ITEMSIZE_BASE_IDX … #define regVGT_GS_VERT_ITEMSIZE_1 … #define regVGT_GS_VERT_ITEMSIZE_1_BASE_IDX … #define regVGT_GS_VERT_ITEMSIZE_2 … #define regVGT_GS_VERT_ITEMSIZE_2_BASE_IDX … #define regVGT_GS_VERT_ITEMSIZE_3 … #define regVGT_GS_VERT_ITEMSIZE_3_BASE_IDX … #define regVGT_TF_PARAM … #define regVGT_TF_PARAM_BASE_IDX … #define regDB_ALPHA_TO_MASK … #define regDB_ALPHA_TO_MASK_BASE_IDX … #define regVGT_DISPATCH_DRAW_INDEX … #define regVGT_DISPATCH_DRAW_INDEX_BASE_IDX … #define regPA_SU_POLY_OFFSET_DB_FMT_CNTL … #define regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX … #define regPA_SU_POLY_OFFSET_CLAMP … #define regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX … #define regPA_SU_POLY_OFFSET_FRONT_SCALE … #define regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX … #define regPA_SU_POLY_OFFSET_FRONT_OFFSET … #define regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX … #define regPA_SU_POLY_OFFSET_BACK_SCALE … #define regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX … #define regPA_SU_POLY_OFFSET_BACK_OFFSET … #define regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX … #define regVGT_GS_INSTANCE_CNT … #define regVGT_GS_INSTANCE_CNT_BASE_IDX … #define regVGT_STRMOUT_CONFIG … #define regVGT_STRMOUT_CONFIG_BASE_IDX … #define regVGT_STRMOUT_BUFFER_CONFIG … #define regVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX … #define regVGT_DMA_EVENT_INITIATOR … #define regVGT_DMA_EVENT_INITIATOR_BASE_IDX … #define regPA_SC_CENTROID_PRIORITY_0 … #define regPA_SC_CENTROID_PRIORITY_0_BASE_IDX … #define regPA_SC_CENTROID_PRIORITY_1 … #define regPA_SC_CENTROID_PRIORITY_1_BASE_IDX … #define regPA_SC_LINE_CNTL … #define regPA_SC_LINE_CNTL_BASE_IDX … #define regPA_SC_AA_CONFIG … #define regPA_SC_AA_CONFIG_BASE_IDX … #define regPA_SU_VTX_CNTL … #define regPA_SU_VTX_CNTL_BASE_IDX … #define regPA_CL_GB_VERT_CLIP_ADJ … #define regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX … #define regPA_CL_GB_VERT_DISC_ADJ … #define regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX … #define regPA_CL_GB_HORZ_CLIP_ADJ … #define regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX … #define regPA_CL_GB_HORZ_DISC_ADJ … #define regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX … #define regPA_SC_AA_MASK_X0Y0_X1Y0 … #define regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX … #define regPA_SC_AA_MASK_X0Y1_X1Y1 … #define regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX … #define regPA_SC_SHADER_CONTROL … #define regPA_SC_SHADER_CONTROL_BASE_IDX … #define regPA_SC_BINNER_CNTL_0 … #define regPA_SC_BINNER_CNTL_0_BASE_IDX … #define regPA_SC_BINNER_CNTL_1 … #define regPA_SC_BINNER_CNTL_1_BASE_IDX … #define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL … #define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX … #define regPA_SC_NGG_MODE_CNTL … #define regPA_SC_NGG_MODE_CNTL_BASE_IDX … #define regVGT_VERTEX_REUSE_BLOCK_CNTL … #define regVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX … #define regVGT_OUT_DEALLOC_CNTL … #define regVGT_OUT_DEALLOC_CNTL_BASE_IDX … #define regCB_COLOR0_BASE … #define regCB_COLOR0_BASE_BASE_IDX … #define regCB_COLOR0_BASE_EXT … #define regCB_COLOR0_BASE_EXT_BASE_IDX … #define regCB_COLOR0_ATTRIB2 … #define regCB_COLOR0_ATTRIB2_BASE_IDX … #define regCB_COLOR0_VIEW … #define regCB_COLOR0_VIEW_BASE_IDX … #define regCB_COLOR0_INFO … #define regCB_COLOR0_INFO_BASE_IDX … #define regCB_COLOR0_ATTRIB … #define regCB_COLOR0_ATTRIB_BASE_IDX … #define regCB_COLOR0_DCC_CONTROL … #define regCB_COLOR0_DCC_CONTROL_BASE_IDX … #define regCB_COLOR0_CMASK … #define regCB_COLOR0_CMASK_BASE_IDX … #define regCB_COLOR0_CMASK_BASE_EXT … #define regCB_COLOR0_CMASK_BASE_EXT_BASE_IDX … #define regCB_COLOR0_FMASK … #define regCB_COLOR0_FMASK_BASE_IDX … #define regCB_COLOR0_FMASK_BASE_EXT … #define regCB_COLOR0_FMASK_BASE_EXT_BASE_IDX … #define regCB_COLOR0_CLEAR_WORD0 … #define regCB_COLOR0_CLEAR_WORD0_BASE_IDX … #define regCB_COLOR0_CLEAR_WORD1 … #define regCB_COLOR0_CLEAR_WORD1_BASE_IDX … #define regCB_COLOR0_DCC_BASE … #define regCB_COLOR0_DCC_BASE_BASE_IDX … #define regCB_COLOR0_DCC_BASE_EXT … #define regCB_COLOR0_DCC_BASE_EXT_BASE_IDX … #define regCB_COLOR1_BASE … #define regCB_COLOR1_BASE_BASE_IDX … #define regCB_COLOR1_BASE_EXT … #define regCB_COLOR1_BASE_EXT_BASE_IDX … #define regCB_COLOR1_ATTRIB2 … #define regCB_COLOR1_ATTRIB2_BASE_IDX … #define regCB_COLOR1_VIEW … #define regCB_COLOR1_VIEW_BASE_IDX … #define regCB_COLOR1_INFO … #define regCB_COLOR1_INFO_BASE_IDX … #define regCB_COLOR1_ATTRIB … #define regCB_COLOR1_ATTRIB_BASE_IDX … #define regCB_COLOR1_DCC_CONTROL … #define regCB_COLOR1_DCC_CONTROL_BASE_IDX … #define regCB_COLOR1_CMASK … #define regCB_COLOR1_CMASK_BASE_IDX … #define regCB_COLOR1_CMASK_BASE_EXT … #define regCB_COLOR1_CMASK_BASE_EXT_BASE_IDX … #define regCB_COLOR1_FMASK … #define regCB_COLOR1_FMASK_BASE_IDX … #define regCB_COLOR1_FMASK_BASE_EXT … #define regCB_COLOR1_FMASK_BASE_EXT_BASE_IDX … #define regCB_COLOR1_CLEAR_WORD0 … #define regCB_COLOR1_CLEAR_WORD0_BASE_IDX … #define regCB_COLOR1_CLEAR_WORD1 … #define regCB_COLOR1_CLEAR_WORD1_BASE_IDX … #define regCB_COLOR1_DCC_BASE … #define regCB_COLOR1_DCC_BASE_BASE_IDX … #define regCB_COLOR1_DCC_BASE_EXT … #define regCB_COLOR1_DCC_BASE_EXT_BASE_IDX … #define regCB_COLOR2_BASE … #define regCB_COLOR2_BASE_BASE_IDX … #define regCB_COLOR2_BASE_EXT … #define regCB_COLOR2_BASE_EXT_BASE_IDX … #define regCB_COLOR2_ATTRIB2 … #define regCB_COLOR2_ATTRIB2_BASE_IDX … #define regCB_COLOR2_VIEW … #define regCB_COLOR2_VIEW_BASE_IDX … #define regCB_COLOR2_INFO … #define regCB_COLOR2_INFO_BASE_IDX … #define regCB_COLOR2_ATTRIB … #define regCB_COLOR2_ATTRIB_BASE_IDX … #define regCB_COLOR2_DCC_CONTROL … #define regCB_COLOR2_DCC_CONTROL_BASE_IDX … #define regCB_COLOR2_CMASK … #define regCB_COLOR2_CMASK_BASE_IDX … #define regCB_COLOR2_CMASK_BASE_EXT … #define regCB_COLOR2_CMASK_BASE_EXT_BASE_IDX … #define regCB_COLOR2_FMASK … #define regCB_COLOR2_FMASK_BASE_IDX … #define regCB_COLOR2_FMASK_BASE_EXT … #define regCB_COLOR2_FMASK_BASE_EXT_BASE_IDX … #define regCB_COLOR2_CLEAR_WORD0 … #define regCB_COLOR2_CLEAR_WORD0_BASE_IDX … #define regCB_COLOR2_CLEAR_WORD1 … #define regCB_COLOR2_CLEAR_WORD1_BASE_IDX … #define regCB_COLOR2_DCC_BASE … #define regCB_COLOR2_DCC_BASE_BASE_IDX … #define regCB_COLOR2_DCC_BASE_EXT … #define regCB_COLOR2_DCC_BASE_EXT_BASE_IDX … #define regCB_COLOR3_BASE … #define regCB_COLOR3_BASE_BASE_IDX … #define regCB_COLOR3_BASE_EXT … #define regCB_COLOR3_BASE_EXT_BASE_IDX … #define regCB_COLOR3_ATTRIB2 … #define regCB_COLOR3_ATTRIB2_BASE_IDX … #define regCB_COLOR3_VIEW … #define regCB_COLOR3_VIEW_BASE_IDX … #define regCB_COLOR3_INFO … #define regCB_COLOR3_INFO_BASE_IDX … #define regCB_COLOR3_ATTRIB … #define regCB_COLOR3_ATTRIB_BASE_IDX … #define regCB_COLOR3_DCC_CONTROL … #define regCB_COLOR3_DCC_CONTROL_BASE_IDX … #define regCB_COLOR3_CMASK … #define regCB_COLOR3_CMASK_BASE_IDX … #define regCB_COLOR3_CMASK_BASE_EXT … #define regCB_COLOR3_CMASK_BASE_EXT_BASE_IDX … #define regCB_COLOR3_FMASK … #define regCB_COLOR3_FMASK_BASE_IDX … #define regCB_COLOR3_FMASK_BASE_EXT … #define regCB_COLOR3_FMASK_BASE_EXT_BASE_IDX … #define regCB_COLOR3_CLEAR_WORD0 … #define regCB_COLOR3_CLEAR_WORD0_BASE_IDX … #define regCB_COLOR3_CLEAR_WORD1 … #define regCB_COLOR3_CLEAR_WORD1_BASE_IDX … #define regCB_COLOR3_DCC_BASE … #define regCB_COLOR3_DCC_BASE_BASE_IDX … #define regCB_COLOR3_DCC_BASE_EXT … #define regCB_COLOR3_DCC_BASE_EXT_BASE_IDX … #define regCB_COLOR4_BASE … #define regCB_COLOR4_BASE_BASE_IDX … #define regCB_COLOR4_BASE_EXT … #define regCB_COLOR4_BASE_EXT_BASE_IDX … #define regCB_COLOR4_ATTRIB2 … #define regCB_COLOR4_ATTRIB2_BASE_IDX … #define regCB_COLOR4_VIEW … #define regCB_COLOR4_VIEW_BASE_IDX … #define regCB_COLOR4_INFO … #define regCB_COLOR4_INFO_BASE_IDX … #define regCB_COLOR4_ATTRIB … #define regCB_COLOR4_ATTRIB_BASE_IDX … #define regCB_COLOR4_DCC_CONTROL … #define regCB_COLOR4_DCC_CONTROL_BASE_IDX … #define regCB_COLOR4_CMASK … #define regCB_COLOR4_CMASK_BASE_IDX … #define regCB_COLOR4_CMASK_BASE_EXT … #define regCB_COLOR4_CMASK_BASE_EXT_BASE_IDX … #define regCB_COLOR4_FMASK … #define regCB_COLOR4_FMASK_BASE_IDX … #define regCB_COLOR4_FMASK_BASE_EXT … #define regCB_COLOR4_FMASK_BASE_EXT_BASE_IDX … #define regCB_COLOR4_CLEAR_WORD0 … #define regCB_COLOR4_CLEAR_WORD0_BASE_IDX … #define regCB_COLOR4_CLEAR_WORD1 … #define regCB_COLOR4_CLEAR_WORD1_BASE_IDX … #define regCB_COLOR4_DCC_BASE … #define regCB_COLOR4_DCC_BASE_BASE_IDX … #define regCB_COLOR4_DCC_BASE_EXT … #define regCB_COLOR4_DCC_BASE_EXT_BASE_IDX … #define regCB_COLOR5_BASE … #define regCB_COLOR5_BASE_BASE_IDX … #define regCB_COLOR5_BASE_EXT … #define regCB_COLOR5_BASE_EXT_BASE_IDX … #define regCB_COLOR5_ATTRIB2 … #define regCB_COLOR5_ATTRIB2_BASE_IDX … #define regCB_COLOR5_VIEW … #define regCB_COLOR5_VIEW_BASE_IDX … #define regCB_COLOR5_INFO … #define regCB_COLOR5_INFO_BASE_IDX … #define regCB_COLOR5_ATTRIB … #define regCB_COLOR5_ATTRIB_BASE_IDX … #define regCB_COLOR5_DCC_CONTROL … #define regCB_COLOR5_DCC_CONTROL_BASE_IDX … #define regCB_COLOR5_CMASK … #define regCB_COLOR5_CMASK_BASE_IDX … #define regCB_COLOR5_CMASK_BASE_EXT … #define regCB_COLOR5_CMASK_BASE_EXT_BASE_IDX … #define regCB_COLOR5_FMASK … #define regCB_COLOR5_FMASK_BASE_IDX … #define regCB_COLOR5_FMASK_BASE_EXT … #define regCB_COLOR5_FMASK_BASE_EXT_BASE_IDX … #define regCB_COLOR5_CLEAR_WORD0 … #define regCB_COLOR5_CLEAR_WORD0_BASE_IDX … #define regCB_COLOR5_CLEAR_WORD1 … #define regCB_COLOR5_CLEAR_WORD1_BASE_IDX … #define regCB_COLOR5_DCC_BASE … #define regCB_COLOR5_DCC_BASE_BASE_IDX … #define regCB_COLOR5_DCC_BASE_EXT … #define regCB_COLOR5_DCC_BASE_EXT_BASE_IDX … #define regCB_COLOR6_BASE … #define regCB_COLOR6_BASE_BASE_IDX … #define regCB_COLOR6_BASE_EXT … #define regCB_COLOR6_BASE_EXT_BASE_IDX … #define regCB_COLOR6_ATTRIB2 … #define regCB_COLOR6_ATTRIB2_BASE_IDX … #define regCB_COLOR6_VIEW … #define regCB_COLOR6_VIEW_BASE_IDX … #define regCB_COLOR6_INFO … #define regCB_COLOR6_INFO_BASE_IDX … #define regCB_COLOR6_ATTRIB … #define regCB_COLOR6_ATTRIB_BASE_IDX … #define regCB_COLOR6_DCC_CONTROL … #define regCB_COLOR6_DCC_CONTROL_BASE_IDX … #define regCB_COLOR6_CMASK … #define regCB_COLOR6_CMASK_BASE_IDX … #define regCB_COLOR6_CMASK_BASE_EXT … #define regCB_COLOR6_CMASK_BASE_EXT_BASE_IDX … #define regCB_COLOR6_FMASK … #define regCB_COLOR6_FMASK_BASE_IDX … #define regCB_COLOR6_FMASK_BASE_EXT … #define regCB_COLOR6_FMASK_BASE_EXT_BASE_IDX … #define regCB_COLOR6_CLEAR_WORD0 … #define regCB_COLOR6_CLEAR_WORD0_BASE_IDX … #define regCB_COLOR6_CLEAR_WORD1 … #define regCB_COLOR6_CLEAR_WORD1_BASE_IDX … #define regCB_COLOR6_DCC_BASE … #define regCB_COLOR6_DCC_BASE_BASE_IDX … #define regCB_COLOR6_DCC_BASE_EXT … #define regCB_COLOR6_DCC_BASE_EXT_BASE_IDX … #define regCB_COLOR7_BASE … #define regCB_COLOR7_BASE_BASE_IDX … #define regCB_COLOR7_BASE_EXT … #define regCB_COLOR7_BASE_EXT_BASE_IDX … #define regCB_COLOR7_ATTRIB2 … #define regCB_COLOR7_ATTRIB2_BASE_IDX … #define regCB_COLOR7_VIEW … #define regCB_COLOR7_VIEW_BASE_IDX … #define regCB_COLOR7_INFO … #define regCB_COLOR7_INFO_BASE_IDX … #define regCB_COLOR7_ATTRIB … #define regCB_COLOR7_ATTRIB_BASE_IDX … #define regCB_COLOR7_DCC_CONTROL … #define regCB_COLOR7_DCC_CONTROL_BASE_IDX … #define regCB_COLOR7_CMASK … #define regCB_COLOR7_CMASK_BASE_IDX … #define regCB_COLOR7_CMASK_BASE_EXT … #define regCB_COLOR7_CMASK_BASE_EXT_BASE_IDX … #define regCB_COLOR7_FMASK … #define regCB_COLOR7_FMASK_BASE_IDX … #define regCB_COLOR7_FMASK_BASE_EXT … #define regCB_COLOR7_FMASK_BASE_EXT_BASE_IDX … #define regCB_COLOR7_CLEAR_WORD0 … #define regCB_COLOR7_CLEAR_WORD0_BASE_IDX … #define regCB_COLOR7_CLEAR_WORD1 … #define regCB_COLOR7_CLEAR_WORD1_BASE_IDX … #define regCB_COLOR7_DCC_BASE … #define regCB_COLOR7_DCC_BASE_BASE_IDX … #define regCB_COLOR7_DCC_BASE_EXT … #define regCB_COLOR7_DCC_BASE_EXT_BASE_IDX … // addressBlock: xcd0_gc_gfxudec // base address: 0x30000 #define regCP_EOP_DONE_ADDR_LO … #define regCP_EOP_DONE_ADDR_LO_BASE_IDX … #define regCP_EOP_DONE_ADDR_HI … #define regCP_EOP_DONE_ADDR_HI_BASE_IDX … #define regCP_EOP_DONE_DATA_LO … #define regCP_EOP_DONE_DATA_LO_BASE_IDX … #define regCP_EOP_DONE_DATA_HI … #define regCP_EOP_DONE_DATA_HI_BASE_IDX … #define regCP_EOP_LAST_FENCE_LO … #define regCP_EOP_LAST_FENCE_LO_BASE_IDX … #define regCP_EOP_LAST_FENCE_HI … #define regCP_EOP_LAST_FENCE_HI_BASE_IDX … #define regCP_STREAM_OUT_ADDR_LO … #define regCP_STREAM_OUT_ADDR_LO_BASE_IDX … #define regCP_STREAM_OUT_ADDR_HI … #define regCP_STREAM_OUT_ADDR_HI_BASE_IDX … #define regCP_NUM_PRIM_WRITTEN_COUNT0_LO … #define regCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX … #define regCP_NUM_PRIM_WRITTEN_COUNT0_HI … #define regCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX … #define regCP_NUM_PRIM_NEEDED_COUNT0_LO … #define regCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX … #define regCP_NUM_PRIM_NEEDED_COUNT0_HI … #define regCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX … #define regCP_NUM_PRIM_WRITTEN_COUNT1_LO … #define regCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX … #define regCP_NUM_PRIM_WRITTEN_COUNT1_HI … #define regCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX … #define regCP_NUM_PRIM_NEEDED_COUNT1_LO … #define regCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX … #define regCP_NUM_PRIM_NEEDED_COUNT1_HI … #define regCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX … #define regCP_NUM_PRIM_WRITTEN_COUNT2_LO … #define regCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX … #define regCP_NUM_PRIM_WRITTEN_COUNT2_HI … #define regCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX … #define regCP_NUM_PRIM_NEEDED_COUNT2_LO … #define regCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX … #define regCP_NUM_PRIM_NEEDED_COUNT2_HI … #define regCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX … #define regCP_NUM_PRIM_WRITTEN_COUNT3_LO … #define regCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX … #define regCP_NUM_PRIM_WRITTEN_COUNT3_HI … #define regCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX … #define regCP_NUM_PRIM_NEEDED_COUNT3_LO … #define regCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX … #define regCP_NUM_PRIM_NEEDED_COUNT3_HI … #define regCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX … #define regCP_PIPE_STATS_ADDR_LO … #define regCP_PIPE_STATS_ADDR_LO_BASE_IDX … #define regCP_PIPE_STATS_ADDR_HI … #define regCP_PIPE_STATS_ADDR_HI_BASE_IDX … #define regCP_VGT_IAVERT_COUNT_LO … #define regCP_VGT_IAVERT_COUNT_LO_BASE_IDX … #define regCP_VGT_IAVERT_COUNT_HI … #define regCP_VGT_IAVERT_COUNT_HI_BASE_IDX … #define regCP_VGT_IAPRIM_COUNT_LO … #define regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX … #define regCP_VGT_IAPRIM_COUNT_HI … #define regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX … #define regCP_VGT_GSPRIM_COUNT_LO … #define regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX … #define regCP_VGT_GSPRIM_COUNT_HI … #define regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX … #define regCP_VGT_VSINVOC_COUNT_LO … #define regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX … #define regCP_VGT_VSINVOC_COUNT_HI … #define regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX … #define regCP_VGT_GSINVOC_COUNT_LO … #define regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX … #define regCP_VGT_GSINVOC_COUNT_HI … #define regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX … #define regCP_VGT_HSINVOC_COUNT_LO … #define regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX … #define regCP_VGT_HSINVOC_COUNT_HI … #define regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX … #define regCP_VGT_DSINVOC_COUNT_LO … #define regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX … #define regCP_VGT_DSINVOC_COUNT_HI … #define regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX … #define regCP_PA_CINVOC_COUNT_LO … #define regCP_PA_CINVOC_COUNT_LO_BASE_IDX … #define regCP_PA_CINVOC_COUNT_HI … #define regCP_PA_CINVOC_COUNT_HI_BASE_IDX … #define regCP_PA_CPRIM_COUNT_LO … #define regCP_PA_CPRIM_COUNT_LO_BASE_IDX … #define regCP_PA_CPRIM_COUNT_HI … #define regCP_PA_CPRIM_COUNT_HI_BASE_IDX … #define regCP_SC_PSINVOC_COUNT0_LO … #define regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX … #define regCP_SC_PSINVOC_COUNT0_HI … #define regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX … #define regCP_SC_PSINVOC_COUNT1_LO … #define regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX … #define regCP_SC_PSINVOC_COUNT1_HI … #define regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX … #define regCP_VGT_CSINVOC_COUNT_LO … #define regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX … #define regCP_VGT_CSINVOC_COUNT_HI … #define regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX … #define regCP_PIPE_STATS_CONTROL … #define regCP_PIPE_STATS_CONTROL_BASE_IDX … #define regCP_STREAM_OUT_CONTROL … #define regCP_STREAM_OUT_CONTROL_BASE_IDX … #define regCP_STRMOUT_CNTL … #define regCP_STRMOUT_CNTL_BASE_IDX … #define regSCRATCH_REG0 … #define regSCRATCH_REG0_BASE_IDX … #define regSCRATCH_REG1 … #define regSCRATCH_REG1_BASE_IDX … #define regSCRATCH_REG2 … #define regSCRATCH_REG2_BASE_IDX … #define regSCRATCH_REG3 … #define regSCRATCH_REG3_BASE_IDX … #define regSCRATCH_REG4 … #define regSCRATCH_REG4_BASE_IDX … #define regSCRATCH_REG5 … #define regSCRATCH_REG5_BASE_IDX … #define regSCRATCH_REG6 … #define regSCRATCH_REG6_BASE_IDX … #define regSCRATCH_REG7 … #define regSCRATCH_REG7_BASE_IDX … #define regCP_APPEND_DATA_HI … #define regCP_APPEND_DATA_HI_BASE_IDX … #define regCP_APPEND_LAST_CS_FENCE_HI … #define regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX … #define regCP_APPEND_LAST_PS_FENCE_HI … #define regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX … #define regSCRATCH_UMSK … #define regSCRATCH_UMSK_BASE_IDX … #define regSCRATCH_ADDR … #define regSCRATCH_ADDR_BASE_IDX … #define regCP_PFP_ATOMIC_PREOP_LO … #define regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX … #define regCP_PFP_ATOMIC_PREOP_HI … #define regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX … #define regCP_PFP_GDS_ATOMIC0_PREOP_LO … #define regCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX … #define regCP_PFP_GDS_ATOMIC0_PREOP_HI … #define regCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX … #define regCP_PFP_GDS_ATOMIC1_PREOP_LO … #define regCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX … #define regCP_PFP_GDS_ATOMIC1_PREOP_HI … #define regCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX … #define regCP_APPEND_ADDR_LO … #define regCP_APPEND_ADDR_LO_BASE_IDX … #define regCP_APPEND_ADDR_HI … #define regCP_APPEND_ADDR_HI_BASE_IDX … #define regCP_APPEND_DATA_LO … #define regCP_APPEND_DATA_LO_BASE_IDX … #define regCP_APPEND_LAST_CS_FENCE_LO … #define regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX … #define regCP_APPEND_LAST_PS_FENCE_LO … #define regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX … #define regCP_ATOMIC_PREOP_LO … #define regCP_ATOMIC_PREOP_LO_BASE_IDX … #define regCP_ME_ATOMIC_PREOP_LO … #define regCP_ME_ATOMIC_PREOP_LO_BASE_IDX … #define regCP_ATOMIC_PREOP_HI … #define regCP_ATOMIC_PREOP_HI_BASE_IDX … #define regCP_ME_ATOMIC_PREOP_HI … #define regCP_ME_ATOMIC_PREOP_HI_BASE_IDX … #define regCP_GDS_ATOMIC0_PREOP_LO … #define regCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX … #define regCP_ME_GDS_ATOMIC0_PREOP_LO … #define regCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX … #define regCP_GDS_ATOMIC0_PREOP_HI … #define regCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX … #define regCP_ME_GDS_ATOMIC0_PREOP_HI … #define regCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX … #define regCP_GDS_ATOMIC1_PREOP_LO … #define regCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX … #define regCP_ME_GDS_ATOMIC1_PREOP_LO … #define regCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX … #define regCP_GDS_ATOMIC1_PREOP_HI … #define regCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX … #define regCP_ME_GDS_ATOMIC1_PREOP_HI … #define regCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX … #define regCP_ME_MC_WADDR_LO … #define regCP_ME_MC_WADDR_LO_BASE_IDX … #define regCP_ME_MC_WADDR_HI … #define regCP_ME_MC_WADDR_HI_BASE_IDX … #define regCP_ME_MC_WDATA_LO … #define regCP_ME_MC_WDATA_LO_BASE_IDX … #define regCP_ME_MC_WDATA_HI … #define regCP_ME_MC_WDATA_HI_BASE_IDX … #define regCP_ME_MC_RADDR_LO … #define regCP_ME_MC_RADDR_LO_BASE_IDX … #define regCP_ME_MC_RADDR_HI … #define regCP_ME_MC_RADDR_HI_BASE_IDX … #define regCP_SEM_WAIT_TIMER … #define regCP_SEM_WAIT_TIMER_BASE_IDX … #define regCP_SIG_SEM_ADDR_LO … #define regCP_SIG_SEM_ADDR_LO_BASE_IDX … #define regCP_SIG_SEM_ADDR_HI … #define regCP_SIG_SEM_ADDR_HI_BASE_IDX … #define regCP_WAIT_REG_MEM_TIMEOUT … #define regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX … #define regCP_WAIT_SEM_ADDR_LO … #define regCP_WAIT_SEM_ADDR_LO_BASE_IDX … #define regCP_WAIT_SEM_ADDR_HI … #define regCP_WAIT_SEM_ADDR_HI_BASE_IDX … #define regCP_DMA_PFP_CONTROL … #define regCP_DMA_PFP_CONTROL_BASE_IDX … #define regCP_DMA_ME_CONTROL … #define regCP_DMA_ME_CONTROL_BASE_IDX … #define regCP_COHER_BASE_HI … #define regCP_COHER_BASE_HI_BASE_IDX … #define regCP_COHER_START_DELAY … #define regCP_COHER_START_DELAY_BASE_IDX … #define regCP_COHER_CNTL … #define regCP_COHER_CNTL_BASE_IDX … #define regCP_COHER_SIZE … #define regCP_COHER_SIZE_BASE_IDX … #define regCP_COHER_BASE … #define regCP_COHER_BASE_BASE_IDX … #define regCP_COHER_STATUS … #define regCP_COHER_STATUS_BASE_IDX … #define regCP_DMA_ME_SRC_ADDR … #define regCP_DMA_ME_SRC_ADDR_BASE_IDX … #define regCP_DMA_ME_SRC_ADDR_HI … #define regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX … #define regCP_DMA_ME_DST_ADDR … #define regCP_DMA_ME_DST_ADDR_BASE_IDX … #define regCP_DMA_ME_DST_ADDR_HI … #define regCP_DMA_ME_DST_ADDR_HI_BASE_IDX … #define regCP_DMA_ME_COMMAND … #define regCP_DMA_ME_COMMAND_BASE_IDX … #define regCP_DMA_PFP_SRC_ADDR … #define regCP_DMA_PFP_SRC_ADDR_BASE_IDX … #define regCP_DMA_PFP_SRC_ADDR_HI … #define regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX … #define regCP_DMA_PFP_DST_ADDR … #define regCP_DMA_PFP_DST_ADDR_BASE_IDX … #define regCP_DMA_PFP_DST_ADDR_HI … #define regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX … #define regCP_DMA_PFP_COMMAND … #define regCP_DMA_PFP_COMMAND_BASE_IDX … #define regCP_DMA_CNTL … #define regCP_DMA_CNTL_BASE_IDX … #define regCP_DMA_READ_TAGS … #define regCP_DMA_READ_TAGS_BASE_IDX … #define regCP_COHER_SIZE_HI … #define regCP_COHER_SIZE_HI_BASE_IDX … #define regCP_PFP_IB_CONTROL … #define regCP_PFP_IB_CONTROL_BASE_IDX … #define regCP_PFP_LOAD_CONTROL … #define regCP_PFP_LOAD_CONTROL_BASE_IDX … #define regCP_SCRATCH_INDEX … #define regCP_SCRATCH_INDEX_BASE_IDX … #define regCP_SCRATCH_DATA … #define regCP_SCRATCH_DATA_BASE_IDX … #define regCP_RB_OFFSET … #define regCP_RB_OFFSET_BASE_IDX … #define regCP_IB1_OFFSET … #define regCP_IB1_OFFSET_BASE_IDX … #define regCP_IB2_OFFSET … #define regCP_IB2_OFFSET_BASE_IDX … #define regCP_IB1_PREAMBLE_BEGIN … #define regCP_IB1_PREAMBLE_BEGIN_BASE_IDX … #define regCP_IB1_PREAMBLE_END … #define regCP_IB1_PREAMBLE_END_BASE_IDX … #define regCP_IB2_PREAMBLE_BEGIN … #define regCP_IB2_PREAMBLE_BEGIN_BASE_IDX … #define regCP_IB2_PREAMBLE_END … #define regCP_IB2_PREAMBLE_END_BASE_IDX … #define regCP_CE_IB1_OFFSET … #define regCP_CE_IB1_OFFSET_BASE_IDX … #define regCP_CE_IB2_OFFSET … #define regCP_CE_IB2_OFFSET_BASE_IDX … #define regCP_CE_COUNTER … #define regCP_CE_COUNTER_BASE_IDX … #define regCP_CE_RB_OFFSET … #define regCP_CE_RB_OFFSET_BASE_IDX … #define regCP_CE_INIT_CMD_BUFSZ … #define regCP_CE_INIT_CMD_BUFSZ_BASE_IDX … #define regCP_CE_IB1_CMD_BUFSZ … #define regCP_CE_IB1_CMD_BUFSZ_BASE_IDX … #define regCP_CE_IB2_CMD_BUFSZ … #define regCP_CE_IB2_CMD_BUFSZ_BASE_IDX … #define regCP_IB1_CMD_BUFSZ … #define regCP_IB1_CMD_BUFSZ_BASE_IDX … #define regCP_IB2_CMD_BUFSZ … #define regCP_IB2_CMD_BUFSZ_BASE_IDX … #define regCP_ST_CMD_BUFSZ … #define regCP_ST_CMD_BUFSZ_BASE_IDX … #define regCP_CE_INIT_BASE_LO … #define regCP_CE_INIT_BASE_LO_BASE_IDX … #define regCP_CE_INIT_BASE_HI … #define regCP_CE_INIT_BASE_HI_BASE_IDX … #define regCP_CE_INIT_BUFSZ … #define regCP_CE_INIT_BUFSZ_BASE_IDX … #define regCP_CE_IB1_BASE_LO … #define regCP_CE_IB1_BASE_LO_BASE_IDX … #define regCP_CE_IB1_BASE_HI … #define regCP_CE_IB1_BASE_HI_BASE_IDX … #define regCP_CE_IB1_BUFSZ … #define regCP_CE_IB1_BUFSZ_BASE_IDX … #define regCP_CE_IB2_BASE_LO … #define regCP_CE_IB2_BASE_LO_BASE_IDX … #define regCP_CE_IB2_BASE_HI … #define regCP_CE_IB2_BASE_HI_BASE_IDX … #define regCP_CE_IB2_BUFSZ … #define regCP_CE_IB2_BUFSZ_BASE_IDX … #define regCP_IB1_BASE_LO … #define regCP_IB1_BASE_LO_BASE_IDX … #define regCP_IB1_BASE_HI … #define regCP_IB1_BASE_HI_BASE_IDX … #define regCP_IB1_BUFSZ … #define regCP_IB1_BUFSZ_BASE_IDX … #define regCP_IB2_BASE_LO … #define regCP_IB2_BASE_LO_BASE_IDX … #define regCP_IB2_BASE_HI … #define regCP_IB2_BASE_HI_BASE_IDX … #define regCP_IB2_BUFSZ … #define regCP_IB2_BUFSZ_BASE_IDX … #define regCP_ST_BASE_LO … #define regCP_ST_BASE_LO_BASE_IDX … #define regCP_ST_BASE_HI … #define regCP_ST_BASE_HI_BASE_IDX … #define regCP_ST_BUFSZ … #define regCP_ST_BUFSZ_BASE_IDX … #define regCP_EOP_DONE_EVENT_CNTL … #define regCP_EOP_DONE_EVENT_CNTL_BASE_IDX … #define regCP_EOP_DONE_DATA_CNTL … #define regCP_EOP_DONE_DATA_CNTL_BASE_IDX … #define regCP_EOP_DONE_CNTX_ID … #define regCP_EOP_DONE_CNTX_ID_BASE_IDX … #define regCP_PFP_COMPLETION_STATUS … #define regCP_PFP_COMPLETION_STATUS_BASE_IDX … #define regCP_CE_COMPLETION_STATUS … #define regCP_CE_COMPLETION_STATUS_BASE_IDX … #define regCP_PRED_NOT_VISIBLE … #define regCP_PRED_NOT_VISIBLE_BASE_IDX … #define regCP_PFP_METADATA_BASE_ADDR … #define regCP_PFP_METADATA_BASE_ADDR_BASE_IDX … #define regCP_PFP_METADATA_BASE_ADDR_HI … #define regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX … #define regCP_CE_METADATA_BASE_ADDR … #define regCP_CE_METADATA_BASE_ADDR_BASE_IDX … #define regCP_CE_METADATA_BASE_ADDR_HI … #define regCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX … #define regCP_DRAW_INDX_INDR_ADDR … #define regCP_DRAW_INDX_INDR_ADDR_BASE_IDX … #define regCP_DRAW_INDX_INDR_ADDR_HI … #define regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX … #define regCP_DISPATCH_INDR_ADDR … #define regCP_DISPATCH_INDR_ADDR_BASE_IDX … #define regCP_DISPATCH_INDR_ADDR_HI … #define regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX … #define regCP_INDEX_BASE_ADDR … #define regCP_INDEX_BASE_ADDR_BASE_IDX … #define regCP_INDEX_BASE_ADDR_HI … #define regCP_INDEX_BASE_ADDR_HI_BASE_IDX … #define regCP_INDEX_TYPE … #define regCP_INDEX_TYPE_BASE_IDX … #define regCP_GDS_BKUP_ADDR … #define regCP_GDS_BKUP_ADDR_BASE_IDX … #define regCP_GDS_BKUP_ADDR_HI … #define regCP_GDS_BKUP_ADDR_HI_BASE_IDX … #define regCP_SAMPLE_STATUS … #define regCP_SAMPLE_STATUS_BASE_IDX … #define regCP_ME_COHER_CNTL … #define regCP_ME_COHER_CNTL_BASE_IDX … #define regCP_ME_COHER_SIZE … #define regCP_ME_COHER_SIZE_BASE_IDX … #define regCP_ME_COHER_SIZE_HI … #define regCP_ME_COHER_SIZE_HI_BASE_IDX … #define regCP_ME_COHER_BASE … #define regCP_ME_COHER_BASE_BASE_IDX … #define regCP_ME_COHER_BASE_HI … #define regCP_ME_COHER_BASE_HI_BASE_IDX … #define regCP_ME_COHER_STATUS … #define regCP_ME_COHER_STATUS_BASE_IDX … #define regRLC_GPM_PERF_COUNT_0 … #define regRLC_GPM_PERF_COUNT_0_BASE_IDX … #define regRLC_GPM_PERF_COUNT_1 … #define regRLC_GPM_PERF_COUNT_1_BASE_IDX … #define regGRBM_GFX_INDEX … #define regGRBM_GFX_INDEX_BASE_IDX … #define regVGT_GSVS_RING_SIZE … #define regVGT_GSVS_RING_SIZE_BASE_IDX … #define regVGT_PRIMITIVE_TYPE … #define regVGT_PRIMITIVE_TYPE_BASE_IDX … #define regVGT_INDEX_TYPE … #define regVGT_INDEX_TYPE_BASE_IDX … #define regVGT_STRMOUT_BUFFER_FILLED_SIZE_0 … #define regVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX … #define regVGT_STRMOUT_BUFFER_FILLED_SIZE_1 … #define regVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX … #define regVGT_STRMOUT_BUFFER_FILLED_SIZE_2 … #define regVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX … #define regVGT_STRMOUT_BUFFER_FILLED_SIZE_3 … #define regVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX … #define regVGT_MAX_VTX_INDX … #define regVGT_MAX_VTX_INDX_BASE_IDX … #define regVGT_MIN_VTX_INDX … #define regVGT_MIN_VTX_INDX_BASE_IDX … #define regVGT_INDX_OFFSET … #define regVGT_INDX_OFFSET_BASE_IDX … #define regVGT_MULTI_PRIM_IB_RESET_EN … #define regVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX … #define regVGT_NUM_INDICES … #define regVGT_NUM_INDICES_BASE_IDX … #define regVGT_NUM_INSTANCES … #define regVGT_NUM_INSTANCES_BASE_IDX … #define regVGT_TF_RING_SIZE … #define regVGT_TF_RING_SIZE_BASE_IDX … #define regVGT_HS_OFFCHIP_PARAM … #define regVGT_HS_OFFCHIP_PARAM_BASE_IDX … #define regVGT_TF_MEMORY_BASE … #define regVGT_TF_MEMORY_BASE_BASE_IDX … #define regVGT_TF_MEMORY_BASE_HI … #define regVGT_TF_MEMORY_BASE_HI_BASE_IDX … #define regWD_POS_BUF_BASE … #define regWD_POS_BUF_BASE_BASE_IDX … #define regWD_POS_BUF_BASE_HI … #define regWD_POS_BUF_BASE_HI_BASE_IDX … #define regWD_CNTL_SB_BUF_BASE … #define regWD_CNTL_SB_BUF_BASE_BASE_IDX … #define regWD_CNTL_SB_BUF_BASE_HI … #define regWD_CNTL_SB_BUF_BASE_HI_BASE_IDX … #define regWD_INDEX_BUF_BASE … #define regWD_INDEX_BUF_BASE_BASE_IDX … #define regWD_INDEX_BUF_BASE_HI … #define regWD_INDEX_BUF_BASE_HI_BASE_IDX … #define regIA_MULTI_VGT_PARAM … #define regIA_MULTI_VGT_PARAM_BASE_IDX … #define regVGT_INSTANCE_BASE_ID … #define regVGT_INSTANCE_BASE_ID_BASE_IDX … #define regPA_SU_LINE_STIPPLE_VALUE … #define regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX … #define regPA_SC_LINE_STIPPLE_STATE … #define regPA_SC_LINE_STIPPLE_STATE_BASE_IDX … #define regPA_SC_SCREEN_EXTENT_MIN_0 … #define regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX … #define regPA_SC_SCREEN_EXTENT_MAX_0 … #define regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX … #define regPA_SC_SCREEN_EXTENT_MIN_1 … #define regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX … #define regPA_SC_SCREEN_EXTENT_MAX_1 … #define regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX … #define regPA_SC_P3D_TRAP_SCREEN_HV_EN … #define regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX … #define regPA_SC_P3D_TRAP_SCREEN_H … #define regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX … #define regPA_SC_P3D_TRAP_SCREEN_V … #define regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX … #define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE … #define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX … #define regPA_SC_P3D_TRAP_SCREEN_COUNT … #define regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX … #define regPA_SC_HP3D_TRAP_SCREEN_HV_EN … #define regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX … #define regPA_SC_HP3D_TRAP_SCREEN_H … #define regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX … #define regPA_SC_HP3D_TRAP_SCREEN_V … #define regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX … #define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE … #define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX … #define regPA_SC_HP3D_TRAP_SCREEN_COUNT … #define regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX … #define regPA_SC_TRAP_SCREEN_HV_EN … #define regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX … #define regPA_SC_TRAP_SCREEN_H … #define regPA_SC_TRAP_SCREEN_H_BASE_IDX … #define regPA_SC_TRAP_SCREEN_V … #define regPA_SC_TRAP_SCREEN_V_BASE_IDX … #define regPA_SC_TRAP_SCREEN_OCCURRENCE … #define regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX … #define regPA_SC_TRAP_SCREEN_COUNT … #define regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX … #define regPA_STATE_STEREO_X … #define regPA_STATE_STEREO_X_BASE_IDX … #define regSQ_THREAD_TRACE_BASE … #define regSQ_THREAD_TRACE_BASE_BASE_IDX … #define regSQ_THREAD_TRACE_SIZE … #define regSQ_THREAD_TRACE_SIZE_BASE_IDX … #define regSQ_THREAD_TRACE_MASK … #define regSQ_THREAD_TRACE_MASK_BASE_IDX … #define regSQ_THREAD_TRACE_TOKEN_MASK … #define regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX … #define regSQ_THREAD_TRACE_PERF_MASK … #define regSQ_THREAD_TRACE_PERF_MASK_BASE_IDX … #define regSQ_THREAD_TRACE_CTRL … #define regSQ_THREAD_TRACE_CTRL_BASE_IDX … #define regSQ_THREAD_TRACE_MODE … #define regSQ_THREAD_TRACE_MODE_BASE_IDX … #define regSQ_THREAD_TRACE_BASE2 … #define regSQ_THREAD_TRACE_BASE2_BASE_IDX … #define regSQ_THREAD_TRACE_TOKEN_MASK2 … #define regSQ_THREAD_TRACE_TOKEN_MASK2_BASE_IDX … #define regSQ_THREAD_TRACE_WPTR … #define regSQ_THREAD_TRACE_WPTR_BASE_IDX … #define regSQ_THREAD_TRACE_STATUS … #define regSQ_THREAD_TRACE_STATUS_BASE_IDX … #define regSQ_THREAD_TRACE_HIWATER … #define regSQ_THREAD_TRACE_HIWATER_BASE_IDX … #define regSQ_THREAD_TRACE_CNTR … #define regSQ_THREAD_TRACE_CNTR_BASE_IDX … #define regSQ_THREAD_TRACE_USERDATA_0 … #define regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX … #define regSQ_THREAD_TRACE_USERDATA_1 … #define regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX … #define regSQ_THREAD_TRACE_USERDATA_2 … #define regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX … #define regSQ_THREAD_TRACE_USERDATA_3 … #define regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX … #define regSQC_CACHES … #define regSQC_CACHES_BASE_IDX … #define regSQC_WRITEBACK … #define regSQC_WRITEBACK_BASE_IDX … #define regDB_OCCLUSION_COUNT0_LOW … #define regDB_OCCLUSION_COUNT0_LOW_BASE_IDX … #define regDB_OCCLUSION_COUNT0_HI … #define regDB_OCCLUSION_COUNT0_HI_BASE_IDX … #define regDB_OCCLUSION_COUNT1_LOW … #define regDB_OCCLUSION_COUNT1_LOW_BASE_IDX … #define regDB_OCCLUSION_COUNT1_HI … #define regDB_OCCLUSION_COUNT1_HI_BASE_IDX … #define regDB_OCCLUSION_COUNT2_LOW … #define regDB_OCCLUSION_COUNT2_LOW_BASE_IDX … #define regDB_OCCLUSION_COUNT2_HI … #define regDB_OCCLUSION_COUNT2_HI_BASE_IDX … #define regDB_OCCLUSION_COUNT3_LOW … #define regDB_OCCLUSION_COUNT3_LOW_BASE_IDX … #define regDB_OCCLUSION_COUNT3_HI … #define regDB_OCCLUSION_COUNT3_HI_BASE_IDX … #define regDB_ZPASS_COUNT_LOW … #define regDB_ZPASS_COUNT_LOW_BASE_IDX … #define regDB_ZPASS_COUNT_HI … #define regDB_ZPASS_COUNT_HI_BASE_IDX … #define regGDS_RD_ADDR … #define regGDS_RD_ADDR_BASE_IDX … #define regGDS_RD_DATA … #define regGDS_RD_DATA_BASE_IDX … #define regGDS_RD_BURST_ADDR … #define regGDS_RD_BURST_ADDR_BASE_IDX … #define regGDS_RD_BURST_COUNT … #define regGDS_RD_BURST_COUNT_BASE_IDX … #define regGDS_RD_BURST_DATA … #define regGDS_RD_BURST_DATA_BASE_IDX … #define regGDS_WR_ADDR … #define regGDS_WR_ADDR_BASE_IDX … #define regGDS_WR_DATA … #define regGDS_WR_DATA_BASE_IDX … #define regGDS_WR_BURST_ADDR … #define regGDS_WR_BURST_ADDR_BASE_IDX … #define regGDS_WR_BURST_DATA … #define regGDS_WR_BURST_DATA_BASE_IDX … #define regGDS_WRITE_COMPLETE … #define regGDS_WRITE_COMPLETE_BASE_IDX … #define regGDS_ATOM_CNTL … #define regGDS_ATOM_CNTL_BASE_IDX … #define regGDS_ATOM_COMPLETE … #define regGDS_ATOM_COMPLETE_BASE_IDX … #define regGDS_ATOM_BASE … #define regGDS_ATOM_BASE_BASE_IDX … #define regGDS_ATOM_SIZE … #define regGDS_ATOM_SIZE_BASE_IDX … #define regGDS_ATOM_OFFSET0 … #define regGDS_ATOM_OFFSET0_BASE_IDX … #define regGDS_ATOM_OFFSET1 … #define regGDS_ATOM_OFFSET1_BASE_IDX … #define regGDS_ATOM_DST … #define regGDS_ATOM_DST_BASE_IDX … #define regGDS_ATOM_OP … #define regGDS_ATOM_OP_BASE_IDX … #define regGDS_ATOM_SRC0 … #define regGDS_ATOM_SRC0_BASE_IDX … #define regGDS_ATOM_SRC0_U … #define regGDS_ATOM_SRC0_U_BASE_IDX … #define regGDS_ATOM_SRC1 … #define regGDS_ATOM_SRC1_BASE_IDX … #define regGDS_ATOM_SRC1_U … #define regGDS_ATOM_SRC1_U_BASE_IDX … #define regGDS_ATOM_READ0 … #define regGDS_ATOM_READ0_BASE_IDX … #define regGDS_ATOM_READ0_U … #define regGDS_ATOM_READ0_U_BASE_IDX … #define regGDS_ATOM_READ1 … #define regGDS_ATOM_READ1_BASE_IDX … #define regGDS_ATOM_READ1_U … #define regGDS_ATOM_READ1_U_BASE_IDX … #define regGDS_GWS_RESOURCE_CNTL … #define regGDS_GWS_RESOURCE_CNTL_BASE_IDX … #define regGDS_GWS_RESOURCE … #define regGDS_GWS_RESOURCE_BASE_IDX … #define regGDS_GWS_RESOURCE_CNT … #define regGDS_GWS_RESOURCE_CNT_BASE_IDX … #define regGDS_OA_CNTL … #define regGDS_OA_CNTL_BASE_IDX … #define regGDS_OA_COUNTER … #define regGDS_OA_COUNTER_BASE_IDX … #define regGDS_OA_ADDRESS … #define regGDS_OA_ADDRESS_BASE_IDX … #define regGDS_OA_INCDEC … #define regGDS_OA_INCDEC_BASE_IDX … #define regGDS_OA_RING_SIZE … #define regGDS_OA_RING_SIZE_BASE_IDX … #define regSPI_CONFIG_CNTL … #define regSPI_CONFIG_CNTL_BASE_IDX … #define regSPI_CONFIG_CNTL_1 … #define regSPI_CONFIG_CNTL_1_BASE_IDX … #define regSPI_CONFIG_CNTL_2 … #define regSPI_CONFIG_CNTL_2_BASE_IDX … #define regSPI_WAVE_LIMIT_CNTL … #define regSPI_WAVE_LIMIT_CNTL_BASE_IDX … // addressBlock: xcd0_gc_gccanedec // base address: 0x33d00 #define regGC_CANE_ERR_STATUS … #define regGC_CANE_ERR_STATUS_BASE_IDX … #define regGC_CANE_UE_ERR_STATUS_LO … #define regGC_CANE_UE_ERR_STATUS_LO_BASE_IDX … #define regGC_CANE_UE_ERR_STATUS_HI … #define regGC_CANE_UE_ERR_STATUS_HI_BASE_IDX … #define regGC_CANE_CE_ERR_STATUS_LO … #define regGC_CANE_CE_ERR_STATUS_LO_BASE_IDX … #define regGC_CANE_CE_ERR_STATUS_HI … #define regGC_CANE_CE_ERR_STATUS_HI_BASE_IDX … // addressBlock: xcd0_gc_perfddec // base address: 0x34000 #define regCPG_PERFCOUNTER1_LO … #define regCPG_PERFCOUNTER1_LO_BASE_IDX … #define regCPG_PERFCOUNTER1_HI … #define regCPG_PERFCOUNTER1_HI_BASE_IDX … #define regCPG_PERFCOUNTER0_LO … #define regCPG_PERFCOUNTER0_LO_BASE_IDX … #define regCPG_PERFCOUNTER0_HI … #define regCPG_PERFCOUNTER0_HI_BASE_IDX … #define regCPC_PERFCOUNTER1_LO … #define regCPC_PERFCOUNTER1_LO_BASE_IDX … #define regCPC_PERFCOUNTER1_HI … #define regCPC_PERFCOUNTER1_HI_BASE_IDX … #define regCPC_PERFCOUNTER0_LO … #define regCPC_PERFCOUNTER0_LO_BASE_IDX … #define regCPC_PERFCOUNTER0_HI … #define regCPC_PERFCOUNTER0_HI_BASE_IDX … #define regCPF_PERFCOUNTER1_LO … #define regCPF_PERFCOUNTER1_LO_BASE_IDX … #define regCPF_PERFCOUNTER1_HI … #define regCPF_PERFCOUNTER1_HI_BASE_IDX … #define regCPF_PERFCOUNTER0_LO … #define regCPF_PERFCOUNTER0_LO_BASE_IDX … #define regCPF_PERFCOUNTER0_HI … #define regCPF_PERFCOUNTER0_HI_BASE_IDX … #define regCPF_LATENCY_STATS_DATA … #define regCPF_LATENCY_STATS_DATA_BASE_IDX … #define regCPG_LATENCY_STATS_DATA … #define regCPG_LATENCY_STATS_DATA_BASE_IDX … #define regCPC_LATENCY_STATS_DATA … #define regCPC_LATENCY_STATS_DATA_BASE_IDX … #define regGRBM_PERFCOUNTER0_LO … #define regGRBM_PERFCOUNTER0_LO_BASE_IDX … #define regGRBM_PERFCOUNTER0_HI … #define regGRBM_PERFCOUNTER0_HI_BASE_IDX … #define regGRBM_PERFCOUNTER1_LO … #define regGRBM_PERFCOUNTER1_LO_BASE_IDX … #define regGRBM_PERFCOUNTER1_HI … #define regGRBM_PERFCOUNTER1_HI_BASE_IDX … #define regGRBM_SE0_PERFCOUNTER_LO … #define regGRBM_SE0_PERFCOUNTER_LO_BASE_IDX … #define regGRBM_SE0_PERFCOUNTER_HI … #define regGRBM_SE0_PERFCOUNTER_HI_BASE_IDX … #define regGRBM_SE1_PERFCOUNTER_LO … #define regGRBM_SE1_PERFCOUNTER_LO_BASE_IDX … #define regGRBM_SE1_PERFCOUNTER_HI … #define regGRBM_SE1_PERFCOUNTER_HI_BASE_IDX … #define regGRBM_SE2_PERFCOUNTER_LO … #define regGRBM_SE2_PERFCOUNTER_LO_BASE_IDX … #define regGRBM_SE2_PERFCOUNTER_HI … #define regGRBM_SE2_PERFCOUNTER_HI_BASE_IDX … #define regGRBM_SE3_PERFCOUNTER_LO … #define regGRBM_SE3_PERFCOUNTER_LO_BASE_IDX … #define regGRBM_SE3_PERFCOUNTER_HI … #define regGRBM_SE3_PERFCOUNTER_HI_BASE_IDX … #define regWD_PERFCOUNTER0_LO … #define regWD_PERFCOUNTER0_LO_BASE_IDX … #define regWD_PERFCOUNTER0_HI … #define regWD_PERFCOUNTER0_HI_BASE_IDX … #define regWD_PERFCOUNTER1_LO … #define regWD_PERFCOUNTER1_LO_BASE_IDX … #define regWD_PERFCOUNTER1_HI … #define regWD_PERFCOUNTER1_HI_BASE_IDX … #define regWD_PERFCOUNTER2_LO … #define regWD_PERFCOUNTER2_LO_BASE_IDX … #define regWD_PERFCOUNTER2_HI … #define regWD_PERFCOUNTER2_HI_BASE_IDX … #define regWD_PERFCOUNTER3_LO … #define regWD_PERFCOUNTER3_LO_BASE_IDX … #define regWD_PERFCOUNTER3_HI … #define regWD_PERFCOUNTER3_HI_BASE_IDX … #define regIA_PERFCOUNTER0_LO … #define regIA_PERFCOUNTER0_LO_BASE_IDX … #define regIA_PERFCOUNTER0_HI … #define regIA_PERFCOUNTER0_HI_BASE_IDX … #define regIA_PERFCOUNTER1_LO … #define regIA_PERFCOUNTER1_LO_BASE_IDX … #define regIA_PERFCOUNTER1_HI … #define regIA_PERFCOUNTER1_HI_BASE_IDX … #define regIA_PERFCOUNTER2_LO … #define regIA_PERFCOUNTER2_LO_BASE_IDX … #define regIA_PERFCOUNTER2_HI … #define regIA_PERFCOUNTER2_HI_BASE_IDX … #define regIA_PERFCOUNTER3_LO … #define regIA_PERFCOUNTER3_LO_BASE_IDX … #define regIA_PERFCOUNTER3_HI … #define regIA_PERFCOUNTER3_HI_BASE_IDX … #define regVGT_PERFCOUNTER0_LO … #define regVGT_PERFCOUNTER0_LO_BASE_IDX … #define regVGT_PERFCOUNTER0_HI … #define regVGT_PERFCOUNTER0_HI_BASE_IDX … #define regVGT_PERFCOUNTER1_LO … #define regVGT_PERFCOUNTER1_LO_BASE_IDX … #define regVGT_PERFCOUNTER1_HI … #define regVGT_PERFCOUNTER1_HI_BASE_IDX … #define regVGT_PERFCOUNTER2_LO … #define regVGT_PERFCOUNTER2_LO_BASE_IDX … #define regVGT_PERFCOUNTER2_HI … #define regVGT_PERFCOUNTER2_HI_BASE_IDX … #define regVGT_PERFCOUNTER3_LO … #define regVGT_PERFCOUNTER3_LO_BASE_IDX … #define regVGT_PERFCOUNTER3_HI … #define regVGT_PERFCOUNTER3_HI_BASE_IDX … #define regPA_SU_PERFCOUNTER0_LO … #define regPA_SU_PERFCOUNTER0_LO_BASE_IDX … #define regPA_SU_PERFCOUNTER0_HI … #define regPA_SU_PERFCOUNTER0_HI_BASE_IDX … #define regPA_SU_PERFCOUNTER1_LO … #define regPA_SU_PERFCOUNTER1_LO_BASE_IDX … #define regPA_SU_PERFCOUNTER1_HI … #define regPA_SU_PERFCOUNTER1_HI_BASE_IDX … #define regPA_SU_PERFCOUNTER2_LO … #define regPA_SU_PERFCOUNTER2_LO_BASE_IDX … #define regPA_SU_PERFCOUNTER2_HI … #define regPA_SU_PERFCOUNTER2_HI_BASE_IDX … #define regPA_SU_PERFCOUNTER3_LO … #define regPA_SU_PERFCOUNTER3_LO_BASE_IDX … #define regPA_SU_PERFCOUNTER3_HI … #define regPA_SU_PERFCOUNTER3_HI_BASE_IDX … #define regPA_SC_PERFCOUNTER0_LO … #define regPA_SC_PERFCOUNTER0_LO_BASE_IDX … #define regPA_SC_PERFCOUNTER0_HI … #define regPA_SC_PERFCOUNTER0_HI_BASE_IDX … #define regPA_SC_PERFCOUNTER1_LO … #define regPA_SC_PERFCOUNTER1_LO_BASE_IDX … #define regPA_SC_PERFCOUNTER1_HI … #define regPA_SC_PERFCOUNTER1_HI_BASE_IDX … #define regPA_SC_PERFCOUNTER2_LO … #define regPA_SC_PERFCOUNTER2_LO_BASE_IDX … #define regPA_SC_PERFCOUNTER2_HI … #define regPA_SC_PERFCOUNTER2_HI_BASE_IDX … #define regPA_SC_PERFCOUNTER3_LO … #define regPA_SC_PERFCOUNTER3_LO_BASE_IDX … #define regPA_SC_PERFCOUNTER3_HI … #define regPA_SC_PERFCOUNTER3_HI_BASE_IDX … #define regPA_SC_PERFCOUNTER4_LO … #define regPA_SC_PERFCOUNTER4_LO_BASE_IDX … #define regPA_SC_PERFCOUNTER4_HI … #define regPA_SC_PERFCOUNTER4_HI_BASE_IDX … #define regPA_SC_PERFCOUNTER5_LO … #define regPA_SC_PERFCOUNTER5_LO_BASE_IDX … #define regPA_SC_PERFCOUNTER5_HI … #define regPA_SC_PERFCOUNTER5_HI_BASE_IDX … #define regPA_SC_PERFCOUNTER6_LO … #define regPA_SC_PERFCOUNTER6_LO_BASE_IDX … #define regPA_SC_PERFCOUNTER6_HI … #define regPA_SC_PERFCOUNTER6_HI_BASE_IDX … #define regPA_SC_PERFCOUNTER7_LO … #define regPA_SC_PERFCOUNTER7_LO_BASE_IDX … #define regPA_SC_PERFCOUNTER7_HI … #define regPA_SC_PERFCOUNTER7_HI_BASE_IDX … #define regSPI_PERFCOUNTER0_HI … #define regSPI_PERFCOUNTER0_HI_BASE_IDX … #define regSPI_PERFCOUNTER0_LO … #define regSPI_PERFCOUNTER0_LO_BASE_IDX … #define regSPI_PERFCOUNTER1_HI … #define regSPI_PERFCOUNTER1_HI_BASE_IDX … #define regSPI_PERFCOUNTER1_LO … #define regSPI_PERFCOUNTER1_LO_BASE_IDX … #define regSPI_PERFCOUNTER2_HI … #define regSPI_PERFCOUNTER2_HI_BASE_IDX … #define regSPI_PERFCOUNTER2_LO … #define regSPI_PERFCOUNTER2_LO_BASE_IDX … #define regSPI_PERFCOUNTER3_HI … #define regSPI_PERFCOUNTER3_HI_BASE_IDX … #define regSPI_PERFCOUNTER3_LO … #define regSPI_PERFCOUNTER3_LO_BASE_IDX … #define regSPI_PERFCOUNTER4_HI … #define regSPI_PERFCOUNTER4_HI_BASE_IDX … #define regSPI_PERFCOUNTER4_LO … #define regSPI_PERFCOUNTER4_LO_BASE_IDX … #define regSPI_PERFCOUNTER5_HI … #define regSPI_PERFCOUNTER5_HI_BASE_IDX … #define regSPI_PERFCOUNTER5_LO … #define regSPI_PERFCOUNTER5_LO_BASE_IDX … #define regSQ_PERFCOUNTER0_LO … #define regSQ_PERFCOUNTER0_LO_BASE_IDX … #define regSQ_PERFCOUNTER0_HI … #define regSQ_PERFCOUNTER0_HI_BASE_IDX … #define regSQ_PERFCOUNTER1_LO … #define regSQ_PERFCOUNTER1_LO_BASE_IDX … #define regSQ_PERFCOUNTER1_HI … #define regSQ_PERFCOUNTER1_HI_BASE_IDX … #define regSQ_PERFCOUNTER2_LO … #define regSQ_PERFCOUNTER2_LO_BASE_IDX … #define regSQ_PERFCOUNTER2_HI … #define regSQ_PERFCOUNTER2_HI_BASE_IDX … #define regSQ_PERFCOUNTER3_LO … #define regSQ_PERFCOUNTER3_LO_BASE_IDX … #define regSQ_PERFCOUNTER3_HI … #define regSQ_PERFCOUNTER3_HI_BASE_IDX … #define regSQ_PERFCOUNTER4_LO … #define regSQ_PERFCOUNTER4_LO_BASE_IDX … #define regSQ_PERFCOUNTER4_HI … #define regSQ_PERFCOUNTER4_HI_BASE_IDX … #define regSQ_PERFCOUNTER5_LO … #define regSQ_PERFCOUNTER5_LO_BASE_IDX … #define regSQ_PERFCOUNTER5_HI … #define regSQ_PERFCOUNTER5_HI_BASE_IDX … #define regSQ_PERFCOUNTER6_LO … #define regSQ_PERFCOUNTER6_LO_BASE_IDX … #define regSQ_PERFCOUNTER6_HI … #define regSQ_PERFCOUNTER6_HI_BASE_IDX … #define regSQ_PERFCOUNTER7_LO … #define regSQ_PERFCOUNTER7_LO_BASE_IDX … #define regSQ_PERFCOUNTER7_HI … #define regSQ_PERFCOUNTER7_HI_BASE_IDX … #define regSQ_PERFCOUNTER8_LO … #define regSQ_PERFCOUNTER8_LO_BASE_IDX … #define regSQ_PERFCOUNTER8_HI … #define regSQ_PERFCOUNTER8_HI_BASE_IDX … #define regSQ_PERFCOUNTER9_LO … #define regSQ_PERFCOUNTER9_LO_BASE_IDX … #define regSQ_PERFCOUNTER9_HI … #define regSQ_PERFCOUNTER9_HI_BASE_IDX … #define regSQ_PERFCOUNTER10_LO … #define regSQ_PERFCOUNTER10_LO_BASE_IDX … #define regSQ_PERFCOUNTER10_HI … #define regSQ_PERFCOUNTER10_HI_BASE_IDX … #define regSQ_PERFCOUNTER11_LO … #define regSQ_PERFCOUNTER11_LO_BASE_IDX … #define regSQ_PERFCOUNTER11_HI … #define regSQ_PERFCOUNTER11_HI_BASE_IDX … #define regSQ_PERFCOUNTER12_LO … #define regSQ_PERFCOUNTER12_LO_BASE_IDX … #define regSQ_PERFCOUNTER12_HI … #define regSQ_PERFCOUNTER12_HI_BASE_IDX … #define regSQ_PERFCOUNTER13_LO … #define regSQ_PERFCOUNTER13_LO_BASE_IDX … #define regSQ_PERFCOUNTER13_HI … #define regSQ_PERFCOUNTER13_HI_BASE_IDX … #define regSQ_PERFCOUNTER14_LO … #define regSQ_PERFCOUNTER14_LO_BASE_IDX … #define regSQ_PERFCOUNTER14_HI … #define regSQ_PERFCOUNTER14_HI_BASE_IDX … #define regSQ_PERFCOUNTER15_LO … #define regSQ_PERFCOUNTER15_LO_BASE_IDX … #define regSQ_PERFCOUNTER15_HI … #define regSQ_PERFCOUNTER15_HI_BASE_IDX … #define regSX_PERFCOUNTER0_LO … #define regSX_PERFCOUNTER0_LO_BASE_IDX … #define regSX_PERFCOUNTER0_HI … #define regSX_PERFCOUNTER0_HI_BASE_IDX … #define regSX_PERFCOUNTER1_LO … #define regSX_PERFCOUNTER1_LO_BASE_IDX … #define regSX_PERFCOUNTER1_HI … #define regSX_PERFCOUNTER1_HI_BASE_IDX … #define regSX_PERFCOUNTER2_LO … #define regSX_PERFCOUNTER2_LO_BASE_IDX … #define regSX_PERFCOUNTER2_HI … #define regSX_PERFCOUNTER2_HI_BASE_IDX … #define regSX_PERFCOUNTER3_LO … #define regSX_PERFCOUNTER3_LO_BASE_IDX … #define regSX_PERFCOUNTER3_HI … #define regSX_PERFCOUNTER3_HI_BASE_IDX … #define regGDS_PERFCOUNTER0_LO … #define regGDS_PERFCOUNTER0_LO_BASE_IDX … #define regGDS_PERFCOUNTER0_HI … #define regGDS_PERFCOUNTER0_HI_BASE_IDX … #define regGDS_PERFCOUNTER1_LO … #define regGDS_PERFCOUNTER1_LO_BASE_IDX … #define regGDS_PERFCOUNTER1_HI … #define regGDS_PERFCOUNTER1_HI_BASE_IDX … #define regGDS_PERFCOUNTER2_LO … #define regGDS_PERFCOUNTER2_LO_BASE_IDX … #define regGDS_PERFCOUNTER2_HI … #define regGDS_PERFCOUNTER2_HI_BASE_IDX … #define regGDS_PERFCOUNTER3_LO … #define regGDS_PERFCOUNTER3_LO_BASE_IDX … #define regGDS_PERFCOUNTER3_HI … #define regGDS_PERFCOUNTER3_HI_BASE_IDX … #define regTA_PERFCOUNTER0_LO … #define regTA_PERFCOUNTER0_LO_BASE_IDX … #define regTA_PERFCOUNTER0_HI … #define regTA_PERFCOUNTER0_HI_BASE_IDX … #define regTA_PERFCOUNTER1_LO … #define regTA_PERFCOUNTER1_LO_BASE_IDX … #define regTA_PERFCOUNTER1_HI … #define regTA_PERFCOUNTER1_HI_BASE_IDX … #define regTD_PERFCOUNTER0_LO … #define regTD_PERFCOUNTER0_LO_BASE_IDX … #define regTD_PERFCOUNTER0_HI … #define regTD_PERFCOUNTER0_HI_BASE_IDX … #define regTD_PERFCOUNTER1_LO … #define regTD_PERFCOUNTER1_LO_BASE_IDX … #define regTD_PERFCOUNTER1_HI … #define regTD_PERFCOUNTER1_HI_BASE_IDX … #define regTCP_PERFCOUNTER0_LO … #define regTCP_PERFCOUNTER0_LO_BASE_IDX … #define regTCP_PERFCOUNTER0_HI … #define regTCP_PERFCOUNTER0_HI_BASE_IDX … #define regTCP_PERFCOUNTER1_LO … #define regTCP_PERFCOUNTER1_LO_BASE_IDX … #define regTCP_PERFCOUNTER1_HI … #define regTCP_PERFCOUNTER1_HI_BASE_IDX … #define regTCP_PERFCOUNTER2_LO … #define regTCP_PERFCOUNTER2_LO_BASE_IDX … #define regTCP_PERFCOUNTER2_HI … #define regTCP_PERFCOUNTER2_HI_BASE_IDX … #define regTCP_PERFCOUNTER3_LO … #define regTCP_PERFCOUNTER3_LO_BASE_IDX … #define regTCP_PERFCOUNTER3_HI … #define regTCP_PERFCOUNTER3_HI_BASE_IDX … #define regTCC_PERFCOUNTER0_LO … #define regTCC_PERFCOUNTER0_LO_BASE_IDX … #define regTCC_PERFCOUNTER0_HI … #define regTCC_PERFCOUNTER0_HI_BASE_IDX … #define regTCC_PERFCOUNTER1_LO … #define regTCC_PERFCOUNTER1_LO_BASE_IDX … #define regTCC_PERFCOUNTER1_HI … #define regTCC_PERFCOUNTER1_HI_BASE_IDX … #define regTCC_PERFCOUNTER2_LO … #define regTCC_PERFCOUNTER2_LO_BASE_IDX … #define regTCC_PERFCOUNTER2_HI … #define regTCC_PERFCOUNTER2_HI_BASE_IDX … #define regTCC_PERFCOUNTER3_LO … #define regTCC_PERFCOUNTER3_LO_BASE_IDX … #define regTCC_PERFCOUNTER3_HI … #define regTCC_PERFCOUNTER3_HI_BASE_IDX … #define regTCA_PERFCOUNTER0_LO … #define regTCA_PERFCOUNTER0_LO_BASE_IDX … #define regTCA_PERFCOUNTER0_HI … #define regTCA_PERFCOUNTER0_HI_BASE_IDX … #define regTCA_PERFCOUNTER1_LO … #define regTCA_PERFCOUNTER1_LO_BASE_IDX … #define regTCA_PERFCOUNTER1_HI … #define regTCA_PERFCOUNTER1_HI_BASE_IDX … #define regTCA_PERFCOUNTER2_LO … #define regTCA_PERFCOUNTER2_LO_BASE_IDX … #define regTCA_PERFCOUNTER2_HI … #define regTCA_PERFCOUNTER2_HI_BASE_IDX … #define regTCA_PERFCOUNTER3_LO … #define regTCA_PERFCOUNTER3_LO_BASE_IDX … #define regTCA_PERFCOUNTER3_HI … #define regTCA_PERFCOUNTER3_HI_BASE_IDX … #define regCB_PERFCOUNTER0_LO … #define regCB_PERFCOUNTER0_LO_BASE_IDX … #define regCB_PERFCOUNTER0_HI … #define regCB_PERFCOUNTER0_HI_BASE_IDX … #define regCB_PERFCOUNTER1_LO … #define regCB_PERFCOUNTER1_LO_BASE_IDX … #define regCB_PERFCOUNTER1_HI … #define regCB_PERFCOUNTER1_HI_BASE_IDX … #define regCB_PERFCOUNTER2_LO … #define regCB_PERFCOUNTER2_LO_BASE_IDX … #define regCB_PERFCOUNTER2_HI … #define regCB_PERFCOUNTER2_HI_BASE_IDX … #define regCB_PERFCOUNTER3_LO … #define regCB_PERFCOUNTER3_LO_BASE_IDX … #define regCB_PERFCOUNTER3_HI … #define regCB_PERFCOUNTER3_HI_BASE_IDX … #define regDB_PERFCOUNTER0_LO … #define regDB_PERFCOUNTER0_LO_BASE_IDX … #define regDB_PERFCOUNTER0_HI … #define regDB_PERFCOUNTER0_HI_BASE_IDX … #define regDB_PERFCOUNTER1_LO … #define regDB_PERFCOUNTER1_LO_BASE_IDX … #define regDB_PERFCOUNTER1_HI … #define regDB_PERFCOUNTER1_HI_BASE_IDX … #define regDB_PERFCOUNTER2_LO … #define regDB_PERFCOUNTER2_LO_BASE_IDX … #define regDB_PERFCOUNTER2_HI … #define regDB_PERFCOUNTER2_HI_BASE_IDX … #define regDB_PERFCOUNTER3_LO … #define regDB_PERFCOUNTER3_LO_BASE_IDX … #define regDB_PERFCOUNTER3_HI … #define regDB_PERFCOUNTER3_HI_BASE_IDX … #define regRLC_PERFCOUNTER0_LO … #define regRLC_PERFCOUNTER0_LO_BASE_IDX … #define regRLC_PERFCOUNTER0_HI … #define regRLC_PERFCOUNTER0_HI_BASE_IDX … #define regRLC_PERFCOUNTER1_LO … #define regRLC_PERFCOUNTER1_LO_BASE_IDX … #define regRLC_PERFCOUNTER1_HI … #define regRLC_PERFCOUNTER1_HI_BASE_IDX … #define regRMI_PERFCOUNTER0_LO … #define regRMI_PERFCOUNTER0_LO_BASE_IDX … #define regRMI_PERFCOUNTER0_HI … #define regRMI_PERFCOUNTER0_HI_BASE_IDX … #define regRMI_PERFCOUNTER1_LO … #define regRMI_PERFCOUNTER1_LO_BASE_IDX … #define regRMI_PERFCOUNTER1_HI … #define regRMI_PERFCOUNTER1_HI_BASE_IDX … #define regRMI_PERFCOUNTER2_LO … #define regRMI_PERFCOUNTER2_LO_BASE_IDX … #define regRMI_PERFCOUNTER2_HI … #define regRMI_PERFCOUNTER2_HI_BASE_IDX … #define regRMI_PERFCOUNTER3_LO … #define regRMI_PERFCOUNTER3_LO_BASE_IDX … #define regRMI_PERFCOUNTER3_HI … #define regRMI_PERFCOUNTER3_HI_BASE_IDX … // addressBlock: xcd0_gc_utcl2_atcl2pfcntrdec // base address: 0x35400 #define regATC_L2_PERFCOUNTER_LO … #define regATC_L2_PERFCOUNTER_LO_BASE_IDX … #define regATC_L2_PERFCOUNTER_HI … #define regATC_L2_PERFCOUNTER_HI_BASE_IDX … // addressBlock: xcd0_gc_utcl2_vml2prdec // base address: 0x35408 #define regMC_VM_L2_PERFCOUNTER_LO … #define regMC_VM_L2_PERFCOUNTER_LO_BASE_IDX … #define regMC_VM_L2_PERFCOUNTER_HI … #define regMC_VM_L2_PERFCOUNTER_HI_BASE_IDX … // addressBlock: xcd0_gc_utcl2_l2tlbprdec // base address: 0x35448 #define regL2TLB_PERFCOUNTER_LO … #define regL2TLB_PERFCOUNTER_LO_BASE_IDX … #define regL2TLB_PERFCOUNTER_HI … #define regL2TLB_PERFCOUNTER_HI_BASE_IDX … // addressBlock: xcd0_gc_perfsdec // base address: 0x36000 #define regCPG_PERFCOUNTER1_SELECT … #define regCPG_PERFCOUNTER1_SELECT_BASE_IDX … #define regCPG_PERFCOUNTER0_SELECT1 … #define regCPG_PERFCOUNTER0_SELECT1_BASE_IDX … #define regCPG_PERFCOUNTER0_SELECT … #define regCPG_PERFCOUNTER0_SELECT_BASE_IDX … #define regCPC_PERFCOUNTER1_SELECT … #define regCPC_PERFCOUNTER1_SELECT_BASE_IDX … #define regCPC_PERFCOUNTER0_SELECT1 … #define regCPC_PERFCOUNTER0_SELECT1_BASE_IDX … #define regCPF_PERFCOUNTER1_SELECT … #define regCPF_PERFCOUNTER1_SELECT_BASE_IDX … #define regCPF_PERFCOUNTER0_SELECT1 … #define regCPF_PERFCOUNTER0_SELECT1_BASE_IDX … #define regCPF_PERFCOUNTER0_SELECT … #define regCPF_PERFCOUNTER0_SELECT_BASE_IDX … #define regCP_PERFMON_CNTL … #define regCP_PERFMON_CNTL_BASE_IDX … #define regCPC_PERFCOUNTER0_SELECT … #define regCPC_PERFCOUNTER0_SELECT_BASE_IDX … #define regCPF_TC_PERF_COUNTER_WINDOW_SELECT … #define regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX … #define regCPG_TC_PERF_COUNTER_WINDOW_SELECT … #define regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX … #define regCPF_LATENCY_STATS_SELECT … #define regCPF_LATENCY_STATS_SELECT_BASE_IDX … #define regCPG_LATENCY_STATS_SELECT … #define regCPG_LATENCY_STATS_SELECT_BASE_IDX … #define regCPC_LATENCY_STATS_SELECT … #define regCPC_LATENCY_STATS_SELECT_BASE_IDX … #define regCP_DRAW_OBJECT … #define regCP_DRAW_OBJECT_BASE_IDX … #define regCP_DRAW_OBJECT_COUNTER … #define regCP_DRAW_OBJECT_COUNTER_BASE_IDX … #define regCP_DRAW_WINDOW_MASK_HI … #define regCP_DRAW_WINDOW_MASK_HI_BASE_IDX … #define regCP_DRAW_WINDOW_HI … #define regCP_DRAW_WINDOW_HI_BASE_IDX … #define regCP_DRAW_WINDOW_LO … #define regCP_DRAW_WINDOW_LO_BASE_IDX … #define regCP_DRAW_WINDOW_CNTL … #define regCP_DRAW_WINDOW_CNTL_BASE_IDX … #define regGRBM_PERFCOUNTER0_SELECT … #define regGRBM_PERFCOUNTER0_SELECT_BASE_IDX … #define regGRBM_PERFCOUNTER1_SELECT … #define regGRBM_PERFCOUNTER1_SELECT_BASE_IDX … #define regGRBM_SE0_PERFCOUNTER_SELECT … #define regGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX … #define regGRBM_SE1_PERFCOUNTER_SELECT … #define regGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX … #define regGRBM_SE2_PERFCOUNTER_SELECT … #define regGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX … #define regGRBM_SE3_PERFCOUNTER_SELECT … #define regGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX … #define regWD_PERFCOUNTER0_SELECT … #define regWD_PERFCOUNTER0_SELECT_BASE_IDX … #define regWD_PERFCOUNTER1_SELECT … #define regWD_PERFCOUNTER1_SELECT_BASE_IDX … #define regWD_PERFCOUNTER2_SELECT … #define regWD_PERFCOUNTER2_SELECT_BASE_IDX … #define regWD_PERFCOUNTER3_SELECT … #define regWD_PERFCOUNTER3_SELECT_BASE_IDX … #define regIA_PERFCOUNTER0_SELECT … #define regIA_PERFCOUNTER0_SELECT_BASE_IDX … #define regIA_PERFCOUNTER1_SELECT … #define regIA_PERFCOUNTER1_SELECT_BASE_IDX … #define regIA_PERFCOUNTER2_SELECT … #define regIA_PERFCOUNTER2_SELECT_BASE_IDX … #define regIA_PERFCOUNTER3_SELECT … #define regIA_PERFCOUNTER3_SELECT_BASE_IDX … #define regIA_PERFCOUNTER0_SELECT1 … #define regIA_PERFCOUNTER0_SELECT1_BASE_IDX … #define regVGT_PERFCOUNTER0_SELECT … #define regVGT_PERFCOUNTER0_SELECT_BASE_IDX … #define regVGT_PERFCOUNTER1_SELECT … #define regVGT_PERFCOUNTER1_SELECT_BASE_IDX … #define regVGT_PERFCOUNTER2_SELECT … #define regVGT_PERFCOUNTER2_SELECT_BASE_IDX … #define regVGT_PERFCOUNTER3_SELECT … #define regVGT_PERFCOUNTER3_SELECT_BASE_IDX … #define regVGT_PERFCOUNTER0_SELECT1 … #define regVGT_PERFCOUNTER0_SELECT1_BASE_IDX … #define regVGT_PERFCOUNTER1_SELECT1 … #define regVGT_PERFCOUNTER1_SELECT1_BASE_IDX … #define regVGT_PERFCOUNTER_SEID_MASK … #define regVGT_PERFCOUNTER_SEID_MASK_BASE_IDX … #define regPA_SU_PERFCOUNTER0_SELECT … #define regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX … #define regPA_SU_PERFCOUNTER0_SELECT1 … #define regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX … #define regPA_SU_PERFCOUNTER1_SELECT … #define regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX … #define regPA_SU_PERFCOUNTER1_SELECT1 … #define regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX … #define regPA_SU_PERFCOUNTER2_SELECT … #define regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX … #define regPA_SU_PERFCOUNTER3_SELECT … #define regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX … #define regPA_SC_PERFCOUNTER0_SELECT … #define regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX … #define regPA_SC_PERFCOUNTER0_SELECT1 … #define regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX … #define regPA_SC_PERFCOUNTER1_SELECT … #define regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX … #define regPA_SC_PERFCOUNTER2_SELECT … #define regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX … #define regPA_SC_PERFCOUNTER3_SELECT … #define regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX … #define regPA_SC_PERFCOUNTER4_SELECT … #define regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX … #define regPA_SC_PERFCOUNTER5_SELECT … #define regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX … #define regPA_SC_PERFCOUNTER6_SELECT … #define regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX … #define regPA_SC_PERFCOUNTER7_SELECT … #define regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX … #define regSPI_PERFCOUNTER0_SELECT … #define regSPI_PERFCOUNTER0_SELECT_BASE_IDX … #define regSPI_PERFCOUNTER1_SELECT … #define regSPI_PERFCOUNTER1_SELECT_BASE_IDX … #define regSPI_PERFCOUNTER2_SELECT … #define regSPI_PERFCOUNTER2_SELECT_BASE_IDX … #define regSPI_PERFCOUNTER3_SELECT … #define regSPI_PERFCOUNTER3_SELECT_BASE_IDX … #define regSPI_PERFCOUNTER0_SELECT1 … #define regSPI_PERFCOUNTER0_SELECT1_BASE_IDX … #define regSPI_PERFCOUNTER1_SELECT1 … #define regSPI_PERFCOUNTER1_SELECT1_BASE_IDX … #define regSPI_PERFCOUNTER2_SELECT1 … #define regSPI_PERFCOUNTER2_SELECT1_BASE_IDX … #define regSPI_PERFCOUNTER3_SELECT1 … #define regSPI_PERFCOUNTER3_SELECT1_BASE_IDX … #define regSPI_PERFCOUNTER4_SELECT … #define regSPI_PERFCOUNTER4_SELECT_BASE_IDX … #define regSPI_PERFCOUNTER5_SELECT … #define regSPI_PERFCOUNTER5_SELECT_BASE_IDX … #define regSPI_PERFCOUNTER_BINS … #define regSPI_PERFCOUNTER_BINS_BASE_IDX … #define regSQ_PERFCOUNTER0_SELECT … #define regSQ_PERFCOUNTER0_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER1_SELECT … #define regSQ_PERFCOUNTER1_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER2_SELECT … #define regSQ_PERFCOUNTER2_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER3_SELECT … #define regSQ_PERFCOUNTER3_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER4_SELECT … #define regSQ_PERFCOUNTER4_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER5_SELECT … #define regSQ_PERFCOUNTER5_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER6_SELECT … #define regSQ_PERFCOUNTER6_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER7_SELECT … #define regSQ_PERFCOUNTER7_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER8_SELECT … #define regSQ_PERFCOUNTER8_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER9_SELECT … #define regSQ_PERFCOUNTER9_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER10_SELECT … #define regSQ_PERFCOUNTER10_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER11_SELECT … #define regSQ_PERFCOUNTER11_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER12_SELECT … #define regSQ_PERFCOUNTER12_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER13_SELECT … #define regSQ_PERFCOUNTER13_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER14_SELECT … #define regSQ_PERFCOUNTER14_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER15_SELECT … #define regSQ_PERFCOUNTER15_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER_CTRL … #define regSQ_PERFCOUNTER_CTRL_BASE_IDX … #define regSQ_PERFCOUNTER_MASK … #define regSQ_PERFCOUNTER_MASK_BASE_IDX … #define regSQ_PERFCOUNTER_CTRL2 … #define regSQ_PERFCOUNTER_CTRL2_BASE_IDX … #define regSX_PERFCOUNTER0_SELECT … #define regSX_PERFCOUNTER0_SELECT_BASE_IDX … #define regSX_PERFCOUNTER1_SELECT … #define regSX_PERFCOUNTER1_SELECT_BASE_IDX … #define regSX_PERFCOUNTER2_SELECT … #define regSX_PERFCOUNTER2_SELECT_BASE_IDX … #define regSX_PERFCOUNTER3_SELECT … #define regSX_PERFCOUNTER3_SELECT_BASE_IDX … #define regSX_PERFCOUNTER0_SELECT1 … #define regSX_PERFCOUNTER0_SELECT1_BASE_IDX … #define regSX_PERFCOUNTER1_SELECT1 … #define regSX_PERFCOUNTER1_SELECT1_BASE_IDX … #define regGDS_PERFCOUNTER0_SELECT … #define regGDS_PERFCOUNTER0_SELECT_BASE_IDX … #define regGDS_PERFCOUNTER1_SELECT … #define regGDS_PERFCOUNTER1_SELECT_BASE_IDX … #define regGDS_PERFCOUNTER2_SELECT … #define regGDS_PERFCOUNTER2_SELECT_BASE_IDX … #define regGDS_PERFCOUNTER3_SELECT … #define regGDS_PERFCOUNTER3_SELECT_BASE_IDX … #define regGDS_PERFCOUNTER0_SELECT1 … #define regGDS_PERFCOUNTER0_SELECT1_BASE_IDX … #define regTA_PERFCOUNTER0_SELECT … #define regTA_PERFCOUNTER0_SELECT_BASE_IDX … #define regTA_PERFCOUNTER0_SELECT1 … #define regTA_PERFCOUNTER0_SELECT1_BASE_IDX … #define regTA_PERFCOUNTER1_SELECT … #define regTA_PERFCOUNTER1_SELECT_BASE_IDX … #define regTD_PERFCOUNTER0_SELECT … #define regTD_PERFCOUNTER0_SELECT_BASE_IDX … #define regTD_PERFCOUNTER0_SELECT1 … #define regTD_PERFCOUNTER0_SELECT1_BASE_IDX … #define regTD_PERFCOUNTER1_SELECT … #define regTD_PERFCOUNTER1_SELECT_BASE_IDX … #define regTCP_PERFCOUNTER0_SELECT … #define regTCP_PERFCOUNTER0_SELECT_BASE_IDX … #define regTCP_PERFCOUNTER0_SELECT1 … #define regTCP_PERFCOUNTER0_SELECT1_BASE_IDX … #define regTCP_PERFCOUNTER1_SELECT … #define regTCP_PERFCOUNTER1_SELECT_BASE_IDX … #define regTCP_PERFCOUNTER1_SELECT1 … #define regTCP_PERFCOUNTER1_SELECT1_BASE_IDX … #define regTCP_PERFCOUNTER2_SELECT … #define regTCP_PERFCOUNTER2_SELECT_BASE_IDX … #define regTCP_PERFCOUNTER3_SELECT … #define regTCP_PERFCOUNTER3_SELECT_BASE_IDX … #define regTCC_PERFCOUNTER0_SELECT … #define regTCC_PERFCOUNTER0_SELECT_BASE_IDX … #define regTCC_PERFCOUNTER0_SELECT1 … #define regTCC_PERFCOUNTER0_SELECT1_BASE_IDX … #define regTCC_PERFCOUNTER1_SELECT … #define regTCC_PERFCOUNTER1_SELECT_BASE_IDX … #define regTCC_PERFCOUNTER1_SELECT1 … #define regTCC_PERFCOUNTER1_SELECT1_BASE_IDX … #define regTCC_PERFCOUNTER2_SELECT … #define regTCC_PERFCOUNTER2_SELECT_BASE_IDX … #define regTCC_PERFCOUNTER3_SELECT … #define regTCC_PERFCOUNTER3_SELECT_BASE_IDX … #define regTCA_PERFCOUNTER0_SELECT … #define regTCA_PERFCOUNTER0_SELECT_BASE_IDX … #define regTCA_PERFCOUNTER0_SELECT1 … #define regTCA_PERFCOUNTER0_SELECT1_BASE_IDX … #define regTCA_PERFCOUNTER1_SELECT … #define regTCA_PERFCOUNTER1_SELECT_BASE_IDX … #define regTCA_PERFCOUNTER1_SELECT1 … #define regTCA_PERFCOUNTER1_SELECT1_BASE_IDX … #define regTCA_PERFCOUNTER2_SELECT … #define regTCA_PERFCOUNTER2_SELECT_BASE_IDX … #define regTCA_PERFCOUNTER3_SELECT … #define regTCA_PERFCOUNTER3_SELECT_BASE_IDX … #define regCB_PERFCOUNTER_FILTER … #define regCB_PERFCOUNTER_FILTER_BASE_IDX … #define regCB_PERFCOUNTER0_SELECT … #define regCB_PERFCOUNTER0_SELECT_BASE_IDX … #define regCB_PERFCOUNTER0_SELECT1 … #define regCB_PERFCOUNTER0_SELECT1_BASE_IDX … #define regCB_PERFCOUNTER1_SELECT … #define regCB_PERFCOUNTER1_SELECT_BASE_IDX … #define regCB_PERFCOUNTER2_SELECT … #define regCB_PERFCOUNTER2_SELECT_BASE_IDX … #define regCB_PERFCOUNTER3_SELECT … #define regCB_PERFCOUNTER3_SELECT_BASE_IDX … #define regDB_PERFCOUNTER0_SELECT … #define regDB_PERFCOUNTER0_SELECT_BASE_IDX … #define regDB_PERFCOUNTER0_SELECT1 … #define regDB_PERFCOUNTER0_SELECT1_BASE_IDX … #define regDB_PERFCOUNTER1_SELECT … #define regDB_PERFCOUNTER1_SELECT_BASE_IDX … #define regDB_PERFCOUNTER1_SELECT1 … #define regDB_PERFCOUNTER1_SELECT1_BASE_IDX … #define regDB_PERFCOUNTER2_SELECT … #define regDB_PERFCOUNTER2_SELECT_BASE_IDX … #define regDB_PERFCOUNTER3_SELECT … #define regDB_PERFCOUNTER3_SELECT_BASE_IDX … #define regRLC_SPM_PERFMON_CNTL … #define regRLC_SPM_PERFMON_CNTL_BASE_IDX … #define regRLC_SPM_PERFMON_RING_BASE_LO … #define regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX … #define regRLC_SPM_PERFMON_RING_BASE_HI … #define regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX … #define regRLC_SPM_PERFMON_RING_SIZE … #define regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX … #define regRLC_SPM_PERFMON_SEGMENT_SIZE … #define regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX … #define regRLC_SPM_SE_MUXSEL_ADDR … #define regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX … #define regRLC_SPM_SE_MUXSEL_DATA … #define regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX … #define regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY … #define regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY_BASE_IDX … #define regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY … #define regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY_BASE_IDX … #define regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY … #define regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY_BASE_IDX … #define regRLC_SPM_CB_PERFMON_SAMPLE_DELAY … #define regRLC_SPM_CB_PERFMON_SAMPLE_DELAY_BASE_IDX … #define regRLC_SPM_DB_PERFMON_SAMPLE_DELAY … #define regRLC_SPM_DB_PERFMON_SAMPLE_DELAY_BASE_IDX … #define regRLC_SPM_PA_PERFMON_SAMPLE_DELAY … #define regRLC_SPM_PA_PERFMON_SAMPLE_DELAY_BASE_IDX … #define regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY … #define regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY_BASE_IDX … #define regRLC_SPM_IA_PERFMON_SAMPLE_DELAY … #define regRLC_SPM_IA_PERFMON_SAMPLE_DELAY_BASE_IDX … #define regRLC_SPM_SC_PERFMON_SAMPLE_DELAY … #define regRLC_SPM_SC_PERFMON_SAMPLE_DELAY_BASE_IDX … #define regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY … #define regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY_BASE_IDX … #define regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY … #define regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY_BASE_IDX … #define regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY … #define regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY_BASE_IDX … #define regRLC_SPM_TA_PERFMON_SAMPLE_DELAY … #define regRLC_SPM_TA_PERFMON_SAMPLE_DELAY_BASE_IDX … #define regRLC_SPM_TD_PERFMON_SAMPLE_DELAY … #define regRLC_SPM_TD_PERFMON_SAMPLE_DELAY_BASE_IDX … #define regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY … #define regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY_BASE_IDX … #define regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY … #define regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY_BASE_IDX … #define regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY … #define regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY_BASE_IDX … #define regRLC_SPM_SX_PERFMON_SAMPLE_DELAY … #define regRLC_SPM_SX_PERFMON_SAMPLE_DELAY_BASE_IDX … #define regRLC_SPM_GLOBAL_MUXSEL_ADDR … #define regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX … #define regRLC_SPM_GLOBAL_MUXSEL_DATA … #define regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX … #define regRLC_SPM_RING_RDPTR … #define regRLC_SPM_RING_RDPTR_BASE_IDX … #define regRLC_SPM_SEGMENT_THRESHOLD … #define regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX … #define regRLC_SPM_RMI_PERFMON_SAMPLE_DELAY … #define regRLC_SPM_RMI_PERFMON_SAMPLE_DELAY_BASE_IDX … #define regRLC_SPM_PERFMON_SAMPLE_DELAY_MAX … #define regRLC_SPM_PERFMON_SAMPLE_DELAY_MAX_BASE_IDX … #define regRLC_PERFMON_CNTL … #define regRLC_PERFMON_CNTL_BASE_IDX … #define regRLC_PERFCOUNTER0_SELECT … #define regRLC_PERFCOUNTER0_SELECT_BASE_IDX … #define regRLC_PERFCOUNTER1_SELECT … #define regRLC_PERFCOUNTER1_SELECT_BASE_IDX … #define regRLC_GPU_IOV_PERF_CNT_CNTL … #define regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX … #define regRLC_GPU_IOV_PERF_CNT_WR_ADDR … #define regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX … #define regRLC_GPU_IOV_PERF_CNT_WR_DATA … #define regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX … #define regRLC_GPU_IOV_PERF_CNT_RD_ADDR … #define regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX … #define regRLC_GPU_IOV_PERF_CNT_RD_DATA … #define regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX … #define regRMI_PERFCOUNTER0_SELECT … #define regRMI_PERFCOUNTER0_SELECT_BASE_IDX … #define regRMI_PERFCOUNTER0_SELECT1 … #define regRMI_PERFCOUNTER0_SELECT1_BASE_IDX … #define regRMI_PERFCOUNTER1_SELECT … #define regRMI_PERFCOUNTER1_SELECT_BASE_IDX … #define regRMI_PERFCOUNTER2_SELECT … #define regRMI_PERFCOUNTER2_SELECT_BASE_IDX … #define regRMI_PERFCOUNTER2_SELECT1 … #define regRMI_PERFCOUNTER2_SELECT1_BASE_IDX … #define regRMI_PERFCOUNTER3_SELECT … #define regRMI_PERFCOUNTER3_SELECT_BASE_IDX … #define regRMI_PERF_COUNTER_CNTL … #define regRMI_PERF_COUNTER_CNTL_BASE_IDX … // addressBlock: xcd0_gc_utcl2_atcl2pfcntldec // base address: 0x37500 #define regATC_L2_PERFCOUNTER0_CFG … #define regATC_L2_PERFCOUNTER0_CFG_BASE_IDX … #define regATC_L2_PERFCOUNTER1_CFG … #define regATC_L2_PERFCOUNTER1_CFG_BASE_IDX … #define regATC_L2_PERFCOUNTER_RSLT_CNTL … #define regATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: xcd0_gc_utcl2_vml2pldec // base address: 0x37518 #define regMC_VM_L2_PERFCOUNTER0_CFG … #define regMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX … #define regMC_VM_L2_PERFCOUNTER1_CFG … #define regMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX … #define regMC_VM_L2_PERFCOUNTER2_CFG … #define regMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX … #define regMC_VM_L2_PERFCOUNTER3_CFG … #define regMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX … #define regMC_VM_L2_PERFCOUNTER4_CFG … #define regMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX … #define regMC_VM_L2_PERFCOUNTER5_CFG … #define regMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX … #define regMC_VM_L2_PERFCOUNTER6_CFG … #define regMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX … #define regMC_VM_L2_PERFCOUNTER7_CFG … #define regMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX … #define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL … #define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: xcd0_gc_utcl2_l2tlbpldec // base address: 0x37578 #define regL2TLB_PERFCOUNTER0_CFG … #define regL2TLB_PERFCOUNTER0_CFG_BASE_IDX … #define regL2TLB_PERFCOUNTER1_CFG … #define regL2TLB_PERFCOUNTER1_CFG_BASE_IDX … #define regL2TLB_PERFCOUNTER2_CFG … #define regL2TLB_PERFCOUNTER2_CFG_BASE_IDX … #define regL2TLB_PERFCOUNTER3_CFG … #define regL2TLB_PERFCOUNTER3_CFG_BASE_IDX … #define regL2TLB_PERFCOUNTER_RSLT_CNTL … #define regL2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: xcd0_gc_gdflldec // base address: 0x3a000 #define regGDFLL_EDC_HYSTERESIS_CNTL … #define regGDFLL_EDC_HYSTERESIS_CNTL_BASE_IDX … #define regGDFLL_EDC_HYSTERESIS_STAT … #define regGDFLL_EDC_HYSTERESIS_STAT_BASE_IDX … // addressBlock: xcd0_gc_rlcpdec // base address: 0x3b000 #define regRLC_CNTL … #define regRLC_CNTL_BASE_IDX … #define regRLC_CGCG_CGLS_CTRL_2 … #define regRLC_CGCG_CGLS_CTRL_2_BASE_IDX … #define regRLC_STAT … #define regRLC_STAT_BASE_IDX … #define regRLC_SAFE_MODE … #define regRLC_SAFE_MODE_BASE_IDX … #define regRLC_MEM_SLP_CNTL … #define regRLC_MEM_SLP_CNTL_BASE_IDX … #define regSMU_RLC_RESPONSE … #define regSMU_RLC_RESPONSE_BASE_IDX … #define regRLC_RLCV_SAFE_MODE … #define regRLC_RLCV_SAFE_MODE_BASE_IDX … #define regRLC_SMU_SAFE_MODE … #define regRLC_SMU_SAFE_MODE_BASE_IDX … #define regRLC_RLCV_COMMAND … #define regRLC_RLCV_COMMAND_BASE_IDX … #define regRLC_REFCLOCK_TIMESTAMP_LSB … #define regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX … #define regRLC_REFCLOCK_TIMESTAMP_MSB … #define regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX … #define regRLC_GPM_TIMER_INT_0 … #define regRLC_GPM_TIMER_INT_0_BASE_IDX … #define regRLC_GPM_TIMER_INT_1 … #define regRLC_GPM_TIMER_INT_1_BASE_IDX … #define regRLC_GPM_TIMER_INT_2 … #define regRLC_GPM_TIMER_INT_2_BASE_IDX … #define regRLC_GPM_TIMER_CTRL … #define regRLC_GPM_TIMER_CTRL_BASE_IDX … #define regRLC_LB_CNTR_MAX … #define regRLC_LB_CNTR_MAX_BASE_IDX … #define regRLC_GPM_TIMER_STAT … #define regRLC_GPM_TIMER_STAT_BASE_IDX … #define regRLC_GPM_TIMER_INT_3 … #define regRLC_GPM_TIMER_INT_3_BASE_IDX … #define regRLC_SERDES_WR_NONCU_MASTER_MASK_1 … #define regRLC_SERDES_WR_NONCU_MASTER_MASK_1_BASE_IDX … #define regRLC_SERDES_NONCU_MASTER_BUSY_1 … #define regRLC_SERDES_NONCU_MASTER_BUSY_1_BASE_IDX … #define regRLC_INT_STAT … #define regRLC_INT_STAT_BASE_IDX … #define regRLC_LB_CNTL … #define regRLC_LB_CNTL_BASE_IDX … #define regRLC_MGCG_CTRL … #define regRLC_MGCG_CTRL_BASE_IDX … #define regRLC_LB_CNTR_INIT … #define regRLC_LB_CNTR_INIT_BASE_IDX … #define regRLC_LOAD_BALANCE_CNTR … #define regRLC_LOAD_BALANCE_CNTR_BASE_IDX … #define regRLC_JUMP_TABLE_RESTORE … #define regRLC_JUMP_TABLE_RESTORE_BASE_IDX … #define regRLC_PG_DELAY_2 … #define regRLC_PG_DELAY_2_BASE_IDX … #define regRLC_GPU_CLOCK_COUNT_LSB … #define regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX … #define regRLC_GPU_CLOCK_COUNT_MSB … #define regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX … #define regRLC_CAPTURE_GPU_CLOCK_COUNT … #define regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX … #define regRLC_UCODE_CNTL … #define regRLC_UCODE_CNTL_BASE_IDX … #define regRLC_GPM_THREAD_RESET … #define regRLC_GPM_THREAD_RESET_BASE_IDX … #define regRLC_GPM_CP_DMA_COMPLETE_T0 … #define regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX … #define regRLC_GPM_CP_DMA_COMPLETE_T1 … #define regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX … #define regRLC_FIREWALL_VIOLATION … #define regRLC_FIREWALL_VIOLATION_BASE_IDX … #define regRLC_CLK_COUNT_GFXCLK_LSB … #define regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX … #define regRLC_CLK_COUNT_GFXCLK_MSB … #define regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX … #define regRLC_CLK_COUNT_REFCLK_LSB … #define regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX … #define regRLC_CLK_COUNT_REFCLK_MSB … #define regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX … #define regRLC_CLK_COUNT_CTRL … #define regRLC_CLK_COUNT_CTRL_BASE_IDX … #define regRLC_CLK_COUNT_STAT … #define regRLC_CLK_COUNT_STAT_BASE_IDX … #define regRLC_GPM_STAT … #define regRLC_GPM_STAT_BASE_IDX … #define regRLC_GPU_CLOCK_32_RES_SEL … #define regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX … #define regRLC_GPU_CLOCK_32 … #define regRLC_GPU_CLOCK_32_BASE_IDX … #define regRLC_PG_CNTL … #define regRLC_PG_CNTL_BASE_IDX … #define regRLC_GPM_THREAD_PRIORITY … #define regRLC_GPM_THREAD_PRIORITY_BASE_IDX … #define regRLC_GPM_THREAD_ENABLE … #define regRLC_GPM_THREAD_ENABLE_BASE_IDX … #define regRLC_CGTT_MGCG_OVERRIDE … #define regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX … #define regRLC_CGCG_CGLS_CTRL … #define regRLC_CGCG_CGLS_CTRL_BASE_IDX … #define regRLC_CGCG_RAMP_CTRL … #define regRLC_CGCG_RAMP_CTRL_BASE_IDX … #define regRLC_DYN_PG_STATUS … #define regRLC_DYN_PG_STATUS_BASE_IDX … #define regRLC_DYN_PG_REQUEST … #define regRLC_DYN_PG_REQUEST_BASE_IDX … #define regRLC_PG_DELAY … #define regRLC_PG_DELAY_BASE_IDX … #define regRLC_CU_STATUS … #define regRLC_CU_STATUS_BASE_IDX … #define regRLC_LB_INIT_CU_MASK … #define regRLC_LB_INIT_CU_MASK_BASE_IDX … #define regRLC_LB_ALWAYS_ACTIVE_CU_MASK … #define regRLC_LB_ALWAYS_ACTIVE_CU_MASK_BASE_IDX … #define regRLC_LB_PARAMS … #define regRLC_LB_PARAMS_BASE_IDX … #define regRLC_THREAD1_DELAY … #define regRLC_THREAD1_DELAY_BASE_IDX … #define regRLC_PG_ALWAYS_ON_CU_MASK … #define regRLC_PG_ALWAYS_ON_CU_MASK_BASE_IDX … #define regRLC_MAX_PG_CU … #define regRLC_MAX_PG_CU_BASE_IDX … #define regRLC_AUTO_PG_CTRL … #define regRLC_AUTO_PG_CTRL_BASE_IDX … #define regRLC_SMU_GRBM_REG_SAVE_CTRL … #define regRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX … #define regRLC_SERDES_RD_PENDING … #define regRLC_SERDES_RD_PENDING_BASE_IDX … #define regRLC_SERDES_RD_MASTER_INDEX … #define regRLC_SERDES_RD_MASTER_INDEX_BASE_IDX … #define regRLC_SERDES_RD_DATA_0 … #define regRLC_SERDES_RD_DATA_0_BASE_IDX … #define regRLC_SERDES_RD_DATA_1 … #define regRLC_SERDES_RD_DATA_1_BASE_IDX … #define regRLC_SERDES_RD_DATA_2 … #define regRLC_SERDES_RD_DATA_2_BASE_IDX … #define regRLC_SERDES_WR_CU_MASTER_MASK … #define regRLC_SERDES_WR_CU_MASTER_MASK_BASE_IDX … #define regRLC_SERDES_WR_NONCU_MASTER_MASK … #define regRLC_SERDES_WR_NONCU_MASTER_MASK_BASE_IDX … #define regRLC_SERDES_WR_CTRL … #define regRLC_SERDES_WR_CTRL_BASE_IDX … #define regRLC_SERDES_WR_DATA … #define regRLC_SERDES_WR_DATA_BASE_IDX … #define regRLC_SERDES_CU_MASTER_BUSY … #define regRLC_SERDES_CU_MASTER_BUSY_BASE_IDX … #define regRLC_SERDES_NONCU_MASTER_BUSY … #define regRLC_SERDES_NONCU_MASTER_BUSY_BASE_IDX … #define regRLC_GPM_GENERAL_0 … #define regRLC_GPM_GENERAL_0_BASE_IDX … #define regRLC_GPM_GENERAL_1 … #define regRLC_GPM_GENERAL_1_BASE_IDX … #define regRLC_GPM_GENERAL_2 … #define regRLC_GPM_GENERAL_2_BASE_IDX … #define regRLC_GPM_GENERAL_3 … #define regRLC_GPM_GENERAL_3_BASE_IDX … #define regRLC_GPM_GENERAL_4 … #define regRLC_GPM_GENERAL_4_BASE_IDX … #define regRLC_GPM_GENERAL_5 … #define regRLC_GPM_GENERAL_5_BASE_IDX … #define regRLC_GPM_GENERAL_6 … #define regRLC_GPM_GENERAL_6_BASE_IDX … #define regRLC_GPM_GENERAL_7 … #define regRLC_GPM_GENERAL_7_BASE_IDX … #define regRLC_GPM_SCRATCH_ADDR … #define regRLC_GPM_SCRATCH_ADDR_BASE_IDX … #define regRLC_GPM_SCRATCH_DATA … #define regRLC_GPM_SCRATCH_DATA_BASE_IDX … #define regRLC_STATIC_PG_STATUS … #define regRLC_STATIC_PG_STATUS_BASE_IDX … #define regRLC_SPM_MC_CNTL … #define regRLC_SPM_MC_CNTL_BASE_IDX … #define regRLC_SPM_INT_CNTL … #define regRLC_SPM_INT_CNTL_BASE_IDX … #define regRLC_SPM_INT_STATUS … #define regRLC_SPM_INT_STATUS_BASE_IDX … #define regRLC_SMU_MESSAGE … #define regRLC_SMU_MESSAGE_BASE_IDX … #define regRLC_GPM_LOG_SIZE … #define regRLC_GPM_LOG_SIZE_BASE_IDX … #define regRLC_PG_DELAY_3 … #define regRLC_PG_DELAY_3_BASE_IDX … #define regRLC_GPR_REG1 … #define regRLC_GPR_REG1_BASE_IDX … #define regRLC_GPR_REG2 … #define regRLC_GPR_REG2_BASE_IDX … #define regRLC_GPM_LOG_CONT … #define regRLC_GPM_LOG_CONT_BASE_IDX … #define regRLC_GPM_INT_DISABLE_TH0 … #define regRLC_GPM_INT_DISABLE_TH0_BASE_IDX … #define regRLC_GPM_INT_FORCE_TH0 … #define regRLC_GPM_INT_FORCE_TH0_BASE_IDX … #define regRLC_GPM_INT_FORCE_TH1 … #define regRLC_GPM_INT_FORCE_TH1_BASE_IDX … #define regRLC_SRM_CNTL … #define regRLC_SRM_CNTL_BASE_IDX … #define regRLC_SRM_ARAM_ADDR … #define regRLC_SRM_ARAM_ADDR_BASE_IDX … #define regRLC_SRM_ARAM_DATA … #define regRLC_SRM_ARAM_DATA_BASE_IDX … #define regRLC_SRM_DRAM_ADDR … #define regRLC_SRM_DRAM_ADDR_BASE_IDX … #define regRLC_SRM_DRAM_DATA … #define regRLC_SRM_DRAM_DATA_BASE_IDX … #define regRLC_SRM_GPM_COMMAND … #define regRLC_SRM_GPM_COMMAND_BASE_IDX … #define regRLC_SRM_GPM_COMMAND_STATUS … #define regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX … #define regRLC_SRM_RLCV_COMMAND … #define regRLC_SRM_RLCV_COMMAND_BASE_IDX … #define regRLC_SRM_RLCV_COMMAND_STATUS … #define regRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_ADDR_0 … #define regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_ADDR_1 … #define regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_ADDR_2 … #define regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_ADDR_3 … #define regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_ADDR_4 … #define regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_ADDR_5 … #define regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_ADDR_6 … #define regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_ADDR_7 … #define regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_DATA_0 … #define regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_DATA_1 … #define regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_DATA_2 … #define regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_DATA_3 … #define regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_DATA_4 … #define regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_DATA_5 … #define regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_DATA_6 … #define regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_DATA_7 … #define regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX … #define regRLC_SRM_STAT … #define regRLC_SRM_STAT_BASE_IDX … #define regRLC_SRM_GPM_ABORT … #define regRLC_SRM_GPM_ABORT_BASE_IDX … #define regRLC_CSIB_ADDR_LO … #define regRLC_CSIB_ADDR_LO_BASE_IDX … #define regRLC_CSIB_ADDR_HI … #define regRLC_CSIB_ADDR_HI_BASE_IDX … #define regRLC_CSIB_LENGTH … #define regRLC_CSIB_LENGTH_BASE_IDX … #define regRLC_SMU_COMMAND … #define regRLC_SMU_COMMAND_BASE_IDX … #define regRLC_CP_SCHEDULERS … #define regRLC_CP_SCHEDULERS_BASE_IDX … #define regRLC_SMU_ARGUMENT_1 … #define regRLC_SMU_ARGUMENT_1_BASE_IDX … #define regRLC_SMU_ARGUMENT_2 … #define regRLC_SMU_ARGUMENT_2_BASE_IDX … #define regRLC_GPM_GENERAL_8 … #define regRLC_GPM_GENERAL_8_BASE_IDX … #define regRLC_GPM_GENERAL_9 … #define regRLC_GPM_GENERAL_9_BASE_IDX … #define regRLC_GPM_GENERAL_10 … #define regRLC_GPM_GENERAL_10_BASE_IDX … #define regRLC_GPM_GENERAL_11 … #define regRLC_GPM_GENERAL_11_BASE_IDX … #define regRLC_GPM_GENERAL_12 … #define regRLC_GPM_GENERAL_12_BASE_IDX … #define regRLC_GPM_UTCL1_CNTL_0 … #define regRLC_GPM_UTCL1_CNTL_0_BASE_IDX … #define regRLC_GPM_UTCL1_CNTL_1 … #define regRLC_GPM_UTCL1_CNTL_1_BASE_IDX … #define regRLC_GPM_UTCL1_CNTL_2 … #define regRLC_GPM_UTCL1_CNTL_2_BASE_IDX … #define regRLC_SPM_UTCL1_CNTL … #define regRLC_SPM_UTCL1_CNTL_BASE_IDX … #define regRLC_UTCL1_STATUS_2 … #define regRLC_UTCL1_STATUS_2_BASE_IDX … #define regRLC_LB_THR_CONFIG_2 … #define regRLC_LB_THR_CONFIG_2_BASE_IDX … #define regRLC_LB_THR_CONFIG_3 … #define regRLC_LB_THR_CONFIG_3_BASE_IDX … #define regRLC_LB_THR_CONFIG_4 … #define regRLC_LB_THR_CONFIG_4_BASE_IDX … #define regRLC_SPM_UTCL1_ERROR_1 … #define regRLC_SPM_UTCL1_ERROR_1_BASE_IDX … #define regRLC_SPM_UTCL1_ERROR_2 … #define regRLC_SPM_UTCL1_ERROR_2_BASE_IDX … #define regRLC_GPM_UTCL1_TH0_ERROR_1 … #define regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX … #define regRLC_LB_THR_CONFIG_1 … #define regRLC_LB_THR_CONFIG_1_BASE_IDX … #define regRLC_GPM_UTCL1_TH0_ERROR_2 … #define regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX … #define regRLC_GPM_UTCL1_TH1_ERROR_1 … #define regRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX … #define regRLC_GPM_UTCL1_TH1_ERROR_2 … #define regRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX … #define regRLC_GPM_UTCL1_TH2_ERROR_1 … #define regRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX … #define regRLC_GPM_UTCL1_TH2_ERROR_2 … #define regRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX … #define regRLC_SEMAPHORE_0 … #define regRLC_SEMAPHORE_0_BASE_IDX … #define regRLC_SEMAPHORE_1 … #define regRLC_SEMAPHORE_1_BASE_IDX … #define regRLC_CP_EOF_INT … #define regRLC_CP_EOF_INT_BASE_IDX … #define regRLC_CP_EOF_INT_CNT … #define regRLC_CP_EOF_INT_CNT_BASE_IDX … #define regRLC_SPARE_INT … #define regRLC_SPARE_INT_BASE_IDX … #define regRLC_PREWALKER_UTCL1_CNTL … #define regRLC_PREWALKER_UTCL1_CNTL_BASE_IDX … #define regRLC_PREWALKER_UTCL1_TRIG … #define regRLC_PREWALKER_UTCL1_TRIG_BASE_IDX … #define regRLC_PREWALKER_UTCL1_ADDR_LSB … #define regRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX … #define regRLC_PREWALKER_UTCL1_ADDR_MSB … #define regRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX … #define regRLC_PREWALKER_UTCL1_SIZE_LSB … #define regRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX … #define regRLC_PREWALKER_UTCL1_SIZE_MSB … #define regRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX … #define regRLC_DSM_TRIG … #define regRLC_DSM_TRIG_BASE_IDX … #define regRLC_UTCL1_STATUS … #define regRLC_UTCL1_STATUS_BASE_IDX … #define regRLC_R2I_CNTL_0 … #define regRLC_R2I_CNTL_0_BASE_IDX … #define regRLC_R2I_CNTL_1 … #define regRLC_R2I_CNTL_1_BASE_IDX … #define regRLC_R2I_CNTL_2 … #define regRLC_R2I_CNTL_2_BASE_IDX … #define regRLC_R2I_CNTL_3 … #define regRLC_R2I_CNTL_3_BASE_IDX … #define regRLC_UTCL2_CNTL … #define regRLC_UTCL2_CNTL_BASE_IDX … #define regRLC_LBPW_CU_STAT … #define regRLC_LBPW_CU_STAT_BASE_IDX … #define regRLC_DS_CNTL … #define regRLC_DS_CNTL_BASE_IDX … #define regRLC_GPM_INT_STAT_TH0 … #define regRLC_GPM_INT_STAT_TH0_BASE_IDX … #define regRLC_GPM_GENERAL_13 … #define regRLC_GPM_GENERAL_13_BASE_IDX … #define regRLC_GPM_GENERAL_14 … #define regRLC_GPM_GENERAL_14_BASE_IDX … #define regRLC_GPM_GENERAL_15 … #define regRLC_GPM_GENERAL_15_BASE_IDX … #define regRLC_SPARE_INT_1 … #define regRLC_SPARE_INT_1_BASE_IDX … #define regRLC_RLCV_SPARE_INT_1 … #define regRLC_RLCV_SPARE_INT_1_BASE_IDX … #define regRLC_SEMAPHORE_2 … #define regRLC_SEMAPHORE_2_BASE_IDX … #define regRLC_SEMAPHORE_3 … #define regRLC_SEMAPHORE_3_BASE_IDX … #define regRLC_SMU_ARGUMENT_3 … #define regRLC_SMU_ARGUMENT_3_BASE_IDX … #define regRLC_SMU_ARGUMENT_4 … #define regRLC_SMU_ARGUMENT_4_BASE_IDX … #define regRLC_GPU_CLOCK_COUNT_LSB_1 … #define regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX … #define regRLC_GPU_CLOCK_COUNT_MSB_1 … #define regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX … #define regRLC_CAPTURE_GPU_CLOCK_COUNT_1 … #define regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX … #define regRLC_GPU_CLOCK_COUNT_LSB_2 … #define regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX … #define regRLC_GPU_CLOCK_COUNT_MSB_2 … #define regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX … #define regRLC_CAPTURE_GPU_CLOCK_COUNT_2 … #define regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX … #define regRLC_CPG_STAT_INVAL … #define regRLC_CPG_STAT_INVAL_BASE_IDX … #define regRLC_UE_ERR_STATUS_LOW … #define regRLC_UE_ERR_STATUS_LOW_BASE_IDX … #define regRLC_UE_ERR_STATUS_HIGH … #define regRLC_UE_ERR_STATUS_HIGH_BASE_IDX … #define regRLC_DSM_CNTL … #define regRLC_DSM_CNTL_BASE_IDX … #define regRLC_DSM_CNTLA … #define regRLC_DSM_CNTLA_BASE_IDX … #define regRLC_DSM_CNTL2 … #define regRLC_DSM_CNTL2_BASE_IDX … #define regRLC_DSM_CNTL2A … #define regRLC_DSM_CNTL2A_BASE_IDX … #define regRLC_CE_ERR_STATUS_LOW … #define regRLC_CE_ERR_STATUS_LOW_BASE_IDX … #define regRLC_CE_ERR_STATUS_HIGH … #define regRLC_CE_ERR_STATUS_HIGH_BASE_IDX … #define regRLC_RLCV_SPARE_INT … #define regRLC_RLCV_SPARE_INT_BASE_IDX … #define regRLC_SMU_CLK_REQ … #define regRLC_SMU_CLK_REQ_BASE_IDX … // addressBlock: xcd0_gc_pwrdec // base address: 0x3c000 #define regCGTS_SM_CTRL_REG … #define regCGTS_SM_CTRL_REG_BASE_IDX … #define regCGTS_RD_CTRL_REG … #define regCGTS_RD_CTRL_REG_BASE_IDX … #define regCGTS_RD_REG … #define regCGTS_RD_REG_BASE_IDX … #define regCGTS_TCC_DISABLE … #define regCGTS_TCC_DISABLE_BASE_IDX … #define regCGTS_USER_TCC_DISABLE … #define regCGTS_USER_TCC_DISABLE_BASE_IDX … #define regCGTS_CU0_SP0_CTRL_REG … #define regCGTS_CU0_SP0_CTRL_REG_BASE_IDX … #define regCGTS_CU0_LDS_SQ_CTRL_REG … #define regCGTS_CU0_LDS_SQ_CTRL_REG_BASE_IDX … #define regCGTS_CU0_TA_SQC_CTRL_REG … #define regCGTS_CU0_TA_SQC_CTRL_REG_BASE_IDX … #define regCGTS_CU0_SP1_CTRL_REG … #define regCGTS_CU0_SP1_CTRL_REG_BASE_IDX … #define regCGTS_CU0_TD_TCP_CTRL_REG … #define regCGTS_CU0_TD_TCP_CTRL_REG_BASE_IDX … #define regCGTS_CU1_SP0_CTRL_REG … #define regCGTS_CU1_SP0_CTRL_REG_BASE_IDX … #define regCGTS_CU1_LDS_SQ_CTRL_REG … #define regCGTS_CU1_LDS_SQ_CTRL_REG_BASE_IDX … #define regCGTS_CU1_TA_SQC_CTRL_REG … #define regCGTS_CU1_TA_SQC_CTRL_REG_BASE_IDX … #define regCGTS_CU1_SP1_CTRL_REG … #define regCGTS_CU1_SP1_CTRL_REG_BASE_IDX … #define regCGTS_CU1_TD_TCP_CTRL_REG … #define regCGTS_CU1_TD_TCP_CTRL_REG_BASE_IDX … #define regCGTS_CU2_SP0_CTRL_REG … #define regCGTS_CU2_SP0_CTRL_REG_BASE_IDX … #define regCGTS_CU2_LDS_SQ_CTRL_REG … #define regCGTS_CU2_LDS_SQ_CTRL_REG_BASE_IDX … #define regCGTS_CU2_TA_SQC_CTRL_REG … #define regCGTS_CU2_TA_SQC_CTRL_REG_BASE_IDX … #define regCGTS_CU2_SP1_CTRL_REG … #define regCGTS_CU2_SP1_CTRL_REG_BASE_IDX … #define regCGTS_CU2_TD_TCP_CTRL_REG … #define regCGTS_CU2_TD_TCP_CTRL_REG_BASE_IDX … #define regCGTS_CU3_SP0_CTRL_REG … #define regCGTS_CU3_SP0_CTRL_REG_BASE_IDX … #define regCGTS_CU3_LDS_SQ_CTRL_REG … #define regCGTS_CU3_LDS_SQ_CTRL_REG_BASE_IDX … #define regCGTS_CU3_TA_SQC_CTRL_REG … #define regCGTS_CU3_TA_SQC_CTRL_REG_BASE_IDX … #define regCGTS_CU3_SP1_CTRL_REG … #define regCGTS_CU3_SP1_CTRL_REG_BASE_IDX … #define regCGTS_CU3_TD_TCP_CTRL_REG … #define regCGTS_CU3_TD_TCP_CTRL_REG_BASE_IDX … #define regCGTS_CU4_SP0_CTRL_REG … #define regCGTS_CU4_SP0_CTRL_REG_BASE_IDX … #define regCGTS_CU4_LDS_SQ_CTRL_REG … #define regCGTS_CU4_LDS_SQ_CTRL_REG_BASE_IDX … #define regCGTS_CU4_TA_SQC_CTRL_REG … #define regCGTS_CU4_TA_SQC_CTRL_REG_BASE_IDX … #define regCGTS_CU4_SP1_CTRL_REG … #define regCGTS_CU4_SP1_CTRL_REG_BASE_IDX … #define regCGTS_CU4_TD_TCP_CTRL_REG … #define regCGTS_CU4_TD_TCP_CTRL_REG_BASE_IDX … #define regCGTS_CU5_SP0_CTRL_REG … #define regCGTS_CU5_SP0_CTRL_REG_BASE_IDX … #define regCGTS_CU5_LDS_SQ_CTRL_REG … #define regCGTS_CU5_LDS_SQ_CTRL_REG_BASE_IDX … #define regCGTS_CU5_TA_SQC_CTRL_REG … #define regCGTS_CU5_TA_SQC_CTRL_REG_BASE_IDX … #define regCGTS_CU5_SP1_CTRL_REG … #define regCGTS_CU5_SP1_CTRL_REG_BASE_IDX … #define regCGTS_CU5_TD_TCP_CTRL_REG … #define regCGTS_CU5_TD_TCP_CTRL_REG_BASE_IDX … #define regCGTS_CU6_SP0_CTRL_REG … #define regCGTS_CU6_SP0_CTRL_REG_BASE_IDX … #define regCGTS_CU6_LDS_SQ_CTRL_REG … #define regCGTS_CU6_LDS_SQ_CTRL_REG_BASE_IDX … #define regCGTS_CU6_TA_SQC_CTRL_REG … #define regCGTS_CU6_TA_SQC_CTRL_REG_BASE_IDX … #define regCGTS_CU6_SP1_CTRL_REG … #define regCGTS_CU6_SP1_CTRL_REG_BASE_IDX … #define regCGTS_CU6_TD_TCP_CTRL_REG … #define regCGTS_CU6_TD_TCP_CTRL_REG_BASE_IDX … #define regCGTS_CU7_SP0_CTRL_REG … #define regCGTS_CU7_SP0_CTRL_REG_BASE_IDX … #define regCGTS_CU7_LDS_SQ_CTRL_REG … #define regCGTS_CU7_LDS_SQ_CTRL_REG_BASE_IDX … #define regCGTS_CU7_TA_SQC_CTRL_REG … #define regCGTS_CU7_TA_SQC_CTRL_REG_BASE_IDX … #define regCGTS_CU7_SP1_CTRL_REG … #define regCGTS_CU7_SP1_CTRL_REG_BASE_IDX … #define regCGTS_CU7_TD_TCP_CTRL_REG … #define regCGTS_CU7_TD_TCP_CTRL_REG_BASE_IDX … #define regCGTS_CU8_SP0_CTRL_REG … #define regCGTS_CU8_SP0_CTRL_REG_BASE_IDX … #define regCGTS_CU8_LDS_SQ_CTRL_REG … #define regCGTS_CU8_LDS_SQ_CTRL_REG_BASE_IDX … #define regCGTS_CU8_TA_SQC_CTRL_REG … #define regCGTS_CU8_TA_SQC_CTRL_REG_BASE_IDX … #define regCGTS_CU8_SP1_CTRL_REG … #define regCGTS_CU8_SP1_CTRL_REG_BASE_IDX … #define regCGTS_CU8_TD_TCP_CTRL_REG … #define regCGTS_CU8_TD_TCP_CTRL_REG_BASE_IDX … #define regCGTS_CU9_SP0_CTRL_REG … #define regCGTS_CU9_SP0_CTRL_REG_BASE_IDX … #define regCGTS_CU9_LDS_SQ_CTRL_REG … #define regCGTS_CU9_LDS_SQ_CTRL_REG_BASE_IDX … #define regCGTS_CU9_TA_SQC_CTRL_REG … #define regCGTS_CU9_TA_SQC_CTRL_REG_BASE_IDX … #define regCGTS_CU9_SP1_CTRL_REG … #define regCGTS_CU9_SP1_CTRL_REG_BASE_IDX … #define regCGTS_CU9_TD_TCP_CTRL_REG … #define regCGTS_CU9_TD_TCP_CTRL_REG_BASE_IDX … #define regCGTS_CU10_SP0_CTRL_REG … #define regCGTS_CU10_SP0_CTRL_REG_BASE_IDX … #define regCGTS_CU10_LDS_SQ_CTRL_REG … #define regCGTS_CU10_LDS_SQ_CTRL_REG_BASE_IDX … #define regCGTS_CU10_TA_SQC_CTRL_REG … #define regCGTS_CU10_TA_SQC_CTRL_REG_BASE_IDX … #define regCGTS_CU10_SP1_CTRL_REG … #define regCGTS_CU10_SP1_CTRL_REG_BASE_IDX … #define regCGTS_CU10_TD_TCP_CTRL_REG … #define regCGTS_CU10_TD_TCP_CTRL_REG_BASE_IDX … #define regCGTS_CU11_SP0_CTRL_REG … #define regCGTS_CU11_SP0_CTRL_REG_BASE_IDX … #define regCGTS_CU11_LDS_SQ_CTRL_REG … #define regCGTS_CU11_LDS_SQ_CTRL_REG_BASE_IDX … #define regCGTS_CU11_TA_SQC_CTRL_REG … #define regCGTS_CU11_TA_SQC_CTRL_REG_BASE_IDX … #define regCGTS_CU11_SP1_CTRL_REG … #define regCGTS_CU11_SP1_CTRL_REG_BASE_IDX … #define regCGTS_CU11_TD_TCP_CTRL_REG … #define regCGTS_CU11_TD_TCP_CTRL_REG_BASE_IDX … #define regCGTS_CU12_SP0_CTRL_REG … #define regCGTS_CU12_SP0_CTRL_REG_BASE_IDX … #define regCGTS_CU12_LDS_SQ_CTRL_REG … #define regCGTS_CU12_LDS_SQ_CTRL_REG_BASE_IDX … #define regCGTS_CU12_TA_SQC_CTRL_REG … #define regCGTS_CU12_TA_SQC_CTRL_REG_BASE_IDX … #define regCGTS_CU12_SP1_CTRL_REG … #define regCGTS_CU12_SP1_CTRL_REG_BASE_IDX … #define regCGTS_CU12_TD_TCP_CTRL_REG … #define regCGTS_CU12_TD_TCP_CTRL_REG_BASE_IDX … #define regCGTS_CU13_SP0_CTRL_REG … #define regCGTS_CU13_SP0_CTRL_REG_BASE_IDX … #define regCGTS_CU13_LDS_SQ_CTRL_REG … #define regCGTS_CU13_LDS_SQ_CTRL_REG_BASE_IDX … #define regCGTS_CU13_TA_SQC_CTRL_REG … #define regCGTS_CU13_TA_SQC_CTRL_REG_BASE_IDX … #define regCGTS_CU13_SP1_CTRL_REG … #define regCGTS_CU13_SP1_CTRL_REG_BASE_IDX … #define regCGTS_CU13_TD_TCP_CTRL_REG … #define regCGTS_CU13_TD_TCP_CTRL_REG_BASE_IDX … #define regCGTS_CU14_SP0_CTRL_REG … #define regCGTS_CU14_SP0_CTRL_REG_BASE_IDX … #define regCGTS_CU14_LDS_SQ_CTRL_REG … #define regCGTS_CU14_LDS_SQ_CTRL_REG_BASE_IDX … #define regCGTS_CU14_TA_SQC_CTRL_REG … #define regCGTS_CU14_TA_SQC_CTRL_REG_BASE_IDX … #define regCGTS_CU14_SP1_CTRL_REG … #define regCGTS_CU14_SP1_CTRL_REG_BASE_IDX … #define regCGTS_CU14_TD_TCP_CTRL_REG … #define regCGTS_CU14_TD_TCP_CTRL_REG_BASE_IDX … #define regCGTS_CU15_SP0_CTRL_REG … #define regCGTS_CU15_SP0_CTRL_REG_BASE_IDX … #define regCGTS_CU15_LDS_SQ_CTRL_REG … #define regCGTS_CU15_LDS_SQ_CTRL_REG_BASE_IDX … #define regCGTS_CU15_TA_SQC_CTRL_REG … #define regCGTS_CU15_TA_SQC_CTRL_REG_BASE_IDX … #define regCGTS_CU15_SP1_CTRL_REG … #define regCGTS_CU15_SP1_CTRL_REG_BASE_IDX … #define regCGTS_CU15_TD_TCP_CTRL_REG … #define regCGTS_CU15_TD_TCP_CTRL_REG_BASE_IDX … #define regCGTS_CU0_TCPI_CTRL_REG … #define regCGTS_CU0_TCPI_CTRL_REG_BASE_IDX … #define regCGTS_CU1_TCPI_CTRL_REG … #define regCGTS_CU1_TCPI_CTRL_REG_BASE_IDX … #define regCGTS_CU2_TCPI_CTRL_REG … #define regCGTS_CU2_TCPI_CTRL_REG_BASE_IDX … #define regCGTS_CU3_TCPI_CTRL_REG … #define regCGTS_CU3_TCPI_CTRL_REG_BASE_IDX … #define regCGTS_CU4_TCPI_CTRL_REG … #define regCGTS_CU4_TCPI_CTRL_REG_BASE_IDX … #define regCGTS_CU5_TCPI_CTRL_REG … #define regCGTS_CU5_TCPI_CTRL_REG_BASE_IDX … #define regCGTS_CU6_TCPI_CTRL_REG … #define regCGTS_CU6_TCPI_CTRL_REG_BASE_IDX … #define regCGTS_CU7_TCPI_CTRL_REG … #define regCGTS_CU7_TCPI_CTRL_REG_BASE_IDX … #define regCGTS_CU8_TCPI_CTRL_REG … #define regCGTS_CU8_TCPI_CTRL_REG_BASE_IDX … #define regCGTS_CU9_TCPI_CTRL_REG … #define regCGTS_CU9_TCPI_CTRL_REG_BASE_IDX … #define regCGTS_CU10_TCPI_CTRL_REG … #define regCGTS_CU10_TCPI_CTRL_REG_BASE_IDX … #define regCGTS_CU11_TCPI_CTRL_REG … #define regCGTS_CU11_TCPI_CTRL_REG_BASE_IDX … #define regCGTS_CU12_TCPI_CTRL_REG … #define regCGTS_CU12_TCPI_CTRL_REG_BASE_IDX … #define regCGTS_CU13_TCPI_CTRL_REG … #define regCGTS_CU13_TCPI_CTRL_REG_BASE_IDX … #define regCGTS_CU14_TCPI_CTRL_REG … #define regCGTS_CU14_TCPI_CTRL_REG_BASE_IDX … #define regCGTS_CU15_TCPI_CTRL_REG … #define regCGTS_CU15_TCPI_CTRL_REG_BASE_IDX … #define regCGTT_SPI_PS_CLK_CTRL … #define regCGTT_SPI_PS_CLK_CTRL_BASE_IDX … #define regCGTT_SPIS_CLK_CTRL … #define regCGTT_SPIS_CLK_CTRL_BASE_IDX … #define regCGTX_SPI_DEBUG_CLK_CTRL … #define regCGTX_SPI_DEBUG_CLK_CTRL_BASE_IDX … #define regCGTT_SPI_CLK_CTRL … #define regCGTT_SPI_CLK_CTRL_BASE_IDX … #define regCGTT_PC_CLK_CTRL … #define regCGTT_PC_CLK_CTRL_BASE_IDX … #define regCGTT_BCI_CLK_CTRL … #define regCGTT_BCI_CLK_CTRL_BASE_IDX … #define regCGTT_VGT_CLK_CTRL … #define regCGTT_VGT_CLK_CTRL_BASE_IDX … #define regCGTT_IA_CLK_CTRL … #define regCGTT_IA_CLK_CTRL_BASE_IDX … #define regCGTT_WD_CLK_CTRL … #define regCGTT_WD_CLK_CTRL_BASE_IDX … #define regCGTT_PA_CLK_CTRL … #define regCGTT_PA_CLK_CTRL_BASE_IDX … #define regCGTT_SC_CLK_CTRL0 … #define regCGTT_SC_CLK_CTRL0_BASE_IDX … #define regCGTT_SC_CLK_CTRL1 … #define regCGTT_SC_CLK_CTRL1_BASE_IDX … #define regCGTT_SC_CLK_CTRL2 … #define regCGTT_SC_CLK_CTRL2_BASE_IDX … #define regCGTT_SQ_CLK_CTRL … #define regCGTT_SQ_CLK_CTRL_BASE_IDX … #define regCGTT_SQG_CLK_CTRL … #define regCGTT_SQG_CLK_CTRL_BASE_IDX … #define regSQ_ALU_CLK_CTRL … #define regSQ_ALU_CLK_CTRL_BASE_IDX … #define regSQ_TEX_CLK_CTRL … #define regSQ_TEX_CLK_CTRL_BASE_IDX … #define regSQ_LDS_CLK_CTRL … #define regSQ_LDS_CLK_CTRL_BASE_IDX … #define regSQ_POWER_THROTTLE … #define regSQ_POWER_THROTTLE_BASE_IDX … #define regSQ_POWER_THROTTLE2 … #define regSQ_POWER_THROTTLE2_BASE_IDX … #define regTD_CGTT_CTRL … #define regTD_CGTT_CTRL_BASE_IDX … #define regTA_CGTT_CTRL … #define regTA_CGTT_CTRL_BASE_IDX … #define regCGTT_TCPI_CLK_CTRL … #define regCGTT_TCPI_CLK_CTRL_BASE_IDX … #define regTCX_CGTT_SCLK_CTRL … #define regTCX_CGTT_SCLK_CTRL_BASE_IDX … #define regDB_CGTT_CLK_CTRL_0 … #define regDB_CGTT_CLK_CTRL_0_BASE_IDX … #define regCB_CGTT_SCLK_CTRL … #define regCB_CGTT_SCLK_CTRL_BASE_IDX … #define regTCC_CGTT_SCLK_CTRL … #define regTCC_CGTT_SCLK_CTRL_BASE_IDX … #define regTCC_CGTT_SCLK_CTRL2 … #define regTCC_CGTT_SCLK_CTRL2_BASE_IDX … #define regTCC_CGTT_SCLK_CTRL3 … #define regTCC_CGTT_SCLK_CTRL3_BASE_IDX … #define regTCA_CGTT_SCLK_CTRL … #define regTCA_CGTT_SCLK_CTRL_BASE_IDX … #define regCGTT_CP_CLK_CTRL … #define regCGTT_CP_CLK_CTRL_BASE_IDX … #define regCGTT_CPC_CLK_CTRL … #define regCGTT_CPC_CLK_CTRL_BASE_IDX … #define regCGTT_RLC_CLK_CTRL … #define regCGTT_RLC_CLK_CTRL_BASE_IDX … #define regRLC_GFX_RM_CNTL … #define regRLC_GFX_RM_CNTL_BASE_IDX … #define regRMI_CGTT_SCLK_CTRL … #define regRMI_CGTT_SCLK_CTRL_BASE_IDX … #define regCGTT_TCPF_CLK_CTRL … #define regCGTT_TCPF_CLK_CTRL_BASE_IDX … // addressBlock: xcd0_gc_hypdec // base address: 0x3e000 #define regCP_HYP_PFP_UCODE_ADDR … #define regCP_HYP_PFP_UCODE_ADDR_BASE_IDX … #define regCP_PFP_UCODE_ADDR … #define regCP_PFP_UCODE_ADDR_BASE_IDX … #define regCP_HYP_PFP_UCODE_DATA … #define regCP_HYP_PFP_UCODE_DATA_BASE_IDX … #define regCP_PFP_UCODE_DATA … #define regCP_PFP_UCODE_DATA_BASE_IDX … #define regCP_HYP_ME_UCODE_ADDR … #define regCP_HYP_ME_UCODE_ADDR_BASE_IDX … #define regCP_ME_RAM_RADDR … #define regCP_ME_RAM_RADDR_BASE_IDX … #define regCP_ME_RAM_WADDR … #define regCP_ME_RAM_WADDR_BASE_IDX … #define regCP_HYP_ME_UCODE_DATA … #define regCP_HYP_ME_UCODE_DATA_BASE_IDX … #define regCP_ME_RAM_DATA … #define regCP_ME_RAM_DATA_BASE_IDX … #define regCP_CE_UCODE_ADDR … #define regCP_CE_UCODE_ADDR_BASE_IDX … #define regCP_HYP_CE_UCODE_ADDR … #define regCP_HYP_CE_UCODE_ADDR_BASE_IDX … #define regCP_CE_UCODE_DATA … #define regCP_CE_UCODE_DATA_BASE_IDX … #define regCP_HYP_CE_UCODE_DATA … #define regCP_HYP_CE_UCODE_DATA_BASE_IDX … #define regCP_HYP_MEC1_UCODE_ADDR … #define regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX … #define regCP_MEC_ME1_UCODE_ADDR … #define regCP_MEC_ME1_UCODE_ADDR_BASE_IDX … #define regCP_HYP_MEC1_UCODE_DATA … #define regCP_HYP_MEC1_UCODE_DATA_BASE_IDX … #define regCP_MEC_ME1_UCODE_DATA … #define regCP_MEC_ME1_UCODE_DATA_BASE_IDX … #define regCP_HYP_MEC2_UCODE_ADDR … #define regCP_HYP_MEC2_UCODE_ADDR_BASE_IDX … #define regCP_MEC_ME2_UCODE_ADDR … #define regCP_MEC_ME2_UCODE_ADDR_BASE_IDX … #define regCP_HYP_MEC2_UCODE_DATA … #define regCP_HYP_MEC2_UCODE_DATA_BASE_IDX … #define regCP_MEC_ME2_UCODE_DATA … #define regCP_MEC_ME2_UCODE_DATA_BASE_IDX … #define regCP_HYP_PFP_UCODE_CHKSUM … #define regCP_HYP_PFP_UCODE_CHKSUM_BASE_IDX … #define regCP_HYP_CE_UCODE_CHKSUM … #define regCP_HYP_CE_UCODE_CHKSUM_BASE_IDX … #define regCP_HYP_ME_UCODE_CHKSUM … #define regCP_HYP_ME_UCODE_CHKSUM_BASE_IDX … #define regCP_HYP_MEC_ME1_UCODE_CHKSUM … #define regCP_HYP_MEC_ME1_UCODE_CHKSUM_BASE_IDX … #define regCP_HYP_MEC_ME2_UCODE_CHKSUM … #define regCP_HYP_MEC_ME2_UCODE_CHKSUM_BASE_IDX … #define regCP_HYP_XCP_CTL … #define regCP_HYP_XCP_CTL_BASE_IDX … #define regRLC_GPM_UCODE_ADDR … #define regRLC_GPM_UCODE_ADDR_BASE_IDX … #define regRLC_GPM_UCODE_DATA … #define regRLC_GPM_UCODE_DATA_BASE_IDX … #define regGRBM_GFX_INDEX_SR_SELECT … #define regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX … #define regGRBM_GFX_INDEX_SR_DATA … #define regGRBM_GFX_INDEX_SR_DATA_BASE_IDX … #define regGRBM_GFX_CNTL_SR_SELECT … #define regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX … #define regGRBM_GFX_CNTL_SR_DATA … #define regGRBM_GFX_CNTL_SR_DATA_BASE_IDX … #define regGRBM_MCM_ADDR … #define regGRBM_MCM_ADDR_BASE_IDX … #define regRLC_GPU_IOV_VF_ENABLE … #define regRLC_GPU_IOV_VF_ENABLE_BASE_IDX … #define regRLC_GPU_IOV_CFG_REG6 … #define regRLC_GPU_IOV_CFG_REG6_BASE_IDX … #define regRLC_GPU_IOV_CFG_REG8 … #define regRLC_GPU_IOV_CFG_REG8_BASE_IDX … #define regRLC_RLCV_TIMER_INT_0 … #define regRLC_RLCV_TIMER_INT_0_BASE_IDX … #define regRLC_RLCV_TIMER_CTRL … #define regRLC_RLCV_TIMER_CTRL_BASE_IDX … #define regRLC_RLCV_TIMER_STAT … #define regRLC_RLCV_TIMER_STAT_BASE_IDX … #define regRLC_GPU_IOV_VF_DOORBELL_STATUS … #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX … #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET … #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX … #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR … #define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX … #define regRLC_GPU_IOV_VF_MASK … #define regRLC_GPU_IOV_VF_MASK_BASE_IDX … #define regRLC_HYP_SEMAPHORE_0 … #define regRLC_HYP_SEMAPHORE_0_BASE_IDX … #define regRLC_HYP_SEMAPHORE_1 … #define regRLC_HYP_SEMAPHORE_1_BASE_IDX … #define regRLC_CLK_CNTL … #define regRLC_CLK_CNTL_BASE_IDX … #define regRLC_GPU_IOV_SCH_BLOCK … #define regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX … #define regRLC_GPU_IOV_CFG_REG1 … #define regRLC_GPU_IOV_CFG_REG1_BASE_IDX … #define regRLC_GPU_IOV_CFG_REG2 … #define regRLC_GPU_IOV_CFG_REG2_BASE_IDX … #define regRLC_GPU_IOV_VM_BUSY_STATUS … #define regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX … #define regRLC_GPU_IOV_SCH_0 … #define regRLC_GPU_IOV_SCH_0_BASE_IDX … #define regRLC_GPU_IOV_ACTIVE_FCN_ID … #define regRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX … #define regRLC_GPU_IOV_SCH_3 … #define regRLC_GPU_IOV_SCH_3_BASE_IDX … #define regRLC_GPU_IOV_SCH_1 … #define regRLC_GPU_IOV_SCH_1_BASE_IDX … #define regRLC_GPU_IOV_SCH_2 … #define regRLC_GPU_IOV_SCH_2_BASE_IDX … #define regRLC_GPU_IOV_INT_STAT … #define regRLC_GPU_IOV_INT_STAT_BASE_IDX … #define regRLC_RLCV_TIMER_INT_1 … #define regRLC_RLCV_TIMER_INT_1_BASE_IDX … #define regRLC_GPU_IOV_UCODE_ADDR … #define regRLC_GPU_IOV_UCODE_ADDR_BASE_IDX … #define regRLC_GPU_IOV_UCODE_DATA … #define regRLC_GPU_IOV_UCODE_DATA_BASE_IDX … #define regRLC_GPU_IOV_SCRATCH_ADDR … #define regRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX … #define regRLC_GPU_IOV_SCRATCH_DATA … #define regRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX … #define regRLC_GPU_IOV_F32_CNTL … #define regRLC_GPU_IOV_F32_CNTL_BASE_IDX … #define regRLC_GPU_IOV_F32_RESET … #define regRLC_GPU_IOV_F32_RESET_BASE_IDX … #define regRLC_GPU_IOV_SDMA0_STATUS … #define regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX … #define regRLC_GPU_IOV_SDMA1_STATUS … #define regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX … #define regRLC_GPU_IOV_SMU_RESPONSE … #define regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX … #define regRLC_GPU_IOV_VIRT_RESET_REQ … #define regRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX … #define regRLC_GPU_IOV_RLC_RESPONSE … #define regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX … #define regRLC_GPU_IOV_INT_DISABLE … #define regRLC_GPU_IOV_INT_DISABLE_BASE_IDX … #define regRLC_GPU_IOV_INT_FORCE … #define regRLC_GPU_IOV_INT_FORCE_BASE_IDX … #define regRLC_GPU_IOV_SDMA0_BUSY_STATUS … #define regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX … #define regRLC_GPU_IOV_SDMA1_BUSY_STATUS … #define regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX … #define regRLC_HYP_SEMAPHORE_2 … #define regRLC_HYP_SEMAPHORE_2_BASE_IDX … #define regRLC_HYP_SEMAPHORE_3 … #define regRLC_HYP_SEMAPHORE_3_BASE_IDX … #define regRLC_GPU_IOV_SDMA2_STATUS … #define regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX … #define regRLC_GPU_IOV_SDMA3_STATUS … #define regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX … #define regRLC_GPU_IOV_SDMA4_STATUS … #define regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX … #define regRLC_GPU_IOV_SDMA5_STATUS … #define regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX … #define regRLC_GPU_IOV_SDMA6_STATUS … #define regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX … #define regRLC_GPU_IOV_SDMA7_STATUS … #define regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX … #define regRLC_GPU_IOV_SDMA2_BUSY_STATUS … #define regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX … #define regRLC_GPU_IOV_SDMA3_BUSY_STATUS … #define regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX … #define regRLC_GPU_IOV_SDMA4_BUSY_STATUS … #define regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX … #define regRLC_GPU_IOV_SDMA5_BUSY_STATUS … #define regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX … #define regRLC_GPU_IOV_SDMA6_BUSY_STATUS … #define regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX … #define regRLC_GPU_IOV_SDMA7_BUSY_STATUS … #define regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX … // addressBlock: xcd0_gc_utcl2_vmsharedhvdec // base address: 0x3ea00 #define regMC_VM_FB_SIZE_OFFSET_VF0 … #define regMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF1 … #define regMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF2 … #define regMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF3 … #define regMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF4 … #define regMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF5 … #define regMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF6 … #define regMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF7 … #define regMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF8 … #define regMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF9 … #define regMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF10 … #define regMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF11 … #define regMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF12 … #define regMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF13 … #define regMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF14 … #define regMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF15 … #define regMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX … #define regVM_IOMMU_MMIO_CNTRL_1 … #define regVM_IOMMU_MMIO_CNTRL_1_BASE_IDX … #define regMC_VM_MARC_BASE_LO_0 … #define regMC_VM_MARC_BASE_LO_0_BASE_IDX … #define regMC_VM_MARC_BASE_LO_1 … #define regMC_VM_MARC_BASE_LO_1_BASE_IDX … #define regMC_VM_MARC_BASE_LO_2 … #define regMC_VM_MARC_BASE_LO_2_BASE_IDX … #define regMC_VM_MARC_BASE_LO_3 … #define regMC_VM_MARC_BASE_LO_3_BASE_IDX … #define regMC_VM_MARC_BASE_HI_0 … #define regMC_VM_MARC_BASE_HI_0_BASE_IDX … #define regMC_VM_MARC_BASE_HI_1 … #define regMC_VM_MARC_BASE_HI_1_BASE_IDX … #define regMC_VM_MARC_BASE_HI_2 … #define regMC_VM_MARC_BASE_HI_2_BASE_IDX … #define regMC_VM_MARC_BASE_HI_3 … #define regMC_VM_MARC_BASE_HI_3_BASE_IDX … #define regMC_VM_MARC_RELOC_LO_0 … #define regMC_VM_MARC_RELOC_LO_0_BASE_IDX … #define regMC_VM_MARC_RELOC_LO_1 … #define regMC_VM_MARC_RELOC_LO_1_BASE_IDX … #define regMC_VM_MARC_RELOC_LO_2 … #define regMC_VM_MARC_RELOC_LO_2_BASE_IDX … #define regMC_VM_MARC_RELOC_LO_3 … #define regMC_VM_MARC_RELOC_LO_3_BASE_IDX … #define regMC_VM_MARC_RELOC_HI_0 … #define regMC_VM_MARC_RELOC_HI_0_BASE_IDX … #define regMC_VM_MARC_RELOC_HI_1 … #define regMC_VM_MARC_RELOC_HI_1_BASE_IDX … #define regMC_VM_MARC_RELOC_HI_2 … #define regMC_VM_MARC_RELOC_HI_2_BASE_IDX … #define regMC_VM_MARC_RELOC_HI_3 … #define regMC_VM_MARC_RELOC_HI_3_BASE_IDX … #define regMC_VM_MARC_LEN_LO_0 … #define regMC_VM_MARC_LEN_LO_0_BASE_IDX … #define regMC_VM_MARC_LEN_LO_1 … #define regMC_VM_MARC_LEN_LO_1_BASE_IDX … #define regMC_VM_MARC_LEN_LO_2 … #define regMC_VM_MARC_LEN_LO_2_BASE_IDX … #define regMC_VM_MARC_LEN_LO_3 … #define regMC_VM_MARC_LEN_LO_3_BASE_IDX … #define regMC_VM_MARC_LEN_HI_0 … #define regMC_VM_MARC_LEN_HI_0_BASE_IDX … #define regMC_VM_MARC_LEN_HI_1 … #define regMC_VM_MARC_LEN_HI_1_BASE_IDX … #define regMC_VM_MARC_LEN_HI_2 … #define regMC_VM_MARC_LEN_HI_2_BASE_IDX … #define regMC_VM_MARC_LEN_HI_3 … #define regMC_VM_MARC_LEN_HI_3_BASE_IDX … #define regVM_IOMMU_CONTROL_REGISTER … #define regVM_IOMMU_CONTROL_REGISTER_BASE_IDX … #define regVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER … #define regVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX … #define regVM_PCIE_ATS_CNTL … #define regVM_PCIE_ATS_CNTL_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_0 … #define regVM_PCIE_ATS_CNTL_VF_0_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_1 … #define regVM_PCIE_ATS_CNTL_VF_1_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_2 … #define regVM_PCIE_ATS_CNTL_VF_2_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_3 … #define regVM_PCIE_ATS_CNTL_VF_3_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_4 … #define regVM_PCIE_ATS_CNTL_VF_4_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_5 … #define regVM_PCIE_ATS_CNTL_VF_5_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_6 … #define regVM_PCIE_ATS_CNTL_VF_6_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_7 … #define regVM_PCIE_ATS_CNTL_VF_7_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_8 … #define regVM_PCIE_ATS_CNTL_VF_8_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_9 … #define regVM_PCIE_ATS_CNTL_VF_9_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_10 … #define regVM_PCIE_ATS_CNTL_VF_10_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_11 … #define regVM_PCIE_ATS_CNTL_VF_11_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_12 … #define regVM_PCIE_ATS_CNTL_VF_12_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_13 … #define regVM_PCIE_ATS_CNTL_VF_13_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_14 … #define regVM_PCIE_ATS_CNTL_VF_14_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_15 … #define regVM_PCIE_ATS_CNTL_VF_15_BASE_IDX … #define regMC_SHARED_ACTIVE_FCN_ID … #define regMC_SHARED_ACTIVE_FCN_ID_BASE_IDX … #define regMC_VM_XGMI_GPUIOV_ENABLE … #define regMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX … // addressBlock: xcd0_gc_pspdec // base address: 0x3f000 #define regCPG_PSP_DEBUG … #define regCPG_PSP_DEBUG_BASE_IDX … #define regCPC_PSP_DEBUG … #define regCPC_PSP_DEBUG_BASE_IDX … #define regCP_PSP_XCP_CTL … #define regCP_PSP_XCP_CTL_BASE_IDX … #define regGRBM_SEC_CNTL … #define regGRBM_SEC_CNTL_BASE_IDX … #define regGRBM_IOV_ERROR_FIFO_DATA … #define regGRBM_IOV_ERROR_FIFO_DATA_BASE_IDX … #define regGRBM_DSM_BYPASS … #define regGRBM_DSM_BYPASS_BASE_IDX … #define regGRBM_CAM_INDEX … #define regGRBM_CAM_INDEX_BASE_IDX … #define regGRBM_HYP_CAM_INDEX … #define regGRBM_HYP_CAM_INDEX_BASE_IDX … #define regGRBM_CAM_DATA … #define regGRBM_CAM_DATA_BASE_IDX … #define regGRBM_HYP_CAM_DATA … #define regGRBM_HYP_CAM_DATA_BASE_IDX … #define regRLC_FWL_FIRST_VIOL_ADDR … #define regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX … // addressBlock: sqind // base address: 0x0 #define ixSQ_DEBUG_STS_LOCAL … #define ixSQ_DEBUG_CTRL_LOCAL … #define ixSQ_WAVE_VALID_AND_IDLE … #define ixSQ_WAVE_MODE … #define ixSQ_WAVE_STATUS … #define ixSQ_WAVE_TRAPSTS … #define ixSQ_WAVE_HW_ID … #define ixSQ_WAVE_GPR_ALLOC … #define ixSQ_WAVE_LDS_ALLOC … #define ixSQ_WAVE_IB_STS … #define ixSQ_WAVE_PC_LO … #define ixSQ_WAVE_PC_HI … #define ixSQ_WAVE_INST_DW0 … #define ixSQ_WAVE_INST_DW1 … #define ixSQ_WAVE_IB_DBG0 … #define ixSQ_WAVE_IB_DBG1 … #define ixSQ_WAVE_FLUSH_IB … #define ixSQ_WAVE_TTMP0 … #define ixSQ_WAVE_TTMP1 … #define ixSQ_WAVE_TTMP2 … #define ixSQ_WAVE_TTMP3 … #define ixSQ_WAVE_TTMP4 … #define ixSQ_WAVE_TTMP5 … #define ixSQ_WAVE_TTMP6 … #define ixSQ_WAVE_TTMP7 … #define ixSQ_WAVE_TTMP8 … #define ixSQ_WAVE_TTMP9 … #define ixSQ_WAVE_TTMP10 … #define ixSQ_WAVE_TTMP11 … #define ixSQ_WAVE_TTMP12 … #define ixSQ_WAVE_TTMP13 … #define ixSQ_WAVE_TTMP14 … #define ixSQ_WAVE_TTMP15 … #define ixSQ_WAVE_M0 … #define ixSQ_WAVE_EXEC_LO … #define ixSQ_WAVE_EXEC_HI … #define ixSQ_INTERRUPT_WORD_AUTO_CTXID … #define ixSQ_INTERRUPT_WORD_AUTO_HI … #define ixSQ_INTERRUPT_WORD_AUTO_LO … #define ixSQ_INTERRUPT_WORD_CMN_CTXID … #define ixSQ_INTERRUPT_WORD_CMN_HI … #define ixSQ_INTERRUPT_WORD_WAVE_CTXID … #define ixSQ_INTERRUPT_WORD_WAVE_HI … #define ixSQ_INTERRUPT_WORD_WAVE_LO … #endif
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