// SPDX-License-Identifier: GPL-2.0-only /* * IOSF-SB MailBox Interface Driver * Copyright (c) 2013, Intel Corporation. * * The IOSF-SB is a fabric bus available on Atom based SOC's that uses a * mailbox interface (MBI) to communicate with multiple devices. This * driver implements access to this interface for those platforms that can * enumerate the device using PCI. */ #include <linux/delay.h> #include <linux/module.h> #include <linux/init.h> #include <linux/spinlock.h> #include <linux/pci.h> #include <linux/debugfs.h> #include <linux/capability.h> #include <linux/pm_qos.h> #include <linux/wait.h> #include <asm/iosf_mbi.h> #define PCI_DEVICE_ID_INTEL_BAYTRAIL … #define PCI_DEVICE_ID_INTEL_BRASWELL … #define PCI_DEVICE_ID_INTEL_QUARK_X1000 … #define PCI_DEVICE_ID_INTEL_TANGIER … static struct pci_dev *mbi_pdev; static DEFINE_SPINLOCK(iosf_mbi_lock); /**************** Generic iosf_mbi access helpers ****************/ static inline u32 iosf_mbi_form_mcr(u8 op, u8 port, u8 offset) { … } static int iosf_mbi_pci_read_mdr(u32 mcrx, u32 mcr, u32 *mdr) { … } static int iosf_mbi_pci_write_mdr(u32 mcrx, u32 mcr, u32 mdr) { … } int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr) { … } EXPORT_SYMBOL(…); int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr) { … } EXPORT_SYMBOL(…); int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask) { … } EXPORT_SYMBOL(…); bool iosf_mbi_available(void) { … } EXPORT_SYMBOL(…); /* **************** P-Unit/kernel shared I2C bus arbitration **************** * * Some Bay Trail and Cherry Trail devices have the P-Unit and us (the kernel) * share a single I2C bus to the PMIC. Below are helpers to arbitrate the * accesses between the kernel and the P-Unit. * * See arch/x86/include/asm/iosf_mbi.h for kernel-doc text for each function. */ #define SEMAPHORE_TIMEOUT … #define PUNIT_SEMAPHORE_BYT … #define PUNIT_SEMAPHORE_CHT … #define PUNIT_SEMAPHORE_BIT … #define PUNIT_SEMAPHORE_ACQUIRE … static DEFINE_MUTEX(iosf_mbi_pmic_access_mutex); static BLOCKING_NOTIFIER_HEAD(iosf_mbi_pmic_bus_access_notifier); static DECLARE_WAIT_QUEUE_HEAD(iosf_mbi_pmic_access_waitq); static u32 iosf_mbi_pmic_punit_access_count; static u32 iosf_mbi_pmic_i2c_access_count; static u32 iosf_mbi_sem_address; static unsigned long iosf_mbi_sem_acquired; static struct pm_qos_request iosf_mbi_pm_qos; void iosf_mbi_punit_acquire(void) { … } EXPORT_SYMBOL(…); void iosf_mbi_punit_release(void) { … } EXPORT_SYMBOL(…); static int iosf_mbi_get_sem(u32 *sem) { … } static void iosf_mbi_reset_semaphore(void) { … } /* * This function blocks P-Unit accesses to the PMIC I2C bus, so that kernel * I2C code, such as e.g. a fuel-gauge driver, can access it safely. * * This function may be called by I2C controller code while an I2C driver has * already blocked P-Unit accesses because it wants them blocked over multiple * i2c-transfers, for e.g. read-modify-write of an I2C client register. * * To allow safe PMIC i2c bus accesses this function takes the following steps: * * 1) Some code sends request to the P-Unit which make it access the PMIC * I2C bus. Testing has shown that the P-Unit does not check its internal * PMIC bus semaphore for these requests. Callers of these requests call * iosf_mbi_punit_acquire()/_release() around their P-Unit accesses, these * functions increase/decrease iosf_mbi_pmic_punit_access_count, so first * we wait for iosf_mbi_pmic_punit_access_count to become 0. * * 2) Check iosf_mbi_pmic_i2c_access_count, if access has already * been blocked by another caller, we only need to increment * iosf_mbi_pmic_i2c_access_count and we can skip the other steps. * * 3) Some code makes such P-Unit requests from atomic contexts where it * cannot call iosf_mbi_punit_acquire() as that may sleep. * As the second step we call a notifier chain which allows any code * needing P-Unit resources from atomic context to acquire them before * we take control over the PMIC I2C bus. * * 4) When CPU cores enter C6 or C7 the P-Unit needs to talk to the PMIC * if this happens while the kernel itself is accessing the PMIC I2C bus * the SoC hangs. * As the third step we call cpu_latency_qos_update_request() to disallow the * CPU to enter C6 or C7. * * 5) The P-Unit has a PMIC bus semaphore which we can request to stop * autonomous P-Unit tasks from accessing the PMIC I2C bus while we hold it. * As the fourth and final step we request this semaphore and wait for our * request to be acknowledged. */ int iosf_mbi_block_punit_i2c_access(void) { … } EXPORT_SYMBOL(…); void iosf_mbi_unblock_punit_i2c_access(void) { … } EXPORT_SYMBOL(…); int iosf_mbi_register_pmic_bus_access_notifier(struct notifier_block *nb) { … } EXPORT_SYMBOL(…); int iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( struct notifier_block *nb) { … } EXPORT_SYMBOL(…); int iosf_mbi_unregister_pmic_bus_access_notifier(struct notifier_block *nb) { … } EXPORT_SYMBOL(…); void iosf_mbi_assert_punit_acquired(void) { … } EXPORT_SYMBOL(…); /**************** iosf_mbi debug code ****************/ #ifdef CONFIG_IOSF_MBI_DEBUG static u32 dbg_mdr; static u32 dbg_mcr; static u32 dbg_mcrx; static int mcr_get(void *data, u64 *val) { … } static int mcr_set(void *data, u64 val) { … } DEFINE_SIMPLE_ATTRIBUTE(…); static struct dentry *iosf_dbg; static void iosf_sideband_debug_init(void) { … } static void iosf_debugfs_init(void) { … } static void iosf_debugfs_remove(void) { … } #else static inline void iosf_debugfs_init(void) { } static inline void iosf_debugfs_remove(void) { } #endif /* CONFIG_IOSF_MBI_DEBUG */ static int iosf_mbi_probe(struct pci_dev *pdev, const struct pci_device_id *dev_id) { … } static const struct pci_device_id iosf_mbi_pci_ids[] = …; MODULE_DEVICE_TABLE(pci, iosf_mbi_pci_ids); static struct pci_driver iosf_mbi_pci_driver = …; static int __init iosf_mbi_init(void) { … } static void __exit iosf_mbi_exit(void) { … } module_init(…) …; module_exit(iosf_mbi_exit); MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
Codebase Browser
linux