// SPDX-License-Identifier: GPL-2.0-only /* * Intel MID Power Management Unit (PWRMU) device driver * * Copyright (C) 2016, Intel Corporation * * Author: Andy Shevchenko <[email protected]> * * Intel MID Power Management Unit device driver handles the South Complex PCI * devices such as GPDMA, SPI, I2C, PWM, and so on. By default PCI core * modifies bits in PMCSR register in the PCI configuration space. This is not * enough on some SoCs like Intel Tangier. In such case PCI core sets a new * power state of the device in question through a PM hook registered in struct * pci_platform_pm_ops (see drivers/pci/pci-mid.c). */ #define pr_fmt(fmt) … #include <linux/delay.h> #include <linux/errno.h> #include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/export.h> #include <linux/mutex.h> #include <linux/pci.h> #include <asm/intel-mid.h> /* Registers */ #define PM_STS … #define PM_CMD … #define PM_ICS … #define PM_WKC(x) … #define PM_WKS(x) … #define PM_SSC(x) … #define PM_SSS(x) … /* Bits in PM_STS */ #define PM_STS_BUSY … /* Bits in PM_CMD */ #define PM_CMD_CMD(x) … #define PM_CMD_IOC … #define PM_CMD_CM_NOP … #define PM_CMD_CM_IMMEDIATE … #define PM_CMD_CM_DELAY … #define PM_CMD_CM_TRIGGER … /* System states */ #define PM_CMD_SYS_STATE_S5 … /* Trigger variants */ #define PM_CMD_CFG_TRIGGER_NC … /* Message to wait for TRIGGER_NC case */ #define TRIGGER_NC_MSG_2 … /* List of commands */ #define CMD_SET_CFG … /* Bits in PM_ICS */ #define PM_ICS_INT_STATUS(x) … #define PM_ICS_IE … #define PM_ICS_IP … #define PM_ICS_SW_INT_STS … /* List of interrupts */ #define INT_INVALID … #define INT_CMD_COMPLETE … #define INT_CMD_ERR … #define INT_WAKE_EVENT … #define INT_LSS_POWER_ERR … #define INT_S0iX_MSG_ERR … #define INT_NO_C6 … #define INT_TRIGGER_ERR … #define INT_INACTIVITY … /* South Complex devices */ #define LSS_MAX_SHARED_DEVS … #define LSS_MAX_DEVS … #define LSS_WS_BITS … #define LSS_PWS_BITS … /* Supported device IDs */ #define PCI_DEVICE_ID_PENWELL … #define PCI_DEVICE_ID_TANGIER … struct mid_pwr_dev { … }; struct mid_pwr { … }; static struct mid_pwr *midpwr; static u32 mid_pwr_get_state(struct mid_pwr *pwr, int reg) { … } static void mid_pwr_set_state(struct mid_pwr *pwr, int reg, u32 value) { … } static void mid_pwr_set_wake(struct mid_pwr *pwr, int reg, u32 value) { … } static void mid_pwr_interrupt_disable(struct mid_pwr *pwr) { … } static bool mid_pwr_is_busy(struct mid_pwr *pwr) { … } /* Wait 500ms that the latest PWRMU command finished */ static int mid_pwr_wait(struct mid_pwr *pwr) { … } static int mid_pwr_wait_for_cmd(struct mid_pwr *pwr, u8 cmd) { … } static int __update_power_state(struct mid_pwr *pwr, int reg, int bit, int new) { … } static pci_power_t __find_weakest_power_state(struct mid_pwr_dev *lss, struct pci_dev *pdev, pci_power_t state) { … } static int __set_power_state(struct mid_pwr *pwr, struct pci_dev *pdev, pci_power_t state, int id, int reg, int bit) { … } static int mid_pwr_set_power_state(struct mid_pwr *pwr, struct pci_dev *pdev, pci_power_t state) { … } int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) { … } pci_power_t intel_mid_pci_get_power_state(struct pci_dev *pdev) { … } void intel_mid_pwr_power_off(void) { … } int intel_mid_pwr_get_lss_id(struct pci_dev *pdev) { … } static irqreturn_t mid_pwr_irq_handler(int irq, void *dev_id) { … } struct mid_pwr_device_info { … }; static int mid_pwr_probe(struct pci_dev *pdev, const struct pci_device_id *id) { … } static int mid_set_initial_state(struct mid_pwr *pwr, const u32 *states) { … } static int pnw_set_initial_state(struct mid_pwr *pwr) { … } static int tng_set_initial_state(struct mid_pwr *pwr) { … } static const struct mid_pwr_device_info pnw_info = …; static const struct mid_pwr_device_info tng_info = …; /* This table should be in sync with the one in drivers/pci/pci-mid.c */ static const struct pci_device_id mid_pwr_pci_ids[] = …; static struct pci_driver mid_pwr_pci_driver = …; builtin_pci_driver(…) …;
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