/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef _mmhub_1_8_0_OFFSET_HEADER #define _mmhub_1_8_0_OFFSET_HEADER // addressBlock: aid_mmhub_dagb_dagbdec0 // base address: 0x60000 #define regDAGB0_RDCLI0 … #define regDAGB0_RDCLI0_BASE_IDX … #define regDAGB0_RDCLI1 … #define regDAGB0_RDCLI1_BASE_IDX … #define regDAGB0_RDCLI2 … #define regDAGB0_RDCLI2_BASE_IDX … #define regDAGB0_RDCLI3 … #define regDAGB0_RDCLI3_BASE_IDX … #define regDAGB0_RDCLI4 … #define regDAGB0_RDCLI4_BASE_IDX … #define regDAGB0_RDCLI5 … #define regDAGB0_RDCLI5_BASE_IDX … #define regDAGB0_RDCLI6 … #define regDAGB0_RDCLI6_BASE_IDX … #define regDAGB0_RDCLI7 … #define regDAGB0_RDCLI7_BASE_IDX … #define regDAGB0_RDCLI8 … #define regDAGB0_RDCLI8_BASE_IDX … #define regDAGB0_RDCLI9 … #define regDAGB0_RDCLI9_BASE_IDX … #define regDAGB0_RDCLI10 … #define regDAGB0_RDCLI10_BASE_IDX … #define regDAGB0_RDCLI11 … #define regDAGB0_RDCLI11_BASE_IDX … #define regDAGB0_RDCLI12 … #define regDAGB0_RDCLI12_BASE_IDX … #define regDAGB0_RDCLI13 … #define regDAGB0_RDCLI13_BASE_IDX … #define regDAGB0_RDCLI14 … #define regDAGB0_RDCLI14_BASE_IDX … #define regDAGB0_RDCLI15 … #define regDAGB0_RDCLI15_BASE_IDX … #define regDAGB0_RD_CNTL … #define regDAGB0_RD_CNTL_BASE_IDX … #define regDAGB0_RD_GMI_CNTL … #define regDAGB0_RD_GMI_CNTL_BASE_IDX … #define regDAGB0_RD_ADDR_DAGB … #define regDAGB0_RD_ADDR_DAGB_BASE_IDX … #define regDAGB0_RD_OUTPUT_DAGB_MAX_BURST … #define regDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define regDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER … #define regDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define regDAGB0_RD_CGTT_CLK_CTRL … #define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL … #define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB0_ATCVM_RD_CGTT_CLK_CTRL … #define regDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB0_RD_ADDR_DAGB_MAX_BURST0 … #define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 … #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define regDAGB0_RD_ADDR_DAGB_MAX_BURST1 … #define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 … #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define regDAGB0_RD_VC0_CNTL … #define regDAGB0_RD_VC0_CNTL_BASE_IDX … #define regDAGB0_RD_VC1_CNTL … #define regDAGB0_RD_VC1_CNTL_BASE_IDX … #define regDAGB0_RD_VC2_CNTL … #define regDAGB0_RD_VC2_CNTL_BASE_IDX … #define regDAGB0_RD_VC3_CNTL … #define regDAGB0_RD_VC3_CNTL_BASE_IDX … #define regDAGB0_RD_VC4_CNTL … #define regDAGB0_RD_VC4_CNTL_BASE_IDX … #define regDAGB0_RD_VC5_CNTL … #define regDAGB0_RD_VC5_CNTL_BASE_IDX … #define regDAGB0_RD_VC6_CNTL … #define regDAGB0_RD_VC6_CNTL_BASE_IDX … #define regDAGB0_RD_VC7_CNTL … #define regDAGB0_RD_VC7_CNTL_BASE_IDX … #define regDAGB0_RD_CNTL_MISC … #define regDAGB0_RD_CNTL_MISC_BASE_IDX … #define regDAGB0_RD_TLB_CREDIT … #define regDAGB0_RD_TLB_CREDIT_BASE_IDX … #define regDAGB0_RD_RDRET_CREDIT_CNTL … #define regDAGB0_RD_RDRET_CREDIT_CNTL_BASE_IDX … #define regDAGB0_RD_RDRET_CREDIT_CNTL2 … #define regDAGB0_RD_RDRET_CREDIT_CNTL2_BASE_IDX … #define regDAGB0_RDCLI_ASK_PENDING … #define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX … #define regDAGB0_RDCLI_GO_PENDING … #define regDAGB0_RDCLI_GO_PENDING_BASE_IDX … #define regDAGB0_RDCLI_GBLSEND_PENDING … #define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX … #define regDAGB0_RDCLI_TLB_PENDING … #define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX … #define regDAGB0_RDCLI_OARB_PENDING … #define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX … #define regDAGB0_RDCLI_OSD_PENDING … #define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX … #define regDAGB0_RDCLI_NOALLOC_OVERRIDE … #define regDAGB0_RDCLI_NOALLOC_OVERRIDE_BASE_IDX … #define regDAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE … #define regDAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX … #define regDAGB0_WRCLI0 … #define regDAGB0_WRCLI0_BASE_IDX … #define regDAGB0_WRCLI1 … #define regDAGB0_WRCLI1_BASE_IDX … #define regDAGB0_WRCLI2 … #define regDAGB0_WRCLI2_BASE_IDX … #define regDAGB0_WRCLI3 … #define regDAGB0_WRCLI3_BASE_IDX … #define regDAGB0_WRCLI4 … #define regDAGB0_WRCLI4_BASE_IDX … #define regDAGB0_WRCLI5 … #define regDAGB0_WRCLI5_BASE_IDX … #define regDAGB0_WRCLI6 … #define regDAGB0_WRCLI6_BASE_IDX … #define regDAGB0_WRCLI7 … #define regDAGB0_WRCLI7_BASE_IDX … #define regDAGB0_WRCLI8 … #define regDAGB0_WRCLI8_BASE_IDX … #define regDAGB0_WRCLI9 … #define regDAGB0_WRCLI9_BASE_IDX … #define regDAGB0_WRCLI10 … #define regDAGB0_WRCLI10_BASE_IDX … #define regDAGB0_WRCLI11 … #define regDAGB0_WRCLI11_BASE_IDX … #define regDAGB0_WRCLI12 … #define regDAGB0_WRCLI12_BASE_IDX … #define regDAGB0_WRCLI13 … #define regDAGB0_WRCLI13_BASE_IDX … #define regDAGB0_WRCLI14 … #define regDAGB0_WRCLI14_BASE_IDX … #define regDAGB0_WRCLI15 … #define regDAGB0_WRCLI15_BASE_IDX … #define regDAGB0_WR_CNTL … #define regDAGB0_WR_CNTL_BASE_IDX … #define regDAGB0_WR_GMI_CNTL … #define regDAGB0_WR_GMI_CNTL_BASE_IDX … #define regDAGB0_WR_ADDR_DAGB … #define regDAGB0_WR_ADDR_DAGB_BASE_IDX … #define regDAGB0_WR_OUTPUT_DAGB_MAX_BURST … #define regDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define regDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER … #define regDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define regDAGB0_WR_CGTT_CLK_CTRL … #define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL … #define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB0_ATCVM_WR_CGTT_CLK_CTRL … #define regDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB0_WR_ADDR_DAGB_MAX_BURST0 … #define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 … #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define regDAGB0_WR_ADDR_DAGB_MAX_BURST1 … #define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 … #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define regDAGB0_WR_DATA_DAGB … #define regDAGB0_WR_DATA_DAGB_BASE_IDX … #define regDAGB0_WR_DATA_DAGB_MAX_BURST0 … #define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX … #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 … #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX … #define regDAGB0_WR_DATA_DAGB_MAX_BURST1 … #define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX … #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 … #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX … #define regDAGB0_WR_VC0_CNTL … #define regDAGB0_WR_VC0_CNTL_BASE_IDX … #define regDAGB0_WR_VC1_CNTL … #define regDAGB0_WR_VC1_CNTL_BASE_IDX … #define regDAGB0_WR_VC2_CNTL … #define regDAGB0_WR_VC2_CNTL_BASE_IDX … #define regDAGB0_WR_VC3_CNTL … #define regDAGB0_WR_VC3_CNTL_BASE_IDX … #define regDAGB0_WR_VC4_CNTL … #define regDAGB0_WR_VC4_CNTL_BASE_IDX … #define regDAGB0_WR_VC5_CNTL … #define regDAGB0_WR_VC5_CNTL_BASE_IDX … #define regDAGB0_WR_VC6_CNTL … #define regDAGB0_WR_VC6_CNTL_BASE_IDX … #define regDAGB0_WR_VC7_CNTL … #define regDAGB0_WR_VC7_CNTL_BASE_IDX … #define regDAGB0_WR_CNTL_MISC … #define regDAGB0_WR_CNTL_MISC_BASE_IDX … #define regDAGB0_WR_TLB_CREDIT … #define regDAGB0_WR_TLB_CREDIT_BASE_IDX … #define regDAGB0_WR_DATA_CREDIT … #define regDAGB0_WR_DATA_CREDIT_BASE_IDX … #define regDAGB0_WR_MISC_CREDIT … #define regDAGB0_WR_MISC_CREDIT_BASE_IDX … #define regDAGB0_WR_OSD_CREDIT_CNTL1 … #define regDAGB0_WR_OSD_CREDIT_CNTL1_BASE_IDX … #define regDAGB0_WR_OSD_CREDIT_CNTL2 … #define regDAGB0_WR_OSD_CREDIT_CNTL2_BASE_IDX … #define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 … #define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX … #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE … #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX … #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE … #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX … #define regDAGB0_WRCLI_ASK_PENDING … #define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX … #define regDAGB0_WRCLI_GO_PENDING … #define regDAGB0_WRCLI_GO_PENDING_BASE_IDX … #define regDAGB0_WRCLI_GBLSEND_PENDING … #define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX … #define regDAGB0_WRCLI_TLB_PENDING … #define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX … #define regDAGB0_WRCLI_OARB_PENDING … #define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX … #define regDAGB0_WRCLI_OSD_PENDING … #define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX … #define regDAGB0_WRCLI_DBUS_ASK_PENDING … #define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX … #define regDAGB0_WRCLI_DBUS_GO_PENDING … #define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX … #define regDAGB0_WRCLI_NOALLOC_OVERRIDE … #define regDAGB0_WRCLI_NOALLOC_OVERRIDE_BASE_IDX … #define regDAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE … #define regDAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX … #define regDAGB0_DAGB_DLY … #define regDAGB0_DAGB_DLY_BASE_IDX … #define regDAGB0_CNTL_MISC … #define regDAGB0_CNTL_MISC_BASE_IDX … #define regDAGB0_CNTL_MISC2 … #define regDAGB0_CNTL_MISC2_BASE_IDX … #define regDAGB0_FATAL_ERROR_CNTL … #define regDAGB0_FATAL_ERROR_CNTL_BASE_IDX … #define regDAGB0_FATAL_ERROR_CLEAR … #define regDAGB0_FATAL_ERROR_CLEAR_BASE_IDX … #define regDAGB0_FATAL_ERROR_STATUS0 … #define regDAGB0_FATAL_ERROR_STATUS0_BASE_IDX … #define regDAGB0_FATAL_ERROR_STATUS1 … #define regDAGB0_FATAL_ERROR_STATUS1_BASE_IDX … #define regDAGB0_FATAL_ERROR_STATUS2 … #define regDAGB0_FATAL_ERROR_STATUS2_BASE_IDX … #define regDAGB0_FATAL_ERROR_STATUS3 … #define regDAGB0_FATAL_ERROR_STATUS3_BASE_IDX … #define regDAGB0_FIFO_EMPTY … #define regDAGB0_FIFO_EMPTY_BASE_IDX … #define regDAGB0_FIFO_FULL … #define regDAGB0_FIFO_FULL_BASE_IDX … #define regDAGB0_WR_CREDITS_FULL … #define regDAGB0_WR_CREDITS_FULL_BASE_IDX … #define regDAGB0_RD_CREDITS_FULL … #define regDAGB0_RD_CREDITS_FULL_BASE_IDX … #define regDAGB0_PERFCOUNTER_LO … #define regDAGB0_PERFCOUNTER_LO_BASE_IDX … #define regDAGB0_PERFCOUNTER_HI … #define regDAGB0_PERFCOUNTER_HI_BASE_IDX … #define regDAGB0_PERFCOUNTER0_CFG … #define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX … #define regDAGB0_PERFCOUNTER1_CFG … #define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX … #define regDAGB0_PERFCOUNTER2_CFG … #define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX … #define regDAGB0_PERFCOUNTER_RSLT_CNTL … #define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define regDAGB0_L1TLB_REG_RW … #define regDAGB0_L1TLB_REG_RW_BASE_IDX … // addressBlock: aid_mmhub_dagb_dagbdec1 // base address: 0x60200 #define regDAGB1_RDCLI0 … #define regDAGB1_RDCLI0_BASE_IDX … #define regDAGB1_RDCLI1 … #define regDAGB1_RDCLI1_BASE_IDX … #define regDAGB1_RDCLI2 … #define regDAGB1_RDCLI2_BASE_IDX … #define regDAGB1_RDCLI3 … #define regDAGB1_RDCLI3_BASE_IDX … #define regDAGB1_RDCLI4 … #define regDAGB1_RDCLI4_BASE_IDX … #define regDAGB1_RDCLI5 … #define regDAGB1_RDCLI5_BASE_IDX … #define regDAGB1_RDCLI6 … #define regDAGB1_RDCLI6_BASE_IDX … #define regDAGB1_RDCLI7 … #define regDAGB1_RDCLI7_BASE_IDX … #define regDAGB1_RDCLI8 … #define regDAGB1_RDCLI8_BASE_IDX … #define regDAGB1_RDCLI9 … #define regDAGB1_RDCLI9_BASE_IDX … #define regDAGB1_RDCLI10 … #define regDAGB1_RDCLI10_BASE_IDX … #define regDAGB1_RDCLI11 … #define regDAGB1_RDCLI11_BASE_IDX … #define regDAGB1_RDCLI12 … #define regDAGB1_RDCLI12_BASE_IDX … #define regDAGB1_RDCLI13 … #define regDAGB1_RDCLI13_BASE_IDX … #define regDAGB1_RDCLI14 … #define regDAGB1_RDCLI14_BASE_IDX … #define regDAGB1_RDCLI15 … #define regDAGB1_RDCLI15_BASE_IDX … #define regDAGB1_RD_CNTL … #define regDAGB1_RD_CNTL_BASE_IDX … #define regDAGB1_RD_GMI_CNTL … #define regDAGB1_RD_GMI_CNTL_BASE_IDX … #define regDAGB1_RD_ADDR_DAGB … #define regDAGB1_RD_ADDR_DAGB_BASE_IDX … #define regDAGB1_RD_OUTPUT_DAGB_MAX_BURST … #define regDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define regDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER … #define regDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define regDAGB1_RD_CGTT_CLK_CTRL … #define regDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL … #define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB1_ATCVM_RD_CGTT_CLK_CTRL … #define regDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB1_RD_ADDR_DAGB_MAX_BURST0 … #define regDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 … #define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define regDAGB1_RD_ADDR_DAGB_MAX_BURST1 … #define regDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 … #define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define regDAGB1_RD_VC0_CNTL … #define regDAGB1_RD_VC0_CNTL_BASE_IDX … #define regDAGB1_RD_VC1_CNTL … #define regDAGB1_RD_VC1_CNTL_BASE_IDX … #define regDAGB1_RD_VC2_CNTL … #define regDAGB1_RD_VC2_CNTL_BASE_IDX … #define regDAGB1_RD_VC3_CNTL … #define regDAGB1_RD_VC3_CNTL_BASE_IDX … #define regDAGB1_RD_VC4_CNTL … #define regDAGB1_RD_VC4_CNTL_BASE_IDX … #define regDAGB1_RD_VC5_CNTL … #define regDAGB1_RD_VC5_CNTL_BASE_IDX … #define regDAGB1_RD_VC6_CNTL … #define regDAGB1_RD_VC6_CNTL_BASE_IDX … #define regDAGB1_RD_VC7_CNTL … #define regDAGB1_RD_VC7_CNTL_BASE_IDX … #define regDAGB1_RD_CNTL_MISC … #define regDAGB1_RD_CNTL_MISC_BASE_IDX … #define regDAGB1_RD_TLB_CREDIT … #define regDAGB1_RD_TLB_CREDIT_BASE_IDX … #define regDAGB1_RD_RDRET_CREDIT_CNTL … #define regDAGB1_RD_RDRET_CREDIT_CNTL_BASE_IDX … #define regDAGB1_RD_RDRET_CREDIT_CNTL2 … #define regDAGB1_RD_RDRET_CREDIT_CNTL2_BASE_IDX … #define regDAGB1_RDCLI_ASK_PENDING … #define regDAGB1_RDCLI_ASK_PENDING_BASE_IDX … #define regDAGB1_RDCLI_GO_PENDING … #define regDAGB1_RDCLI_GO_PENDING_BASE_IDX … #define regDAGB1_RDCLI_GBLSEND_PENDING … #define regDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX … #define regDAGB1_RDCLI_TLB_PENDING … #define regDAGB1_RDCLI_TLB_PENDING_BASE_IDX … #define regDAGB1_RDCLI_OARB_PENDING … #define regDAGB1_RDCLI_OARB_PENDING_BASE_IDX … #define regDAGB1_RDCLI_OSD_PENDING … #define regDAGB1_RDCLI_OSD_PENDING_BASE_IDX … #define regDAGB1_RDCLI_NOALLOC_OVERRIDE … #define regDAGB1_RDCLI_NOALLOC_OVERRIDE_BASE_IDX … #define regDAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE … #define regDAGB1_RDCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX … #define regDAGB1_WRCLI0 … #define regDAGB1_WRCLI0_BASE_IDX … #define regDAGB1_WRCLI1 … #define regDAGB1_WRCLI1_BASE_IDX … #define regDAGB1_WRCLI2 … #define regDAGB1_WRCLI2_BASE_IDX … #define regDAGB1_WRCLI3 … #define regDAGB1_WRCLI3_BASE_IDX … #define regDAGB1_WRCLI4 … #define regDAGB1_WRCLI4_BASE_IDX … #define regDAGB1_WRCLI5 … #define regDAGB1_WRCLI5_BASE_IDX … #define regDAGB1_WRCLI6 … #define regDAGB1_WRCLI6_BASE_IDX … #define regDAGB1_WRCLI7 … #define regDAGB1_WRCLI7_BASE_IDX … #define regDAGB1_WRCLI8 … #define regDAGB1_WRCLI8_BASE_IDX … #define regDAGB1_WRCLI9 … #define regDAGB1_WRCLI9_BASE_IDX … #define regDAGB1_WRCLI10 … #define regDAGB1_WRCLI10_BASE_IDX … #define regDAGB1_WRCLI11 … #define regDAGB1_WRCLI11_BASE_IDX … #define regDAGB1_WRCLI12 … #define regDAGB1_WRCLI12_BASE_IDX … #define regDAGB1_WRCLI13 … #define regDAGB1_WRCLI13_BASE_IDX … #define regDAGB1_WRCLI14 … #define regDAGB1_WRCLI14_BASE_IDX … #define regDAGB1_WRCLI15 … #define regDAGB1_WRCLI15_BASE_IDX … #define regDAGB1_WR_CNTL … #define regDAGB1_WR_CNTL_BASE_IDX … #define regDAGB1_WR_GMI_CNTL … #define regDAGB1_WR_GMI_CNTL_BASE_IDX … #define regDAGB1_WR_ADDR_DAGB … #define regDAGB1_WR_ADDR_DAGB_BASE_IDX … #define regDAGB1_WR_OUTPUT_DAGB_MAX_BURST … #define regDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define regDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER … #define regDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define regDAGB1_WR_CGTT_CLK_CTRL … #define regDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB1_L1TLB_WR_CGTT_CLK_CTRL … #define regDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB1_ATCVM_WR_CGTT_CLK_CTRL … #define regDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB1_WR_ADDR_DAGB_MAX_BURST0 … #define regDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 … #define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define regDAGB1_WR_ADDR_DAGB_MAX_BURST1 … #define regDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 … #define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define regDAGB1_WR_DATA_DAGB … #define regDAGB1_WR_DATA_DAGB_BASE_IDX … #define regDAGB1_WR_DATA_DAGB_MAX_BURST0 … #define regDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX … #define regDAGB1_WR_DATA_DAGB_LAZY_TIMER0 … #define regDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX … #define regDAGB1_WR_DATA_DAGB_MAX_BURST1 … #define regDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX … #define regDAGB1_WR_DATA_DAGB_LAZY_TIMER1 … #define regDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX … #define regDAGB1_WR_VC0_CNTL … #define regDAGB1_WR_VC0_CNTL_BASE_IDX … #define regDAGB1_WR_VC1_CNTL … #define regDAGB1_WR_VC1_CNTL_BASE_IDX … #define regDAGB1_WR_VC2_CNTL … #define regDAGB1_WR_VC2_CNTL_BASE_IDX … #define regDAGB1_WR_VC3_CNTL … #define regDAGB1_WR_VC3_CNTL_BASE_IDX … #define regDAGB1_WR_VC4_CNTL … #define regDAGB1_WR_VC4_CNTL_BASE_IDX … #define regDAGB1_WR_VC5_CNTL … #define regDAGB1_WR_VC5_CNTL_BASE_IDX … #define regDAGB1_WR_VC6_CNTL … #define regDAGB1_WR_VC6_CNTL_BASE_IDX … #define regDAGB1_WR_VC7_CNTL … #define regDAGB1_WR_VC7_CNTL_BASE_IDX … #define regDAGB1_WR_CNTL_MISC … #define regDAGB1_WR_CNTL_MISC_BASE_IDX … #define regDAGB1_WR_TLB_CREDIT … #define regDAGB1_WR_TLB_CREDIT_BASE_IDX … #define regDAGB1_WR_DATA_CREDIT … #define regDAGB1_WR_DATA_CREDIT_BASE_IDX … #define regDAGB1_WR_MISC_CREDIT … #define regDAGB1_WR_MISC_CREDIT_BASE_IDX … #define regDAGB1_WR_OSD_CREDIT_CNTL1 … #define regDAGB1_WR_OSD_CREDIT_CNTL1_BASE_IDX … #define regDAGB1_WR_OSD_CREDIT_CNTL2 … #define regDAGB1_WR_OSD_CREDIT_CNTL2_BASE_IDX … #define regDAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1 … #define regDAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX … #define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE … #define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX … #define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE … #define regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX … #define regDAGB1_WRCLI_ASK_PENDING … #define regDAGB1_WRCLI_ASK_PENDING_BASE_IDX … #define regDAGB1_WRCLI_GO_PENDING … #define regDAGB1_WRCLI_GO_PENDING_BASE_IDX … #define regDAGB1_WRCLI_GBLSEND_PENDING … #define regDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX … #define regDAGB1_WRCLI_TLB_PENDING … #define regDAGB1_WRCLI_TLB_PENDING_BASE_IDX … #define regDAGB1_WRCLI_OARB_PENDING … #define regDAGB1_WRCLI_OARB_PENDING_BASE_IDX … #define regDAGB1_WRCLI_OSD_PENDING … #define regDAGB1_WRCLI_OSD_PENDING_BASE_IDX … #define regDAGB1_WRCLI_DBUS_ASK_PENDING … #define regDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX … #define regDAGB1_WRCLI_DBUS_GO_PENDING … #define regDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX … #define regDAGB1_DAGB_DLY … #define regDAGB1_DAGB_DLY_BASE_IDX … #define regDAGB1_CNTL_MISC … #define regDAGB1_CNTL_MISC_BASE_IDX … #define regDAGB1_CNTL_MISC2 … #define regDAGB1_CNTL_MISC2_BASE_IDX … #define regDAGB1_FATAL_ERROR_CNTL … #define regDAGB1_FATAL_ERROR_CNTL_BASE_IDX … #define regDAGB1_FATAL_ERROR_CLEAR … #define regDAGB1_FATAL_ERROR_CLEAR_BASE_IDX … #define regDAGB1_FATAL_ERROR_STATUS0 … #define regDAGB1_FATAL_ERROR_STATUS0_BASE_IDX … #define regDAGB1_FATAL_ERROR_STATUS1 … #define regDAGB1_FATAL_ERROR_STATUS1_BASE_IDX … #define regDAGB1_FATAL_ERROR_STATUS2 … #define regDAGB1_FATAL_ERROR_STATUS2_BASE_IDX … #define regDAGB1_FATAL_ERROR_STATUS3 … #define regDAGB1_FATAL_ERROR_STATUS3_BASE_IDX … #define regDAGB1_FIFO_EMPTY … #define regDAGB1_FIFO_EMPTY_BASE_IDX … #define regDAGB1_FIFO_FULL … #define regDAGB1_FIFO_FULL_BASE_IDX … #define regDAGB1_WR_CREDITS_FULL … #define regDAGB1_WR_CREDITS_FULL_BASE_IDX … #define regDAGB1_RD_CREDITS_FULL … #define regDAGB1_RD_CREDITS_FULL_BASE_IDX … #define regDAGB1_PERFCOUNTER_LO … #define regDAGB1_PERFCOUNTER_LO_BASE_IDX … #define regDAGB1_PERFCOUNTER_HI … #define regDAGB1_PERFCOUNTER_HI_BASE_IDX … #define regDAGB1_PERFCOUNTER0_CFG … #define regDAGB1_PERFCOUNTER0_CFG_BASE_IDX … #define regDAGB1_PERFCOUNTER1_CFG … #define regDAGB1_PERFCOUNTER1_CFG_BASE_IDX … #define regDAGB1_PERFCOUNTER2_CFG … #define regDAGB1_PERFCOUNTER2_CFG_BASE_IDX … #define regDAGB1_PERFCOUNTER_RSLT_CNTL … #define regDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define regDAGB1_L1TLB_REG_RW … #define regDAGB1_L1TLB_REG_RW_BASE_IDX … // addressBlock: aid_mmhub_dagb_dagbdec2 // base address: 0x60400 #define regDAGB2_RDCLI0 … #define regDAGB2_RDCLI0_BASE_IDX … #define regDAGB2_RDCLI1 … #define regDAGB2_RDCLI1_BASE_IDX … #define regDAGB2_RDCLI2 … #define regDAGB2_RDCLI2_BASE_IDX … #define regDAGB2_RDCLI3 … #define regDAGB2_RDCLI3_BASE_IDX … #define regDAGB2_RDCLI4 … #define regDAGB2_RDCLI4_BASE_IDX … #define regDAGB2_RDCLI5 … #define regDAGB2_RDCLI5_BASE_IDX … #define regDAGB2_RDCLI6 … #define regDAGB2_RDCLI6_BASE_IDX … #define regDAGB2_RDCLI7 … #define regDAGB2_RDCLI7_BASE_IDX … #define regDAGB2_RDCLI8 … #define regDAGB2_RDCLI8_BASE_IDX … #define regDAGB2_RDCLI9 … #define regDAGB2_RDCLI9_BASE_IDX … #define regDAGB2_RDCLI10 … #define regDAGB2_RDCLI10_BASE_IDX … #define regDAGB2_RDCLI11 … #define regDAGB2_RDCLI11_BASE_IDX … #define regDAGB2_RDCLI12 … #define regDAGB2_RDCLI12_BASE_IDX … #define regDAGB2_RDCLI13 … #define regDAGB2_RDCLI13_BASE_IDX … #define regDAGB2_RDCLI14 … #define regDAGB2_RDCLI14_BASE_IDX … #define regDAGB2_RDCLI15 … #define regDAGB2_RDCLI15_BASE_IDX … #define regDAGB2_RD_CNTL … #define regDAGB2_RD_CNTL_BASE_IDX … #define regDAGB2_RD_GMI_CNTL … #define regDAGB2_RD_GMI_CNTL_BASE_IDX … #define regDAGB2_RD_ADDR_DAGB … #define regDAGB2_RD_ADDR_DAGB_BASE_IDX … #define regDAGB2_RD_OUTPUT_DAGB_MAX_BURST … #define regDAGB2_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define regDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER … #define regDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define regDAGB2_RD_CGTT_CLK_CTRL … #define regDAGB2_RD_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB2_L1TLB_RD_CGTT_CLK_CTRL … #define regDAGB2_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB2_ATCVM_RD_CGTT_CLK_CTRL … #define regDAGB2_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB2_RD_ADDR_DAGB_MAX_BURST0 … #define regDAGB2_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER0 … #define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define regDAGB2_RD_ADDR_DAGB_MAX_BURST1 … #define regDAGB2_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER1 … #define regDAGB2_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define regDAGB2_RD_VC0_CNTL … #define regDAGB2_RD_VC0_CNTL_BASE_IDX … #define regDAGB2_RD_VC1_CNTL … #define regDAGB2_RD_VC1_CNTL_BASE_IDX … #define regDAGB2_RD_VC2_CNTL … #define regDAGB2_RD_VC2_CNTL_BASE_IDX … #define regDAGB2_RD_VC3_CNTL … #define regDAGB2_RD_VC3_CNTL_BASE_IDX … #define regDAGB2_RD_VC4_CNTL … #define regDAGB2_RD_VC4_CNTL_BASE_IDX … #define regDAGB2_RD_VC5_CNTL … #define regDAGB2_RD_VC5_CNTL_BASE_IDX … #define regDAGB2_RD_VC6_CNTL … #define regDAGB2_RD_VC6_CNTL_BASE_IDX … #define regDAGB2_RD_VC7_CNTL … #define regDAGB2_RD_VC7_CNTL_BASE_IDX … #define regDAGB2_RD_CNTL_MISC … #define regDAGB2_RD_CNTL_MISC_BASE_IDX … #define regDAGB2_RD_TLB_CREDIT … #define regDAGB2_RD_TLB_CREDIT_BASE_IDX … #define regDAGB2_RD_RDRET_CREDIT_CNTL … #define regDAGB2_RD_RDRET_CREDIT_CNTL_BASE_IDX … #define regDAGB2_RD_RDRET_CREDIT_CNTL2 … #define regDAGB2_RD_RDRET_CREDIT_CNTL2_BASE_IDX … #define regDAGB2_RDCLI_ASK_PENDING … #define regDAGB2_RDCLI_ASK_PENDING_BASE_IDX … #define regDAGB2_RDCLI_GO_PENDING … #define regDAGB2_RDCLI_GO_PENDING_BASE_IDX … #define regDAGB2_RDCLI_GBLSEND_PENDING … #define regDAGB2_RDCLI_GBLSEND_PENDING_BASE_IDX … #define regDAGB2_RDCLI_TLB_PENDING … #define regDAGB2_RDCLI_TLB_PENDING_BASE_IDX … #define regDAGB2_RDCLI_OARB_PENDING … #define regDAGB2_RDCLI_OARB_PENDING_BASE_IDX … #define regDAGB2_RDCLI_OSD_PENDING … #define regDAGB2_RDCLI_OSD_PENDING_BASE_IDX … #define regDAGB2_WRCLI0 … #define regDAGB2_WRCLI0_BASE_IDX … #define regDAGB2_WRCLI1 … #define regDAGB2_WRCLI1_BASE_IDX … #define regDAGB2_WRCLI2 … #define regDAGB2_WRCLI2_BASE_IDX … #define regDAGB2_WRCLI3 … #define regDAGB2_WRCLI3_BASE_IDX … #define regDAGB2_WRCLI4 … #define regDAGB2_WRCLI4_BASE_IDX … #define regDAGB2_WRCLI5 … #define regDAGB2_WRCLI5_BASE_IDX … #define regDAGB2_WRCLI6 … #define regDAGB2_WRCLI6_BASE_IDX … #define regDAGB2_WRCLI7 … #define regDAGB2_WRCLI7_BASE_IDX … #define regDAGB2_WRCLI8 … #define regDAGB2_WRCLI8_BASE_IDX … #define regDAGB2_WRCLI9 … #define regDAGB2_WRCLI9_BASE_IDX … #define regDAGB2_WRCLI10 … #define regDAGB2_WRCLI10_BASE_IDX … #define regDAGB2_WRCLI11 … #define regDAGB2_WRCLI11_BASE_IDX … #define regDAGB2_WRCLI12 … #define regDAGB2_WRCLI12_BASE_IDX … #define regDAGB2_WRCLI13 … #define regDAGB2_WRCLI13_BASE_IDX … #define regDAGB2_WRCLI14 … #define regDAGB2_WRCLI14_BASE_IDX … #define regDAGB2_WRCLI15 … #define regDAGB2_WRCLI15_BASE_IDX … #define regDAGB2_WR_CNTL … #define regDAGB2_WR_CNTL_BASE_IDX … #define regDAGB2_WR_GMI_CNTL … #define regDAGB2_WR_GMI_CNTL_BASE_IDX … #define regDAGB2_WR_ADDR_DAGB … #define regDAGB2_WR_ADDR_DAGB_BASE_IDX … #define regDAGB2_WR_OUTPUT_DAGB_MAX_BURST … #define regDAGB2_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define regDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER … #define regDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define regDAGB2_WR_CGTT_CLK_CTRL … #define regDAGB2_WR_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB2_L1TLB_WR_CGTT_CLK_CTRL … #define regDAGB2_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB2_ATCVM_WR_CGTT_CLK_CTRL … #define regDAGB2_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB2_WR_ADDR_DAGB_MAX_BURST0 … #define regDAGB2_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER0 … #define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define regDAGB2_WR_ADDR_DAGB_MAX_BURST1 … #define regDAGB2_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER1 … #define regDAGB2_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define regDAGB2_WR_DATA_DAGB … #define regDAGB2_WR_DATA_DAGB_BASE_IDX … #define regDAGB2_WR_DATA_DAGB_MAX_BURST0 … #define regDAGB2_WR_DATA_DAGB_MAX_BURST0_BASE_IDX … #define regDAGB2_WR_DATA_DAGB_LAZY_TIMER0 … #define regDAGB2_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX … #define regDAGB2_WR_DATA_DAGB_MAX_BURST1 … #define regDAGB2_WR_DATA_DAGB_MAX_BURST1_BASE_IDX … #define regDAGB2_WR_DATA_DAGB_LAZY_TIMER1 … #define regDAGB2_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX … #define regDAGB2_WR_VC0_CNTL … #define regDAGB2_WR_VC0_CNTL_BASE_IDX … #define regDAGB2_WR_VC1_CNTL … #define regDAGB2_WR_VC1_CNTL_BASE_IDX … #define regDAGB2_WR_VC2_CNTL … #define regDAGB2_WR_VC2_CNTL_BASE_IDX … #define regDAGB2_WR_VC3_CNTL … #define regDAGB2_WR_VC3_CNTL_BASE_IDX … #define regDAGB2_WR_VC4_CNTL … #define regDAGB2_WR_VC4_CNTL_BASE_IDX … #define regDAGB2_WR_VC5_CNTL … #define regDAGB2_WR_VC5_CNTL_BASE_IDX … #define regDAGB2_WR_VC6_CNTL … #define regDAGB2_WR_VC6_CNTL_BASE_IDX … #define regDAGB2_WR_VC7_CNTL … #define regDAGB2_WR_VC7_CNTL_BASE_IDX … #define regDAGB2_WR_CNTL_MISC … #define regDAGB2_WR_CNTL_MISC_BASE_IDX … #define regDAGB2_WR_TLB_CREDIT … #define regDAGB2_WR_TLB_CREDIT_BASE_IDX … #define regDAGB2_WR_DATA_CREDIT … #define regDAGB2_WR_DATA_CREDIT_BASE_IDX … #define regDAGB2_WR_MISC_CREDIT … #define regDAGB2_WR_MISC_CREDIT_BASE_IDX … #define regDAGB2_WR_OSD_CREDIT_CNTL1 … #define regDAGB2_WR_OSD_CREDIT_CNTL1_BASE_IDX … #define regDAGB2_WR_OSD_CREDIT_CNTL2 … #define regDAGB2_WR_OSD_CREDIT_CNTL2_BASE_IDX … #define regDAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1 … #define regDAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX … #define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE … #define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX … #define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE … #define regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX … #define regDAGB2_WRCLI_ASK_PENDING … #define regDAGB2_WRCLI_ASK_PENDING_BASE_IDX … #define regDAGB2_WRCLI_GO_PENDING … #define regDAGB2_WRCLI_GO_PENDING_BASE_IDX … #define regDAGB2_WRCLI_GBLSEND_PENDING … #define regDAGB2_WRCLI_GBLSEND_PENDING_BASE_IDX … #define regDAGB2_WRCLI_TLB_PENDING … #define regDAGB2_WRCLI_TLB_PENDING_BASE_IDX … #define regDAGB2_WRCLI_OARB_PENDING … #define regDAGB2_WRCLI_OARB_PENDING_BASE_IDX … #define regDAGB2_WRCLI_OSD_PENDING … #define regDAGB2_WRCLI_OSD_PENDING_BASE_IDX … #define regDAGB2_WRCLI_DBUS_ASK_PENDING … #define regDAGB2_WRCLI_DBUS_ASK_PENDING_BASE_IDX … #define regDAGB2_WRCLI_DBUS_GO_PENDING … #define regDAGB2_WRCLI_DBUS_GO_PENDING_BASE_IDX … #define regDAGB2_DAGB_DLY … #define regDAGB2_DAGB_DLY_BASE_IDX … #define regDAGB2_CNTL_MISC … #define regDAGB2_CNTL_MISC_BASE_IDX … #define regDAGB2_CNTL_MISC2 … #define regDAGB2_CNTL_MISC2_BASE_IDX … #define regDAGB2_FATAL_ERROR_CNTL … #define regDAGB2_FATAL_ERROR_CNTL_BASE_IDX … #define regDAGB2_FATAL_ERROR_CLEAR … #define regDAGB2_FATAL_ERROR_CLEAR_BASE_IDX … #define regDAGB2_FATAL_ERROR_STATUS0 … #define regDAGB2_FATAL_ERROR_STATUS0_BASE_IDX … #define regDAGB2_FATAL_ERROR_STATUS1 … #define regDAGB2_FATAL_ERROR_STATUS1_BASE_IDX … #define regDAGB2_FATAL_ERROR_STATUS2 … #define regDAGB2_FATAL_ERROR_STATUS2_BASE_IDX … #define regDAGB2_FATAL_ERROR_STATUS3 … #define regDAGB2_FATAL_ERROR_STATUS3_BASE_IDX … #define regDAGB2_FIFO_EMPTY … #define regDAGB2_FIFO_EMPTY_BASE_IDX … #define regDAGB2_FIFO_FULL … #define regDAGB2_FIFO_FULL_BASE_IDX … #define regDAGB2_WR_CREDITS_FULL … #define regDAGB2_WR_CREDITS_FULL_BASE_IDX … #define regDAGB2_RD_CREDITS_FULL … #define regDAGB2_RD_CREDITS_FULL_BASE_IDX … #define regDAGB2_PERFCOUNTER_LO … #define regDAGB2_PERFCOUNTER_LO_BASE_IDX … #define regDAGB2_PERFCOUNTER_HI … #define regDAGB2_PERFCOUNTER_HI_BASE_IDX … #define regDAGB2_PERFCOUNTER0_CFG … #define regDAGB2_PERFCOUNTER0_CFG_BASE_IDX … #define regDAGB2_PERFCOUNTER1_CFG … #define regDAGB2_PERFCOUNTER1_CFG_BASE_IDX … #define regDAGB2_PERFCOUNTER2_CFG … #define regDAGB2_PERFCOUNTER2_CFG_BASE_IDX … #define regDAGB2_PERFCOUNTER_RSLT_CNTL … #define regDAGB2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define regDAGB2_L1TLB_REG_RW … #define regDAGB2_L1TLB_REG_RW_BASE_IDX … // addressBlock: aid_mmhub_dagb_dagbdec3 // base address: 0x60600 #define regDAGB3_RDCLI0 … #define regDAGB3_RDCLI0_BASE_IDX … #define regDAGB3_RDCLI1 … #define regDAGB3_RDCLI1_BASE_IDX … #define regDAGB3_RDCLI2 … #define regDAGB3_RDCLI2_BASE_IDX … #define regDAGB3_RDCLI3 … #define regDAGB3_RDCLI3_BASE_IDX … #define regDAGB3_RDCLI4 … #define regDAGB3_RDCLI4_BASE_IDX … #define regDAGB3_RDCLI5 … #define regDAGB3_RDCLI5_BASE_IDX … #define regDAGB3_RDCLI6 … #define regDAGB3_RDCLI6_BASE_IDX … #define regDAGB3_RDCLI7 … #define regDAGB3_RDCLI7_BASE_IDX … #define regDAGB3_RDCLI8 … #define regDAGB3_RDCLI8_BASE_IDX … #define regDAGB3_RDCLI9 … #define regDAGB3_RDCLI9_BASE_IDX … #define regDAGB3_RDCLI10 … #define regDAGB3_RDCLI10_BASE_IDX … #define regDAGB3_RDCLI11 … #define regDAGB3_RDCLI11_BASE_IDX … #define regDAGB3_RDCLI12 … #define regDAGB3_RDCLI12_BASE_IDX … #define regDAGB3_RDCLI13 … #define regDAGB3_RDCLI13_BASE_IDX … #define regDAGB3_RDCLI14 … #define regDAGB3_RDCLI14_BASE_IDX … #define regDAGB3_RDCLI15 … #define regDAGB3_RDCLI15_BASE_IDX … #define regDAGB3_RD_CNTL … #define regDAGB3_RD_CNTL_BASE_IDX … #define regDAGB3_RD_GMI_CNTL … #define regDAGB3_RD_GMI_CNTL_BASE_IDX … #define regDAGB3_RD_ADDR_DAGB … #define regDAGB3_RD_ADDR_DAGB_BASE_IDX … #define regDAGB3_RD_OUTPUT_DAGB_MAX_BURST … #define regDAGB3_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define regDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER … #define regDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define regDAGB3_RD_CGTT_CLK_CTRL … #define regDAGB3_RD_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB3_L1TLB_RD_CGTT_CLK_CTRL … #define regDAGB3_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB3_ATCVM_RD_CGTT_CLK_CTRL … #define regDAGB3_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB3_RD_ADDR_DAGB_MAX_BURST0 … #define regDAGB3_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER0 … #define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define regDAGB3_RD_ADDR_DAGB_MAX_BURST1 … #define regDAGB3_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER1 … #define regDAGB3_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define regDAGB3_RD_VC0_CNTL … #define regDAGB3_RD_VC0_CNTL_BASE_IDX … #define regDAGB3_RD_VC1_CNTL … #define regDAGB3_RD_VC1_CNTL_BASE_IDX … #define regDAGB3_RD_VC2_CNTL … #define regDAGB3_RD_VC2_CNTL_BASE_IDX … #define regDAGB3_RD_VC3_CNTL … #define regDAGB3_RD_VC3_CNTL_BASE_IDX … #define regDAGB3_RD_VC4_CNTL … #define regDAGB3_RD_VC4_CNTL_BASE_IDX … #define regDAGB3_RD_VC5_CNTL … #define regDAGB3_RD_VC5_CNTL_BASE_IDX … #define regDAGB3_RD_VC6_CNTL … #define regDAGB3_RD_VC6_CNTL_BASE_IDX … #define regDAGB3_RD_VC7_CNTL … #define regDAGB3_RD_VC7_CNTL_BASE_IDX … #define regDAGB3_RD_CNTL_MISC … #define regDAGB3_RD_CNTL_MISC_BASE_IDX … #define regDAGB3_RD_TLB_CREDIT … #define regDAGB3_RD_TLB_CREDIT_BASE_IDX … #define regDAGB3_RD_RDRET_CREDIT_CNTL … #define regDAGB3_RD_RDRET_CREDIT_CNTL_BASE_IDX … #define regDAGB3_RD_RDRET_CREDIT_CNTL2 … #define regDAGB3_RD_RDRET_CREDIT_CNTL2_BASE_IDX … #define regDAGB3_RDCLI_ASK_PENDING … #define regDAGB3_RDCLI_ASK_PENDING_BASE_IDX … #define regDAGB3_RDCLI_GO_PENDING … #define regDAGB3_RDCLI_GO_PENDING_BASE_IDX … #define regDAGB3_RDCLI_GBLSEND_PENDING … #define regDAGB3_RDCLI_GBLSEND_PENDING_BASE_IDX … #define regDAGB3_RDCLI_TLB_PENDING … #define regDAGB3_RDCLI_TLB_PENDING_BASE_IDX … #define regDAGB3_RDCLI_OARB_PENDING … #define regDAGB3_RDCLI_OARB_PENDING_BASE_IDX … #define regDAGB3_RDCLI_OSD_PENDING … #define regDAGB3_RDCLI_OSD_PENDING_BASE_IDX … #define regDAGB3_WRCLI0 … #define regDAGB3_WRCLI0_BASE_IDX … #define regDAGB3_WRCLI1 … #define regDAGB3_WRCLI1_BASE_IDX … #define regDAGB3_WRCLI2 … #define regDAGB3_WRCLI2_BASE_IDX … #define regDAGB3_WRCLI3 … #define regDAGB3_WRCLI3_BASE_IDX … #define regDAGB3_WRCLI4 … #define regDAGB3_WRCLI4_BASE_IDX … #define regDAGB3_WRCLI5 … #define regDAGB3_WRCLI5_BASE_IDX … #define regDAGB3_WRCLI6 … #define regDAGB3_WRCLI6_BASE_IDX … #define regDAGB3_WRCLI7 … #define regDAGB3_WRCLI7_BASE_IDX … #define regDAGB3_WRCLI8 … #define regDAGB3_WRCLI8_BASE_IDX … #define regDAGB3_WRCLI9 … #define regDAGB3_WRCLI9_BASE_IDX … #define regDAGB3_WRCLI10 … #define regDAGB3_WRCLI10_BASE_IDX … #define regDAGB3_WRCLI11 … #define regDAGB3_WRCLI11_BASE_IDX … #define regDAGB3_WRCLI12 … #define regDAGB3_WRCLI12_BASE_IDX … #define regDAGB3_WRCLI13 … #define regDAGB3_WRCLI13_BASE_IDX … #define regDAGB3_WRCLI14 … #define regDAGB3_WRCLI14_BASE_IDX … #define regDAGB3_WRCLI15 … #define regDAGB3_WRCLI15_BASE_IDX … #define regDAGB3_WR_CNTL … #define regDAGB3_WR_CNTL_BASE_IDX … #define regDAGB3_WR_GMI_CNTL … #define regDAGB3_WR_GMI_CNTL_BASE_IDX … #define regDAGB3_WR_ADDR_DAGB … #define regDAGB3_WR_ADDR_DAGB_BASE_IDX … #define regDAGB3_WR_OUTPUT_DAGB_MAX_BURST … #define regDAGB3_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define regDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER … #define regDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define regDAGB3_WR_CGTT_CLK_CTRL … #define regDAGB3_WR_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB3_L1TLB_WR_CGTT_CLK_CTRL … #define regDAGB3_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB3_ATCVM_WR_CGTT_CLK_CTRL … #define regDAGB3_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB3_WR_ADDR_DAGB_MAX_BURST0 … #define regDAGB3_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER0 … #define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define regDAGB3_WR_ADDR_DAGB_MAX_BURST1 … #define regDAGB3_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER1 … #define regDAGB3_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define regDAGB3_WR_DATA_DAGB … #define regDAGB3_WR_DATA_DAGB_BASE_IDX … #define regDAGB3_WR_DATA_DAGB_MAX_BURST0 … #define regDAGB3_WR_DATA_DAGB_MAX_BURST0_BASE_IDX … #define regDAGB3_WR_DATA_DAGB_LAZY_TIMER0 … #define regDAGB3_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX … #define regDAGB3_WR_DATA_DAGB_MAX_BURST1 … #define regDAGB3_WR_DATA_DAGB_MAX_BURST1_BASE_IDX … #define regDAGB3_WR_DATA_DAGB_LAZY_TIMER1 … #define regDAGB3_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX … #define regDAGB3_WR_VC0_CNTL … #define regDAGB3_WR_VC0_CNTL_BASE_IDX … #define regDAGB3_WR_VC1_CNTL … #define regDAGB3_WR_VC1_CNTL_BASE_IDX … #define regDAGB3_WR_VC2_CNTL … #define regDAGB3_WR_VC2_CNTL_BASE_IDX … #define regDAGB3_WR_VC3_CNTL … #define regDAGB3_WR_VC3_CNTL_BASE_IDX … #define regDAGB3_WR_VC4_CNTL … #define regDAGB3_WR_VC4_CNTL_BASE_IDX … #define regDAGB3_WR_VC5_CNTL … #define regDAGB3_WR_VC5_CNTL_BASE_IDX … #define regDAGB3_WR_VC6_CNTL … #define regDAGB3_WR_VC6_CNTL_BASE_IDX … #define regDAGB3_WR_VC7_CNTL … #define regDAGB3_WR_VC7_CNTL_BASE_IDX … #define regDAGB3_WR_CNTL_MISC … #define regDAGB3_WR_CNTL_MISC_BASE_IDX … #define regDAGB3_WR_TLB_CREDIT … #define regDAGB3_WR_TLB_CREDIT_BASE_IDX … #define regDAGB3_WR_DATA_CREDIT … #define regDAGB3_WR_DATA_CREDIT_BASE_IDX … #define regDAGB3_WR_MISC_CREDIT … #define regDAGB3_WR_MISC_CREDIT_BASE_IDX … #define regDAGB3_WR_OSD_CREDIT_CNTL1 … #define regDAGB3_WR_OSD_CREDIT_CNTL1_BASE_IDX … #define regDAGB3_WR_OSD_CREDIT_CNTL2 … #define regDAGB3_WR_OSD_CREDIT_CNTL2_BASE_IDX … #define regDAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1 … #define regDAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX … #define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE … #define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX … #define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE … #define regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX … #define regDAGB3_WRCLI_ASK_PENDING … #define regDAGB3_WRCLI_ASK_PENDING_BASE_IDX … #define regDAGB3_WRCLI_GO_PENDING … #define regDAGB3_WRCLI_GO_PENDING_BASE_IDX … #define regDAGB3_WRCLI_GBLSEND_PENDING … #define regDAGB3_WRCLI_GBLSEND_PENDING_BASE_IDX … #define regDAGB3_WRCLI_TLB_PENDING … #define regDAGB3_WRCLI_TLB_PENDING_BASE_IDX … #define regDAGB3_WRCLI_OARB_PENDING … #define regDAGB3_WRCLI_OARB_PENDING_BASE_IDX … #define regDAGB3_WRCLI_OSD_PENDING … #define regDAGB3_WRCLI_OSD_PENDING_BASE_IDX … #define regDAGB3_WRCLI_DBUS_ASK_PENDING … #define regDAGB3_WRCLI_DBUS_ASK_PENDING_BASE_IDX … #define regDAGB3_WRCLI_DBUS_GO_PENDING … #define regDAGB3_WRCLI_DBUS_GO_PENDING_BASE_IDX … #define regDAGB3_DAGB_DLY … #define regDAGB3_DAGB_DLY_BASE_IDX … #define regDAGB3_CNTL_MISC … #define regDAGB3_CNTL_MISC_BASE_IDX … #define regDAGB3_CNTL_MISC2 … #define regDAGB3_CNTL_MISC2_BASE_IDX … #define regDAGB3_FATAL_ERROR_CNTL … #define regDAGB3_FATAL_ERROR_CNTL_BASE_IDX … #define regDAGB3_FATAL_ERROR_CLEAR … #define regDAGB3_FATAL_ERROR_CLEAR_BASE_IDX … #define regDAGB3_FATAL_ERROR_STATUS0 … #define regDAGB3_FATAL_ERROR_STATUS0_BASE_IDX … #define regDAGB3_FATAL_ERROR_STATUS1 … #define regDAGB3_FATAL_ERROR_STATUS1_BASE_IDX … #define regDAGB3_FATAL_ERROR_STATUS2 … #define regDAGB3_FATAL_ERROR_STATUS2_BASE_IDX … #define regDAGB3_FATAL_ERROR_STATUS3 … #define regDAGB3_FATAL_ERROR_STATUS3_BASE_IDX … #define regDAGB3_FIFO_EMPTY … #define regDAGB3_FIFO_EMPTY_BASE_IDX … #define regDAGB3_FIFO_FULL … #define regDAGB3_FIFO_FULL_BASE_IDX … #define regDAGB3_WR_CREDITS_FULL … #define regDAGB3_WR_CREDITS_FULL_BASE_IDX … #define regDAGB3_RD_CREDITS_FULL … #define regDAGB3_RD_CREDITS_FULL_BASE_IDX … #define regDAGB3_PERFCOUNTER_LO … #define regDAGB3_PERFCOUNTER_LO_BASE_IDX … #define regDAGB3_PERFCOUNTER_HI … #define regDAGB3_PERFCOUNTER_HI_BASE_IDX … #define regDAGB3_PERFCOUNTER0_CFG … #define regDAGB3_PERFCOUNTER0_CFG_BASE_IDX … #define regDAGB3_PERFCOUNTER1_CFG … #define regDAGB3_PERFCOUNTER1_CFG_BASE_IDX … #define regDAGB3_PERFCOUNTER2_CFG … #define regDAGB3_PERFCOUNTER2_CFG_BASE_IDX … #define regDAGB3_PERFCOUNTER_RSLT_CNTL … #define regDAGB3_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define regDAGB3_L1TLB_REG_RW … #define regDAGB3_L1TLB_REG_RW_BASE_IDX … // addressBlock: aid_mmhub_dagb_dagbdec4 // base address: 0x60800 #define regDAGB4_RDCLI0 … #define regDAGB4_RDCLI0_BASE_IDX … #define regDAGB4_RDCLI1 … #define regDAGB4_RDCLI1_BASE_IDX … #define regDAGB4_RDCLI2 … #define regDAGB4_RDCLI2_BASE_IDX … #define regDAGB4_RDCLI3 … #define regDAGB4_RDCLI3_BASE_IDX … #define regDAGB4_RDCLI4 … #define regDAGB4_RDCLI4_BASE_IDX … #define regDAGB4_RDCLI5 … #define regDAGB4_RDCLI5_BASE_IDX … #define regDAGB4_RDCLI6 … #define regDAGB4_RDCLI6_BASE_IDX … #define regDAGB4_RDCLI7 … #define regDAGB4_RDCLI7_BASE_IDX … #define regDAGB4_RDCLI8 … #define regDAGB4_RDCLI8_BASE_IDX … #define regDAGB4_RDCLI9 … #define regDAGB4_RDCLI9_BASE_IDX … #define regDAGB4_RDCLI10 … #define regDAGB4_RDCLI10_BASE_IDX … #define regDAGB4_RDCLI11 … #define regDAGB4_RDCLI11_BASE_IDX … #define regDAGB4_RDCLI12 … #define regDAGB4_RDCLI12_BASE_IDX … #define regDAGB4_RDCLI13 … #define regDAGB4_RDCLI13_BASE_IDX … #define regDAGB4_RDCLI14 … #define regDAGB4_RDCLI14_BASE_IDX … #define regDAGB4_RDCLI15 … #define regDAGB4_RDCLI15_BASE_IDX … #define regDAGB4_RD_CNTL … #define regDAGB4_RD_CNTL_BASE_IDX … #define regDAGB4_RD_GMI_CNTL … #define regDAGB4_RD_GMI_CNTL_BASE_IDX … #define regDAGB4_RD_ADDR_DAGB … #define regDAGB4_RD_ADDR_DAGB_BASE_IDX … #define regDAGB4_RD_OUTPUT_DAGB_MAX_BURST … #define regDAGB4_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define regDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER … #define regDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define regDAGB4_RD_CGTT_CLK_CTRL … #define regDAGB4_RD_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB4_L1TLB_RD_CGTT_CLK_CTRL … #define regDAGB4_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB4_ATCVM_RD_CGTT_CLK_CTRL … #define regDAGB4_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB4_RD_ADDR_DAGB_MAX_BURST0 … #define regDAGB4_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER0 … #define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define regDAGB4_RD_ADDR_DAGB_MAX_BURST1 … #define regDAGB4_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER1 … #define regDAGB4_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define regDAGB4_RD_VC0_CNTL … #define regDAGB4_RD_VC0_CNTL_BASE_IDX … #define regDAGB4_RD_VC1_CNTL … #define regDAGB4_RD_VC1_CNTL_BASE_IDX … #define regDAGB4_RD_VC2_CNTL … #define regDAGB4_RD_VC2_CNTL_BASE_IDX … #define regDAGB4_RD_VC3_CNTL … #define regDAGB4_RD_VC3_CNTL_BASE_IDX … #define regDAGB4_RD_VC4_CNTL … #define regDAGB4_RD_VC4_CNTL_BASE_IDX … #define regDAGB4_RD_VC5_CNTL … #define regDAGB4_RD_VC5_CNTL_BASE_IDX … #define regDAGB4_RD_VC6_CNTL … #define regDAGB4_RD_VC6_CNTL_BASE_IDX … #define regDAGB4_RD_VC7_CNTL … #define regDAGB4_RD_VC7_CNTL_BASE_IDX … #define regDAGB4_RD_CNTL_MISC … #define regDAGB4_RD_CNTL_MISC_BASE_IDX … #define regDAGB4_RD_TLB_CREDIT … #define regDAGB4_RD_TLB_CREDIT_BASE_IDX … #define regDAGB4_RD_RDRET_CREDIT_CNTL … #define regDAGB4_RD_RDRET_CREDIT_CNTL_BASE_IDX … #define regDAGB4_RD_RDRET_CREDIT_CNTL2 … #define regDAGB4_RD_RDRET_CREDIT_CNTL2_BASE_IDX … #define regDAGB4_RDCLI_ASK_PENDING … #define regDAGB4_RDCLI_ASK_PENDING_BASE_IDX … #define regDAGB4_RDCLI_GO_PENDING … #define regDAGB4_RDCLI_GO_PENDING_BASE_IDX … #define regDAGB4_RDCLI_GBLSEND_PENDING … #define regDAGB4_RDCLI_GBLSEND_PENDING_BASE_IDX … #define regDAGB4_RDCLI_TLB_PENDING … #define regDAGB4_RDCLI_TLB_PENDING_BASE_IDX … #define regDAGB4_RDCLI_OARB_PENDING … #define regDAGB4_RDCLI_OARB_PENDING_BASE_IDX … #define regDAGB4_RDCLI_OSD_PENDING … #define regDAGB4_RDCLI_OSD_PENDING_BASE_IDX … #define regDAGB4_WRCLI0 … #define regDAGB4_WRCLI0_BASE_IDX … #define regDAGB4_WRCLI1 … #define regDAGB4_WRCLI1_BASE_IDX … #define regDAGB4_WRCLI2 … #define regDAGB4_WRCLI2_BASE_IDX … #define regDAGB4_WRCLI3 … #define regDAGB4_WRCLI3_BASE_IDX … #define regDAGB4_WRCLI4 … #define regDAGB4_WRCLI4_BASE_IDX … #define regDAGB4_WRCLI5 … #define regDAGB4_WRCLI5_BASE_IDX … #define regDAGB4_WRCLI6 … #define regDAGB4_WRCLI6_BASE_IDX … #define regDAGB4_WRCLI7 … #define regDAGB4_WRCLI7_BASE_IDX … #define regDAGB4_WRCLI8 … #define regDAGB4_WRCLI8_BASE_IDX … #define regDAGB4_WRCLI9 … #define regDAGB4_WRCLI9_BASE_IDX … #define regDAGB4_WRCLI10 … #define regDAGB4_WRCLI10_BASE_IDX … #define regDAGB4_WRCLI11 … #define regDAGB4_WRCLI11_BASE_IDX … #define regDAGB4_WRCLI12 … #define regDAGB4_WRCLI12_BASE_IDX … #define regDAGB4_WRCLI13 … #define regDAGB4_WRCLI13_BASE_IDX … #define regDAGB4_WRCLI14 … #define regDAGB4_WRCLI14_BASE_IDX … #define regDAGB4_WRCLI15 … #define regDAGB4_WRCLI15_BASE_IDX … #define regDAGB4_WR_CNTL … #define regDAGB4_WR_CNTL_BASE_IDX … #define regDAGB4_WR_GMI_CNTL … #define regDAGB4_WR_GMI_CNTL_BASE_IDX … #define regDAGB4_WR_ADDR_DAGB … #define regDAGB4_WR_ADDR_DAGB_BASE_IDX … #define regDAGB4_WR_OUTPUT_DAGB_MAX_BURST … #define regDAGB4_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX … #define regDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER … #define regDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX … #define regDAGB4_WR_CGTT_CLK_CTRL … #define regDAGB4_WR_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB4_L1TLB_WR_CGTT_CLK_CTRL … #define regDAGB4_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB4_ATCVM_WR_CGTT_CLK_CTRL … #define regDAGB4_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX … #define regDAGB4_WR_ADDR_DAGB_MAX_BURST0 … #define regDAGB4_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX … #define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER0 … #define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX … #define regDAGB4_WR_ADDR_DAGB_MAX_BURST1 … #define regDAGB4_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX … #define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER1 … #define regDAGB4_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX … #define regDAGB4_WR_DATA_DAGB … #define regDAGB4_WR_DATA_DAGB_BASE_IDX … #define regDAGB4_WR_DATA_DAGB_MAX_BURST0 … #define regDAGB4_WR_DATA_DAGB_MAX_BURST0_BASE_IDX … #define regDAGB4_WR_DATA_DAGB_LAZY_TIMER0 … #define regDAGB4_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX … #define regDAGB4_WR_DATA_DAGB_MAX_BURST1 … #define regDAGB4_WR_DATA_DAGB_MAX_BURST1_BASE_IDX … #define regDAGB4_WR_DATA_DAGB_LAZY_TIMER1 … #define regDAGB4_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX … #define regDAGB4_WR_VC0_CNTL … #define regDAGB4_WR_VC0_CNTL_BASE_IDX … #define regDAGB4_WR_VC1_CNTL … #define regDAGB4_WR_VC1_CNTL_BASE_IDX … #define regDAGB4_WR_VC2_CNTL … #define regDAGB4_WR_VC2_CNTL_BASE_IDX … #define regDAGB4_WR_VC3_CNTL … #define regDAGB4_WR_VC3_CNTL_BASE_IDX … #define regDAGB4_WR_VC4_CNTL … #define regDAGB4_WR_VC4_CNTL_BASE_IDX … #define regDAGB4_WR_VC5_CNTL … #define regDAGB4_WR_VC5_CNTL_BASE_IDX … #define regDAGB4_WR_VC6_CNTL … #define regDAGB4_WR_VC6_CNTL_BASE_IDX … #define regDAGB4_WR_VC7_CNTL … #define regDAGB4_WR_VC7_CNTL_BASE_IDX … #define regDAGB4_WR_CNTL_MISC … #define regDAGB4_WR_CNTL_MISC_BASE_IDX … #define regDAGB4_WR_TLB_CREDIT … #define regDAGB4_WR_TLB_CREDIT_BASE_IDX … #define regDAGB4_WR_DATA_CREDIT … #define regDAGB4_WR_DATA_CREDIT_BASE_IDX … #define regDAGB4_WR_MISC_CREDIT … #define regDAGB4_WR_MISC_CREDIT_BASE_IDX … #define regDAGB4_WR_OSD_CREDIT_CNTL1 … #define regDAGB4_WR_OSD_CREDIT_CNTL1_BASE_IDX … #define regDAGB4_WR_OSD_CREDIT_CNTL2 … #define regDAGB4_WR_OSD_CREDIT_CNTL2_BASE_IDX … #define regDAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1 … #define regDAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX … #define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE … #define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX … #define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE … #define regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX … #define regDAGB4_WRCLI_ASK_PENDING … #define regDAGB4_WRCLI_ASK_PENDING_BASE_IDX … #define regDAGB4_WRCLI_GO_PENDING … #define regDAGB4_WRCLI_GO_PENDING_BASE_IDX … #define regDAGB4_WRCLI_GBLSEND_PENDING … #define regDAGB4_WRCLI_GBLSEND_PENDING_BASE_IDX … #define regDAGB4_WRCLI_TLB_PENDING … #define regDAGB4_WRCLI_TLB_PENDING_BASE_IDX … #define regDAGB4_WRCLI_OARB_PENDING … #define regDAGB4_WRCLI_OARB_PENDING_BASE_IDX … #define regDAGB4_WRCLI_OSD_PENDING … #define regDAGB4_WRCLI_OSD_PENDING_BASE_IDX … #define regDAGB4_WRCLI_DBUS_ASK_PENDING … #define regDAGB4_WRCLI_DBUS_ASK_PENDING_BASE_IDX … #define regDAGB4_WRCLI_DBUS_GO_PENDING … #define regDAGB4_WRCLI_DBUS_GO_PENDING_BASE_IDX … #define regDAGB4_DAGB_DLY … #define regDAGB4_DAGB_DLY_BASE_IDX … #define regDAGB4_CNTL_MISC … #define regDAGB4_CNTL_MISC_BASE_IDX … #define regDAGB4_CNTL_MISC2 … #define regDAGB4_CNTL_MISC2_BASE_IDX … #define regDAGB4_FATAL_ERROR_CNTL … #define regDAGB4_FATAL_ERROR_CNTL_BASE_IDX … #define regDAGB4_FATAL_ERROR_CLEAR … #define regDAGB4_FATAL_ERROR_CLEAR_BASE_IDX … #define regDAGB4_FATAL_ERROR_STATUS0 … #define regDAGB4_FATAL_ERROR_STATUS0_BASE_IDX … #define regDAGB4_FATAL_ERROR_STATUS1 … #define regDAGB4_FATAL_ERROR_STATUS1_BASE_IDX … #define regDAGB4_FATAL_ERROR_STATUS2 … #define regDAGB4_FATAL_ERROR_STATUS2_BASE_IDX … #define regDAGB4_FATAL_ERROR_STATUS3 … #define regDAGB4_FATAL_ERROR_STATUS3_BASE_IDX … #define regDAGB4_FIFO_EMPTY … #define regDAGB4_FIFO_EMPTY_BASE_IDX … #define regDAGB4_FIFO_FULL … #define regDAGB4_FIFO_FULL_BASE_IDX … #define regDAGB4_WR_CREDITS_FULL … #define regDAGB4_WR_CREDITS_FULL_BASE_IDX … #define regDAGB4_RD_CREDITS_FULL … #define regDAGB4_RD_CREDITS_FULL_BASE_IDX … #define regDAGB4_PERFCOUNTER_LO … #define regDAGB4_PERFCOUNTER_LO_BASE_IDX … #define regDAGB4_PERFCOUNTER_HI … #define regDAGB4_PERFCOUNTER_HI_BASE_IDX … #define regDAGB4_PERFCOUNTER0_CFG … #define regDAGB4_PERFCOUNTER0_CFG_BASE_IDX … #define regDAGB4_PERFCOUNTER1_CFG … #define regDAGB4_PERFCOUNTER1_CFG_BASE_IDX … #define regDAGB4_PERFCOUNTER2_CFG … #define regDAGB4_PERFCOUNTER2_CFG_BASE_IDX … #define regDAGB4_PERFCOUNTER_RSLT_CNTL … #define regDAGB4_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define regDAGB4_L1TLB_REG_RW … #define regDAGB4_L1TLB_REG_RW_BASE_IDX … // addressBlock: aid_mmhub_ea_mmeadec0 // base address: 0x60c00 #define regMMEA0_DRAM_RD_CLI2GRP_MAP0 … #define regMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX … #define regMMEA0_DRAM_RD_CLI2GRP_MAP1 … #define regMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX … #define regMMEA0_DRAM_WR_CLI2GRP_MAP0 … #define regMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX … #define regMMEA0_DRAM_WR_CLI2GRP_MAP1 … #define regMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX … #define regMMEA0_DRAM_RD_GRP2VC_MAP … #define regMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX … #define regMMEA0_DRAM_WR_GRP2VC_MAP … #define regMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX … #define regMMEA0_DRAM_RD_LAZY … #define regMMEA0_DRAM_RD_LAZY_BASE_IDX … #define regMMEA0_DRAM_WR_LAZY … #define regMMEA0_DRAM_WR_LAZY_BASE_IDX … #define regMMEA0_DRAM_RD_CAM_CNTL … #define regMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX … #define regMMEA0_DRAM_WR_CAM_CNTL … #define regMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX … #define regMMEA0_DRAM_PAGE_BURST … #define regMMEA0_DRAM_PAGE_BURST_BASE_IDX … #define regMMEA0_DRAM_RD_PRI_AGE … #define regMMEA0_DRAM_RD_PRI_AGE_BASE_IDX … #define regMMEA0_DRAM_WR_PRI_AGE … #define regMMEA0_DRAM_WR_PRI_AGE_BASE_IDX … #define regMMEA0_DRAM_RD_PRI_QUEUING … #define regMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX … #define regMMEA0_DRAM_WR_PRI_QUEUING … #define regMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX … #define regMMEA0_DRAM_RD_PRI_FIXED … #define regMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX … #define regMMEA0_DRAM_WR_PRI_FIXED … #define regMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX … #define regMMEA0_DRAM_RD_PRI_URGENCY … #define regMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX … #define regMMEA0_DRAM_WR_PRI_URGENCY … #define regMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX … #define regMMEA0_DRAM_RD_PRI_QUANT_PRI1 … #define regMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA0_DRAM_RD_PRI_QUANT_PRI2 … #define regMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA0_DRAM_RD_PRI_QUANT_PRI3 … #define regMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA0_DRAM_WR_PRI_QUANT_PRI1 … #define regMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA0_DRAM_WR_PRI_QUANT_PRI2 … #define regMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA0_DRAM_WR_PRI_QUANT_PRI3 … #define regMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA0_GMI_RD_CLI2GRP_MAP0 … #define regMMEA0_GMI_RD_CLI2GRP_MAP0_BASE_IDX … #define regMMEA0_GMI_RD_CLI2GRP_MAP1 … #define regMMEA0_GMI_RD_CLI2GRP_MAP1_BASE_IDX … #define regMMEA0_GMI_WR_CLI2GRP_MAP0 … #define regMMEA0_GMI_WR_CLI2GRP_MAP0_BASE_IDX … #define regMMEA0_GMI_WR_CLI2GRP_MAP1 … #define regMMEA0_GMI_WR_CLI2GRP_MAP1_BASE_IDX … #define regMMEA0_GMI_RD_GRP2VC_MAP … #define regMMEA0_GMI_RD_GRP2VC_MAP_BASE_IDX … #define regMMEA0_GMI_WR_GRP2VC_MAP … #define regMMEA0_GMI_WR_GRP2VC_MAP_BASE_IDX … #define regMMEA0_GMI_RD_LAZY … #define regMMEA0_GMI_RD_LAZY_BASE_IDX … #define regMMEA0_GMI_WR_LAZY … #define regMMEA0_GMI_WR_LAZY_BASE_IDX … #define regMMEA0_GMI_RD_CAM_CNTL … #define regMMEA0_GMI_RD_CAM_CNTL_BASE_IDX … #define regMMEA0_GMI_WR_CAM_CNTL … #define regMMEA0_GMI_WR_CAM_CNTL_BASE_IDX … #define regMMEA0_GMI_PAGE_BURST … #define regMMEA0_GMI_PAGE_BURST_BASE_IDX … #define regMMEA0_GMI_RD_PRI_AGE … #define regMMEA0_GMI_RD_PRI_AGE_BASE_IDX … #define regMMEA0_GMI_WR_PRI_AGE … #define regMMEA0_GMI_WR_PRI_AGE_BASE_IDX … #define regMMEA0_GMI_RD_PRI_QUEUING … #define regMMEA0_GMI_RD_PRI_QUEUING_BASE_IDX … #define regMMEA0_GMI_WR_PRI_QUEUING … #define regMMEA0_GMI_WR_PRI_QUEUING_BASE_IDX … #define regMMEA0_GMI_RD_PRI_FIXED … #define regMMEA0_GMI_RD_PRI_FIXED_BASE_IDX … #define regMMEA0_GMI_WR_PRI_FIXED … #define regMMEA0_GMI_WR_PRI_FIXED_BASE_IDX … #define regMMEA0_GMI_RD_PRI_URGENCY … #define regMMEA0_GMI_RD_PRI_URGENCY_BASE_IDX … #define regMMEA0_GMI_WR_PRI_URGENCY … #define regMMEA0_GMI_WR_PRI_URGENCY_BASE_IDX … #define regMMEA0_GMI_RD_PRI_URGENCY_MASKING … #define regMMEA0_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX … #define regMMEA0_GMI_WR_PRI_URGENCY_MASKING … #define regMMEA0_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX … #define regMMEA0_GMI_RD_PRI_QUANT_PRI1 … #define regMMEA0_GMI_RD_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA0_GMI_RD_PRI_QUANT_PRI2 … #define regMMEA0_GMI_RD_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA0_GMI_RD_PRI_QUANT_PRI3 … #define regMMEA0_GMI_RD_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA0_GMI_WR_PRI_QUANT_PRI1 … #define regMMEA0_GMI_WR_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA0_GMI_WR_PRI_QUANT_PRI2 … #define regMMEA0_GMI_WR_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA0_GMI_WR_PRI_QUANT_PRI3 … #define regMMEA0_GMI_WR_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA0_IO_RD_CLI2GRP_MAP0 … #define regMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX … #define regMMEA0_IO_RD_CLI2GRP_MAP1 … #define regMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX … #define regMMEA0_IO_WR_CLI2GRP_MAP0 … #define regMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX … #define regMMEA0_IO_WR_CLI2GRP_MAP1 … #define regMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX … #define regMMEA0_IO_RD_COMBINE_FLUSH … #define regMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX … #define regMMEA0_IO_WR_COMBINE_FLUSH … #define regMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX … #define regMMEA0_IO_GROUP_BURST … #define regMMEA0_IO_GROUP_BURST_BASE_IDX … #define regMMEA0_IO_RD_PRI_AGE … #define regMMEA0_IO_RD_PRI_AGE_BASE_IDX … #define regMMEA0_IO_WR_PRI_AGE … #define regMMEA0_IO_WR_PRI_AGE_BASE_IDX … #define regMMEA0_IO_RD_PRI_QUEUING … #define regMMEA0_IO_RD_PRI_QUEUING_BASE_IDX … #define regMMEA0_IO_WR_PRI_QUEUING … #define regMMEA0_IO_WR_PRI_QUEUING_BASE_IDX … #define regMMEA0_IO_RD_PRI_FIXED … #define regMMEA0_IO_RD_PRI_FIXED_BASE_IDX … #define regMMEA0_IO_WR_PRI_FIXED … #define regMMEA0_IO_WR_PRI_FIXED_BASE_IDX … #define regMMEA0_IO_RD_PRI_URGENCY … #define regMMEA0_IO_RD_PRI_URGENCY_BASE_IDX … #define regMMEA0_IO_WR_PRI_URGENCY … #define regMMEA0_IO_WR_PRI_URGENCY_BASE_IDX … #define regMMEA0_IO_RD_PRI_URGENCY_MASKING … #define regMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX … #define regMMEA0_IO_WR_PRI_URGENCY_MASKING … #define regMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX … #define regMMEA0_IO_RD_PRI_QUANT_PRI1 … #define regMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA0_IO_RD_PRI_QUANT_PRI2 … #define regMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA0_IO_RD_PRI_QUANT_PRI3 … #define regMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA0_IO_WR_PRI_QUANT_PRI1 … #define regMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA0_IO_WR_PRI_QUANT_PRI2 … #define regMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA0_IO_WR_PRI_QUANT_PRI3 … #define regMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA0_SDP_ARB_DRAM … #define regMMEA0_SDP_ARB_DRAM_BASE_IDX … #define regMMEA0_SDP_ARB_GMI … #define regMMEA0_SDP_ARB_GMI_BASE_IDX … #define regMMEA0_SDP_ARB_FINAL … #define regMMEA0_SDP_ARB_FINAL_BASE_IDX … #define regMMEA0_SDP_DRAM_PRIORITY … #define regMMEA0_SDP_DRAM_PRIORITY_BASE_IDX … #define regMMEA0_SDP_GMI_PRIORITY … #define regMMEA0_SDP_GMI_PRIORITY_BASE_IDX … #define regMMEA0_SDP_IO_PRIORITY … #define regMMEA0_SDP_IO_PRIORITY_BASE_IDX … #define regMMEA0_SDP_CREDITS … #define regMMEA0_SDP_CREDITS_BASE_IDX … #define regMMEA0_SDP_TAG_RESERVE0 … #define regMMEA0_SDP_TAG_RESERVE0_BASE_IDX … #define regMMEA0_SDP_TAG_RESERVE1 … #define regMMEA0_SDP_TAG_RESERVE1_BASE_IDX … #define regMMEA0_SDP_VCC_RESERVE0 … #define regMMEA0_SDP_VCC_RESERVE0_BASE_IDX … #define regMMEA0_SDP_VCC_RESERVE1 … #define regMMEA0_SDP_VCC_RESERVE1_BASE_IDX … #define regMMEA0_SDP_VCD_RESERVE0 … #define regMMEA0_SDP_VCD_RESERVE0_BASE_IDX … #define regMMEA0_SDP_VCD_RESERVE1 … #define regMMEA0_SDP_VCD_RESERVE1_BASE_IDX … #define regMMEA0_SDP_REQ_CNTL … #define regMMEA0_SDP_REQ_CNTL_BASE_IDX … #define regMMEA0_MISC … #define regMMEA0_MISC_BASE_IDX … #define regMMEA0_LATENCY_SAMPLING … #define regMMEA0_LATENCY_SAMPLING_BASE_IDX … #define regMMEA0_PERFCOUNTER_LO … #define regMMEA0_PERFCOUNTER_LO_BASE_IDX … #define regMMEA0_PERFCOUNTER_HI … #define regMMEA0_PERFCOUNTER_HI_BASE_IDX … #define regMMEA0_PERFCOUNTER0_CFG … #define regMMEA0_PERFCOUNTER0_CFG_BASE_IDX … #define regMMEA0_PERFCOUNTER1_CFG … #define regMMEA0_PERFCOUNTER1_CFG_BASE_IDX … #define regMMEA0_PERFCOUNTER_RSLT_CNTL … #define regMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define regMMEA0_UE_ERR_STATUS_LO … #define regMMEA0_UE_ERR_STATUS_LO_BASE_IDX … #define regMMEA0_UE_ERR_STATUS_HI … #define regMMEA0_UE_ERR_STATUS_HI_BASE_IDX … #define regMMEA0_DSM_CNTL … #define regMMEA0_DSM_CNTL_BASE_IDX … #define regMMEA0_DSM_CNTLA … #define regMMEA0_DSM_CNTLA_BASE_IDX … #define regMMEA0_DSM_CNTLB … #define regMMEA0_DSM_CNTLB_BASE_IDX … #define regMMEA0_DSM_CNTL2 … #define regMMEA0_DSM_CNTL2_BASE_IDX … #define regMMEA0_DSM_CNTL2A … #define regMMEA0_DSM_CNTL2A_BASE_IDX … #define regMMEA0_DSM_CNTL2B … #define regMMEA0_DSM_CNTL2B_BASE_IDX … #define regMMEA0_CGTT_CLK_CTRL … #define regMMEA0_CGTT_CLK_CTRL_BASE_IDX … #define regMMEA0_EDC_MODE … #define regMMEA0_EDC_MODE_BASE_IDX … #define regMMEA0_ERR_STATUS … #define regMMEA0_ERR_STATUS_BASE_IDX … #define regMMEA0_MISC2 … #define regMMEA0_MISC2_BASE_IDX … #define regMMEA0_CE_ERR_STATUS_LO … #define regMMEA0_CE_ERR_STATUS_LO_BASE_IDX … #define regMMEA0_MISC_AON … #define regMMEA0_MISC_AON_BASE_IDX … #define regMMEA0_CE_ERR_STATUS_HI … #define regMMEA0_CE_ERR_STATUS_HI_BASE_IDX … // addressBlock: aid_mmhub_ea_mmeadec1 // base address: 0x61100 #define regMMEA1_DRAM_RD_CLI2GRP_MAP0 … #define regMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX … #define regMMEA1_DRAM_RD_CLI2GRP_MAP1 … #define regMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX … #define regMMEA1_DRAM_WR_CLI2GRP_MAP0 … #define regMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX … #define regMMEA1_DRAM_WR_CLI2GRP_MAP1 … #define regMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX … #define regMMEA1_DRAM_RD_GRP2VC_MAP … #define regMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX … #define regMMEA1_DRAM_WR_GRP2VC_MAP … #define regMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX … #define regMMEA1_DRAM_RD_LAZY … #define regMMEA1_DRAM_RD_LAZY_BASE_IDX … #define regMMEA1_DRAM_WR_LAZY … #define regMMEA1_DRAM_WR_LAZY_BASE_IDX … #define regMMEA1_DRAM_RD_CAM_CNTL … #define regMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX … #define regMMEA1_DRAM_WR_CAM_CNTL … #define regMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX … #define regMMEA1_DRAM_PAGE_BURST … #define regMMEA1_DRAM_PAGE_BURST_BASE_IDX … #define regMMEA1_DRAM_RD_PRI_AGE … #define regMMEA1_DRAM_RD_PRI_AGE_BASE_IDX … #define regMMEA1_DRAM_WR_PRI_AGE … #define regMMEA1_DRAM_WR_PRI_AGE_BASE_IDX … #define regMMEA1_DRAM_RD_PRI_QUEUING … #define regMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX … #define regMMEA1_DRAM_WR_PRI_QUEUING … #define regMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX … #define regMMEA1_DRAM_RD_PRI_FIXED … #define regMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX … #define regMMEA1_DRAM_WR_PRI_FIXED … #define regMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX … #define regMMEA1_DRAM_RD_PRI_URGENCY … #define regMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX … #define regMMEA1_DRAM_WR_PRI_URGENCY … #define regMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX … #define regMMEA1_DRAM_RD_PRI_QUANT_PRI1 … #define regMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA1_DRAM_RD_PRI_QUANT_PRI2 … #define regMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA1_DRAM_RD_PRI_QUANT_PRI3 … #define regMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA1_DRAM_WR_PRI_QUANT_PRI1 … #define regMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA1_DRAM_WR_PRI_QUANT_PRI2 … #define regMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA1_DRAM_WR_PRI_QUANT_PRI3 … #define regMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA1_GMI_RD_CLI2GRP_MAP0 … #define regMMEA1_GMI_RD_CLI2GRP_MAP0_BASE_IDX … #define regMMEA1_GMI_RD_CLI2GRP_MAP1 … #define regMMEA1_GMI_RD_CLI2GRP_MAP1_BASE_IDX … #define regMMEA1_GMI_WR_CLI2GRP_MAP0 … #define regMMEA1_GMI_WR_CLI2GRP_MAP0_BASE_IDX … #define regMMEA1_GMI_WR_CLI2GRP_MAP1 … #define regMMEA1_GMI_WR_CLI2GRP_MAP1_BASE_IDX … #define regMMEA1_GMI_RD_GRP2VC_MAP … #define regMMEA1_GMI_RD_GRP2VC_MAP_BASE_IDX … #define regMMEA1_GMI_WR_GRP2VC_MAP … #define regMMEA1_GMI_WR_GRP2VC_MAP_BASE_IDX … #define regMMEA1_GMI_RD_LAZY … #define regMMEA1_GMI_RD_LAZY_BASE_IDX … #define regMMEA1_GMI_WR_LAZY … #define regMMEA1_GMI_WR_LAZY_BASE_IDX … #define regMMEA1_GMI_RD_CAM_CNTL … #define regMMEA1_GMI_RD_CAM_CNTL_BASE_IDX … #define regMMEA1_GMI_WR_CAM_CNTL … #define regMMEA1_GMI_WR_CAM_CNTL_BASE_IDX … #define regMMEA1_GMI_PAGE_BURST … #define regMMEA1_GMI_PAGE_BURST_BASE_IDX … #define regMMEA1_GMI_RD_PRI_AGE … #define regMMEA1_GMI_RD_PRI_AGE_BASE_IDX … #define regMMEA1_GMI_WR_PRI_AGE … #define regMMEA1_GMI_WR_PRI_AGE_BASE_IDX … #define regMMEA1_GMI_RD_PRI_QUEUING … #define regMMEA1_GMI_RD_PRI_QUEUING_BASE_IDX … #define regMMEA1_GMI_WR_PRI_QUEUING … #define regMMEA1_GMI_WR_PRI_QUEUING_BASE_IDX … #define regMMEA1_GMI_RD_PRI_FIXED … #define regMMEA1_GMI_RD_PRI_FIXED_BASE_IDX … #define regMMEA1_GMI_WR_PRI_FIXED … #define regMMEA1_GMI_WR_PRI_FIXED_BASE_IDX … #define regMMEA1_GMI_RD_PRI_URGENCY … #define regMMEA1_GMI_RD_PRI_URGENCY_BASE_IDX … #define regMMEA1_GMI_WR_PRI_URGENCY … #define regMMEA1_GMI_WR_PRI_URGENCY_BASE_IDX … #define regMMEA1_GMI_RD_PRI_URGENCY_MASKING … #define regMMEA1_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX … #define regMMEA1_GMI_WR_PRI_URGENCY_MASKING … #define regMMEA1_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX … #define regMMEA1_GMI_RD_PRI_QUANT_PRI1 … #define regMMEA1_GMI_RD_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA1_GMI_RD_PRI_QUANT_PRI2 … #define regMMEA1_GMI_RD_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA1_GMI_RD_PRI_QUANT_PRI3 … #define regMMEA1_GMI_RD_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA1_GMI_WR_PRI_QUANT_PRI1 … #define regMMEA1_GMI_WR_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA1_GMI_WR_PRI_QUANT_PRI2 … #define regMMEA1_GMI_WR_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA1_GMI_WR_PRI_QUANT_PRI3 … #define regMMEA1_GMI_WR_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA1_IO_RD_CLI2GRP_MAP0 … #define regMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX … #define regMMEA1_IO_RD_CLI2GRP_MAP1 … #define regMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX … #define regMMEA1_IO_WR_CLI2GRP_MAP0 … #define regMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX … #define regMMEA1_IO_WR_CLI2GRP_MAP1 … #define regMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX … #define regMMEA1_IO_RD_COMBINE_FLUSH … #define regMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX … #define regMMEA1_IO_WR_COMBINE_FLUSH … #define regMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX … #define regMMEA1_IO_GROUP_BURST … #define regMMEA1_IO_GROUP_BURST_BASE_IDX … #define regMMEA1_IO_RD_PRI_AGE … #define regMMEA1_IO_RD_PRI_AGE_BASE_IDX … #define regMMEA1_IO_WR_PRI_AGE … #define regMMEA1_IO_WR_PRI_AGE_BASE_IDX … #define regMMEA1_IO_RD_PRI_QUEUING … #define regMMEA1_IO_RD_PRI_QUEUING_BASE_IDX … #define regMMEA1_IO_WR_PRI_QUEUING … #define regMMEA1_IO_WR_PRI_QUEUING_BASE_IDX … #define regMMEA1_IO_RD_PRI_FIXED … #define regMMEA1_IO_RD_PRI_FIXED_BASE_IDX … #define regMMEA1_IO_WR_PRI_FIXED … #define regMMEA1_IO_WR_PRI_FIXED_BASE_IDX … #define regMMEA1_IO_RD_PRI_URGENCY … #define regMMEA1_IO_RD_PRI_URGENCY_BASE_IDX … #define regMMEA1_IO_WR_PRI_URGENCY … #define regMMEA1_IO_WR_PRI_URGENCY_BASE_IDX … #define regMMEA1_IO_RD_PRI_URGENCY_MASKING … #define regMMEA1_IO_RD_PRI_URGENCY_MASKING_BASE_IDX … #define regMMEA1_IO_WR_PRI_URGENCY_MASKING … #define regMMEA1_IO_WR_PRI_URGENCY_MASKING_BASE_IDX … #define regMMEA1_IO_RD_PRI_QUANT_PRI1 … #define regMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA1_IO_RD_PRI_QUANT_PRI2 … #define regMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA1_IO_RD_PRI_QUANT_PRI3 … #define regMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA1_IO_WR_PRI_QUANT_PRI1 … #define regMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA1_IO_WR_PRI_QUANT_PRI2 … #define regMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA1_IO_WR_PRI_QUANT_PRI3 … #define regMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA1_SDP_ARB_DRAM … #define regMMEA1_SDP_ARB_DRAM_BASE_IDX … #define regMMEA1_SDP_ARB_GMI … #define regMMEA1_SDP_ARB_GMI_BASE_IDX … #define regMMEA1_SDP_ARB_FINAL … #define regMMEA1_SDP_ARB_FINAL_BASE_IDX … #define regMMEA1_SDP_DRAM_PRIORITY … #define regMMEA1_SDP_DRAM_PRIORITY_BASE_IDX … #define regMMEA1_SDP_GMI_PRIORITY … #define regMMEA1_SDP_GMI_PRIORITY_BASE_IDX … #define regMMEA1_SDP_IO_PRIORITY … #define regMMEA1_SDP_IO_PRIORITY_BASE_IDX … #define regMMEA1_SDP_CREDITS … #define regMMEA1_SDP_CREDITS_BASE_IDX … #define regMMEA1_SDP_TAG_RESERVE0 … #define regMMEA1_SDP_TAG_RESERVE0_BASE_IDX … #define regMMEA1_SDP_TAG_RESERVE1 … #define regMMEA1_SDP_TAG_RESERVE1_BASE_IDX … #define regMMEA1_SDP_VCC_RESERVE0 … #define regMMEA1_SDP_VCC_RESERVE0_BASE_IDX … #define regMMEA1_SDP_VCC_RESERVE1 … #define regMMEA1_SDP_VCC_RESERVE1_BASE_IDX … #define regMMEA1_SDP_VCD_RESERVE0 … #define regMMEA1_SDP_VCD_RESERVE0_BASE_IDX … #define regMMEA1_SDP_VCD_RESERVE1 … #define regMMEA1_SDP_VCD_RESERVE1_BASE_IDX … #define regMMEA1_SDP_REQ_CNTL … #define regMMEA1_SDP_REQ_CNTL_BASE_IDX … #define regMMEA1_MISC … #define regMMEA1_MISC_BASE_IDX … #define regMMEA1_LATENCY_SAMPLING … #define regMMEA1_LATENCY_SAMPLING_BASE_IDX … #define regMMEA1_PERFCOUNTER_LO … #define regMMEA1_PERFCOUNTER_LO_BASE_IDX … #define regMMEA1_PERFCOUNTER_HI … #define regMMEA1_PERFCOUNTER_HI_BASE_IDX … #define regMMEA1_PERFCOUNTER0_CFG … #define regMMEA1_PERFCOUNTER0_CFG_BASE_IDX … #define regMMEA1_PERFCOUNTER1_CFG … #define regMMEA1_PERFCOUNTER1_CFG_BASE_IDX … #define regMMEA1_PERFCOUNTER_RSLT_CNTL … #define regMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define regMMEA1_UE_ERR_STATUS_LO … #define regMMEA1_UE_ERR_STATUS_LO_BASE_IDX … #define regMMEA1_UE_ERR_STATUS_HI … #define regMMEA1_UE_ERR_STATUS_HI_BASE_IDX … #define regMMEA1_DSM_CNTL … #define regMMEA1_DSM_CNTL_BASE_IDX … #define regMMEA1_DSM_CNTLA … #define regMMEA1_DSM_CNTLA_BASE_IDX … #define regMMEA1_DSM_CNTLB … #define regMMEA1_DSM_CNTLB_BASE_IDX … #define regMMEA1_DSM_CNTL2 … #define regMMEA1_DSM_CNTL2_BASE_IDX … #define regMMEA1_DSM_CNTL2A … #define regMMEA1_DSM_CNTL2A_BASE_IDX … #define regMMEA1_DSM_CNTL2B … #define regMMEA1_DSM_CNTL2B_BASE_IDX … #define regMMEA1_CGTT_CLK_CTRL … #define regMMEA1_CGTT_CLK_CTRL_BASE_IDX … #define regMMEA1_EDC_MODE … #define regMMEA1_EDC_MODE_BASE_IDX … #define regMMEA1_ERR_STATUS … #define regMMEA1_ERR_STATUS_BASE_IDX … #define regMMEA1_MISC2 … #define regMMEA1_MISC2_BASE_IDX … #define regMMEA1_CE_ERR_STATUS_LO … #define regMMEA1_CE_ERR_STATUS_LO_BASE_IDX … #define regMMEA1_MISC_AON … #define regMMEA1_MISC_AON_BASE_IDX … #define regMMEA1_CE_ERR_STATUS_HI … #define regMMEA1_CE_ERR_STATUS_HI_BASE_IDX … // addressBlock: aid_mmhub_ea_mmeadec2 // base address: 0x61600 #define regMMEA2_DRAM_RD_CLI2GRP_MAP0 … #define regMMEA2_DRAM_RD_CLI2GRP_MAP0_BASE_IDX … #define regMMEA2_DRAM_RD_CLI2GRP_MAP1 … #define regMMEA2_DRAM_RD_CLI2GRP_MAP1_BASE_IDX … #define regMMEA2_DRAM_WR_CLI2GRP_MAP0 … #define regMMEA2_DRAM_WR_CLI2GRP_MAP0_BASE_IDX … #define regMMEA2_DRAM_WR_CLI2GRP_MAP1 … #define regMMEA2_DRAM_WR_CLI2GRP_MAP1_BASE_IDX … #define regMMEA2_DRAM_RD_GRP2VC_MAP … #define regMMEA2_DRAM_RD_GRP2VC_MAP_BASE_IDX … #define regMMEA2_DRAM_WR_GRP2VC_MAP … #define regMMEA2_DRAM_WR_GRP2VC_MAP_BASE_IDX … #define regMMEA2_DRAM_RD_LAZY … #define regMMEA2_DRAM_RD_LAZY_BASE_IDX … #define regMMEA2_DRAM_WR_LAZY … #define regMMEA2_DRAM_WR_LAZY_BASE_IDX … #define regMMEA2_DRAM_RD_CAM_CNTL … #define regMMEA2_DRAM_RD_CAM_CNTL_BASE_IDX … #define regMMEA2_DRAM_WR_CAM_CNTL … #define regMMEA2_DRAM_WR_CAM_CNTL_BASE_IDX … #define regMMEA2_DRAM_PAGE_BURST … #define regMMEA2_DRAM_PAGE_BURST_BASE_IDX … #define regMMEA2_DRAM_RD_PRI_AGE … #define regMMEA2_DRAM_RD_PRI_AGE_BASE_IDX … #define regMMEA2_DRAM_WR_PRI_AGE … #define regMMEA2_DRAM_WR_PRI_AGE_BASE_IDX … #define regMMEA2_DRAM_RD_PRI_QUEUING … #define regMMEA2_DRAM_RD_PRI_QUEUING_BASE_IDX … #define regMMEA2_DRAM_WR_PRI_QUEUING … #define regMMEA2_DRAM_WR_PRI_QUEUING_BASE_IDX … #define regMMEA2_DRAM_RD_PRI_FIXED … #define regMMEA2_DRAM_RD_PRI_FIXED_BASE_IDX … #define regMMEA2_DRAM_WR_PRI_FIXED … #define regMMEA2_DRAM_WR_PRI_FIXED_BASE_IDX … #define regMMEA2_DRAM_RD_PRI_URGENCY … #define regMMEA2_DRAM_RD_PRI_URGENCY_BASE_IDX … #define regMMEA2_DRAM_WR_PRI_URGENCY … #define regMMEA2_DRAM_WR_PRI_URGENCY_BASE_IDX … #define regMMEA2_DRAM_RD_PRI_QUANT_PRI1 … #define regMMEA2_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA2_DRAM_RD_PRI_QUANT_PRI2 … #define regMMEA2_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA2_DRAM_RD_PRI_QUANT_PRI3 … #define regMMEA2_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA2_DRAM_WR_PRI_QUANT_PRI1 … #define regMMEA2_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA2_DRAM_WR_PRI_QUANT_PRI2 … #define regMMEA2_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA2_DRAM_WR_PRI_QUANT_PRI3 … #define regMMEA2_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA2_GMI_RD_CLI2GRP_MAP0 … #define regMMEA2_GMI_RD_CLI2GRP_MAP0_BASE_IDX … #define regMMEA2_GMI_RD_CLI2GRP_MAP1 … #define regMMEA2_GMI_RD_CLI2GRP_MAP1_BASE_IDX … #define regMMEA2_GMI_WR_CLI2GRP_MAP0 … #define regMMEA2_GMI_WR_CLI2GRP_MAP0_BASE_IDX … #define regMMEA2_GMI_WR_CLI2GRP_MAP1 … #define regMMEA2_GMI_WR_CLI2GRP_MAP1_BASE_IDX … #define regMMEA2_GMI_RD_GRP2VC_MAP … #define regMMEA2_GMI_RD_GRP2VC_MAP_BASE_IDX … #define regMMEA2_GMI_WR_GRP2VC_MAP … #define regMMEA2_GMI_WR_GRP2VC_MAP_BASE_IDX … #define regMMEA2_GMI_RD_LAZY … #define regMMEA2_GMI_RD_LAZY_BASE_IDX … #define regMMEA2_GMI_WR_LAZY … #define regMMEA2_GMI_WR_LAZY_BASE_IDX … #define regMMEA2_GMI_RD_CAM_CNTL … #define regMMEA2_GMI_RD_CAM_CNTL_BASE_IDX … #define regMMEA2_GMI_WR_CAM_CNTL … #define regMMEA2_GMI_WR_CAM_CNTL_BASE_IDX … #define regMMEA2_GMI_PAGE_BURST … #define regMMEA2_GMI_PAGE_BURST_BASE_IDX … #define regMMEA2_GMI_RD_PRI_AGE … #define regMMEA2_GMI_RD_PRI_AGE_BASE_IDX … #define regMMEA2_GMI_WR_PRI_AGE … #define regMMEA2_GMI_WR_PRI_AGE_BASE_IDX … #define regMMEA2_GMI_RD_PRI_QUEUING … #define regMMEA2_GMI_RD_PRI_QUEUING_BASE_IDX … #define regMMEA2_GMI_WR_PRI_QUEUING … #define regMMEA2_GMI_WR_PRI_QUEUING_BASE_IDX … #define regMMEA2_GMI_RD_PRI_FIXED … #define regMMEA2_GMI_RD_PRI_FIXED_BASE_IDX … #define regMMEA2_GMI_WR_PRI_FIXED … #define regMMEA2_GMI_WR_PRI_FIXED_BASE_IDX … #define regMMEA2_GMI_RD_PRI_URGENCY … #define regMMEA2_GMI_RD_PRI_URGENCY_BASE_IDX … #define regMMEA2_GMI_WR_PRI_URGENCY … #define regMMEA2_GMI_WR_PRI_URGENCY_BASE_IDX … #define regMMEA2_GMI_RD_PRI_URGENCY_MASKING … #define regMMEA2_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX … #define regMMEA2_GMI_WR_PRI_URGENCY_MASKING … #define regMMEA2_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX … #define regMMEA2_GMI_RD_PRI_QUANT_PRI1 … #define regMMEA2_GMI_RD_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA2_GMI_RD_PRI_QUANT_PRI2 … #define regMMEA2_GMI_RD_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA2_GMI_RD_PRI_QUANT_PRI3 … #define regMMEA2_GMI_RD_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA2_GMI_WR_PRI_QUANT_PRI1 … #define regMMEA2_GMI_WR_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA2_GMI_WR_PRI_QUANT_PRI2 … #define regMMEA2_GMI_WR_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA2_GMI_WR_PRI_QUANT_PRI3 … #define regMMEA2_GMI_WR_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA2_IO_RD_CLI2GRP_MAP0 … #define regMMEA2_IO_RD_CLI2GRP_MAP0_BASE_IDX … #define regMMEA2_IO_RD_CLI2GRP_MAP1 … #define regMMEA2_IO_RD_CLI2GRP_MAP1_BASE_IDX … #define regMMEA2_IO_WR_CLI2GRP_MAP0 … #define regMMEA2_IO_WR_CLI2GRP_MAP0_BASE_IDX … #define regMMEA2_IO_WR_CLI2GRP_MAP1 … #define regMMEA2_IO_WR_CLI2GRP_MAP1_BASE_IDX … #define regMMEA2_IO_RD_COMBINE_FLUSH … #define regMMEA2_IO_RD_COMBINE_FLUSH_BASE_IDX … #define regMMEA2_IO_WR_COMBINE_FLUSH … #define regMMEA2_IO_WR_COMBINE_FLUSH_BASE_IDX … #define regMMEA2_IO_GROUP_BURST … #define regMMEA2_IO_GROUP_BURST_BASE_IDX … #define regMMEA2_IO_RD_PRI_AGE … #define regMMEA2_IO_RD_PRI_AGE_BASE_IDX … #define regMMEA2_IO_WR_PRI_AGE … #define regMMEA2_IO_WR_PRI_AGE_BASE_IDX … #define regMMEA2_IO_RD_PRI_QUEUING … #define regMMEA2_IO_RD_PRI_QUEUING_BASE_IDX … #define regMMEA2_IO_WR_PRI_QUEUING … #define regMMEA2_IO_WR_PRI_QUEUING_BASE_IDX … #define regMMEA2_IO_RD_PRI_FIXED … #define regMMEA2_IO_RD_PRI_FIXED_BASE_IDX … #define regMMEA2_IO_WR_PRI_FIXED … #define regMMEA2_IO_WR_PRI_FIXED_BASE_IDX … #define regMMEA2_IO_RD_PRI_URGENCY … #define regMMEA2_IO_RD_PRI_URGENCY_BASE_IDX … #define regMMEA2_IO_WR_PRI_URGENCY … #define regMMEA2_IO_WR_PRI_URGENCY_BASE_IDX … #define regMMEA2_IO_RD_PRI_URGENCY_MASKING … #define regMMEA2_IO_RD_PRI_URGENCY_MASKING_BASE_IDX … #define regMMEA2_IO_WR_PRI_URGENCY_MASKING … #define regMMEA2_IO_WR_PRI_URGENCY_MASKING_BASE_IDX … #define regMMEA2_IO_RD_PRI_QUANT_PRI1 … #define regMMEA2_IO_RD_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA2_IO_RD_PRI_QUANT_PRI2 … #define regMMEA2_IO_RD_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA2_IO_RD_PRI_QUANT_PRI3 … #define regMMEA2_IO_RD_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA2_IO_WR_PRI_QUANT_PRI1 … #define regMMEA2_IO_WR_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA2_IO_WR_PRI_QUANT_PRI2 … #define regMMEA2_IO_WR_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA2_IO_WR_PRI_QUANT_PRI3 … #define regMMEA2_IO_WR_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA2_SDP_ARB_DRAM … #define regMMEA2_SDP_ARB_DRAM_BASE_IDX … #define regMMEA2_SDP_ARB_GMI … #define regMMEA2_SDP_ARB_GMI_BASE_IDX … #define regMMEA2_SDP_ARB_FINAL … #define regMMEA2_SDP_ARB_FINAL_BASE_IDX … #define regMMEA2_SDP_DRAM_PRIORITY … #define regMMEA2_SDP_DRAM_PRIORITY_BASE_IDX … #define regMMEA2_SDP_GMI_PRIORITY … #define regMMEA2_SDP_GMI_PRIORITY_BASE_IDX … #define regMMEA2_SDP_IO_PRIORITY … #define regMMEA2_SDP_IO_PRIORITY_BASE_IDX … #define regMMEA2_SDP_CREDITS … #define regMMEA2_SDP_CREDITS_BASE_IDX … #define regMMEA2_SDP_TAG_RESERVE0 … #define regMMEA2_SDP_TAG_RESERVE0_BASE_IDX … #define regMMEA2_SDP_TAG_RESERVE1 … #define regMMEA2_SDP_TAG_RESERVE1_BASE_IDX … #define regMMEA2_SDP_VCC_RESERVE0 … #define regMMEA2_SDP_VCC_RESERVE0_BASE_IDX … #define regMMEA2_SDP_VCC_RESERVE1 … #define regMMEA2_SDP_VCC_RESERVE1_BASE_IDX … #define regMMEA2_SDP_VCD_RESERVE0 … #define regMMEA2_SDP_VCD_RESERVE0_BASE_IDX … #define regMMEA2_SDP_VCD_RESERVE1 … #define regMMEA2_SDP_VCD_RESERVE1_BASE_IDX … #define regMMEA2_SDP_REQ_CNTL … #define regMMEA2_SDP_REQ_CNTL_BASE_IDX … #define regMMEA2_MISC … #define regMMEA2_MISC_BASE_IDX … #define regMMEA2_LATENCY_SAMPLING … #define regMMEA2_LATENCY_SAMPLING_BASE_IDX … #define regMMEA2_PERFCOUNTER_LO … #define regMMEA2_PERFCOUNTER_LO_BASE_IDX … #define regMMEA2_PERFCOUNTER_HI … #define regMMEA2_PERFCOUNTER_HI_BASE_IDX … #define regMMEA2_PERFCOUNTER0_CFG … #define regMMEA2_PERFCOUNTER0_CFG_BASE_IDX … #define regMMEA2_PERFCOUNTER1_CFG … #define regMMEA2_PERFCOUNTER1_CFG_BASE_IDX … #define regMMEA2_PERFCOUNTER_RSLT_CNTL … #define regMMEA2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define regMMEA2_UE_ERR_STATUS_LO … #define regMMEA2_UE_ERR_STATUS_LO_BASE_IDX … #define regMMEA2_UE_ERR_STATUS_HI … #define regMMEA2_UE_ERR_STATUS_HI_BASE_IDX … #define regMMEA2_DSM_CNTL … #define regMMEA2_DSM_CNTL_BASE_IDX … #define regMMEA2_DSM_CNTLA … #define regMMEA2_DSM_CNTLA_BASE_IDX … #define regMMEA2_DSM_CNTLB … #define regMMEA2_DSM_CNTLB_BASE_IDX … #define regMMEA2_DSM_CNTL2 … #define regMMEA2_DSM_CNTL2_BASE_IDX … #define regMMEA2_DSM_CNTL2A … #define regMMEA2_DSM_CNTL2A_BASE_IDX … #define regMMEA2_DSM_CNTL2B … #define regMMEA2_DSM_CNTL2B_BASE_IDX … #define regMMEA2_CGTT_CLK_CTRL … #define regMMEA2_CGTT_CLK_CTRL_BASE_IDX … #define regMMEA2_EDC_MODE … #define regMMEA2_EDC_MODE_BASE_IDX … #define regMMEA2_ERR_STATUS … #define regMMEA2_ERR_STATUS_BASE_IDX … #define regMMEA2_MISC2 … #define regMMEA2_MISC2_BASE_IDX … #define regMMEA2_CE_ERR_STATUS_LO … #define regMMEA2_CE_ERR_STATUS_LO_BASE_IDX … #define regMMEA2_MISC_AON … #define regMMEA2_MISC_AON_BASE_IDX … #define regMMEA2_CE_ERR_STATUS_HI … #define regMMEA2_CE_ERR_STATUS_HI_BASE_IDX … // addressBlock: aid_mmhub_ea_mmeadec3 // base address: 0x61b00 #define regMMEA3_DRAM_RD_CLI2GRP_MAP0 … #define regMMEA3_DRAM_RD_CLI2GRP_MAP0_BASE_IDX … #define regMMEA3_DRAM_RD_CLI2GRP_MAP1 … #define regMMEA3_DRAM_RD_CLI2GRP_MAP1_BASE_IDX … #define regMMEA3_DRAM_WR_CLI2GRP_MAP0 … #define regMMEA3_DRAM_WR_CLI2GRP_MAP0_BASE_IDX … #define regMMEA3_DRAM_WR_CLI2GRP_MAP1 … #define regMMEA3_DRAM_WR_CLI2GRP_MAP1_BASE_IDX … #define regMMEA3_DRAM_RD_GRP2VC_MAP … #define regMMEA3_DRAM_RD_GRP2VC_MAP_BASE_IDX … #define regMMEA3_DRAM_WR_GRP2VC_MAP … #define regMMEA3_DRAM_WR_GRP2VC_MAP_BASE_IDX … #define regMMEA3_DRAM_RD_LAZY … #define regMMEA3_DRAM_RD_LAZY_BASE_IDX … #define regMMEA3_DRAM_WR_LAZY … #define regMMEA3_DRAM_WR_LAZY_BASE_IDX … #define regMMEA3_DRAM_RD_CAM_CNTL … #define regMMEA3_DRAM_RD_CAM_CNTL_BASE_IDX … #define regMMEA3_DRAM_WR_CAM_CNTL … #define regMMEA3_DRAM_WR_CAM_CNTL_BASE_IDX … #define regMMEA3_DRAM_PAGE_BURST … #define regMMEA3_DRAM_PAGE_BURST_BASE_IDX … #define regMMEA3_DRAM_RD_PRI_AGE … #define regMMEA3_DRAM_RD_PRI_AGE_BASE_IDX … #define regMMEA3_DRAM_WR_PRI_AGE … #define regMMEA3_DRAM_WR_PRI_AGE_BASE_IDX … #define regMMEA3_DRAM_RD_PRI_QUEUING … #define regMMEA3_DRAM_RD_PRI_QUEUING_BASE_IDX … #define regMMEA3_DRAM_WR_PRI_QUEUING … #define regMMEA3_DRAM_WR_PRI_QUEUING_BASE_IDX … #define regMMEA3_DRAM_RD_PRI_FIXED … #define regMMEA3_DRAM_RD_PRI_FIXED_BASE_IDX … #define regMMEA3_DRAM_WR_PRI_FIXED … #define regMMEA3_DRAM_WR_PRI_FIXED_BASE_IDX … #define regMMEA3_DRAM_RD_PRI_URGENCY … #define regMMEA3_DRAM_RD_PRI_URGENCY_BASE_IDX … #define regMMEA3_DRAM_WR_PRI_URGENCY … #define regMMEA3_DRAM_WR_PRI_URGENCY_BASE_IDX … #define regMMEA3_DRAM_RD_PRI_QUANT_PRI1 … #define regMMEA3_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA3_DRAM_RD_PRI_QUANT_PRI2 … #define regMMEA3_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA3_DRAM_RD_PRI_QUANT_PRI3 … #define regMMEA3_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA3_DRAM_WR_PRI_QUANT_PRI1 … #define regMMEA3_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA3_DRAM_WR_PRI_QUANT_PRI2 … #define regMMEA3_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA3_DRAM_WR_PRI_QUANT_PRI3 … #define regMMEA3_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA3_GMI_RD_CLI2GRP_MAP0 … #define regMMEA3_GMI_RD_CLI2GRP_MAP0_BASE_IDX … #define regMMEA3_GMI_RD_CLI2GRP_MAP1 … #define regMMEA3_GMI_RD_CLI2GRP_MAP1_BASE_IDX … #define regMMEA3_GMI_WR_CLI2GRP_MAP0 … #define regMMEA3_GMI_WR_CLI2GRP_MAP0_BASE_IDX … #define regMMEA3_GMI_WR_CLI2GRP_MAP1 … #define regMMEA3_GMI_WR_CLI2GRP_MAP1_BASE_IDX … #define regMMEA3_GMI_RD_GRP2VC_MAP … #define regMMEA3_GMI_RD_GRP2VC_MAP_BASE_IDX … #define regMMEA3_GMI_WR_GRP2VC_MAP … #define regMMEA3_GMI_WR_GRP2VC_MAP_BASE_IDX … #define regMMEA3_GMI_RD_LAZY … #define regMMEA3_GMI_RD_LAZY_BASE_IDX … #define regMMEA3_GMI_WR_LAZY … #define regMMEA3_GMI_WR_LAZY_BASE_IDX … #define regMMEA3_GMI_RD_CAM_CNTL … #define regMMEA3_GMI_RD_CAM_CNTL_BASE_IDX … #define regMMEA3_GMI_WR_CAM_CNTL … #define regMMEA3_GMI_WR_CAM_CNTL_BASE_IDX … #define regMMEA3_GMI_PAGE_BURST … #define regMMEA3_GMI_PAGE_BURST_BASE_IDX … #define regMMEA3_GMI_RD_PRI_AGE … #define regMMEA3_GMI_RD_PRI_AGE_BASE_IDX … #define regMMEA3_GMI_WR_PRI_AGE … #define regMMEA3_GMI_WR_PRI_AGE_BASE_IDX … #define regMMEA3_GMI_RD_PRI_QUEUING … #define regMMEA3_GMI_RD_PRI_QUEUING_BASE_IDX … #define regMMEA3_GMI_WR_PRI_QUEUING … #define regMMEA3_GMI_WR_PRI_QUEUING_BASE_IDX … #define regMMEA3_GMI_RD_PRI_FIXED … #define regMMEA3_GMI_RD_PRI_FIXED_BASE_IDX … #define regMMEA3_GMI_WR_PRI_FIXED … #define regMMEA3_GMI_WR_PRI_FIXED_BASE_IDX … #define regMMEA3_GMI_RD_PRI_URGENCY … #define regMMEA3_GMI_RD_PRI_URGENCY_BASE_IDX … #define regMMEA3_GMI_WR_PRI_URGENCY … #define regMMEA3_GMI_WR_PRI_URGENCY_BASE_IDX … #define regMMEA3_GMI_RD_PRI_URGENCY_MASKING … #define regMMEA3_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX … #define regMMEA3_GMI_WR_PRI_URGENCY_MASKING … #define regMMEA3_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX … #define regMMEA3_GMI_RD_PRI_QUANT_PRI1 … #define regMMEA3_GMI_RD_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA3_GMI_RD_PRI_QUANT_PRI2 … #define regMMEA3_GMI_RD_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA3_GMI_RD_PRI_QUANT_PRI3 … #define regMMEA3_GMI_RD_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA3_GMI_WR_PRI_QUANT_PRI1 … #define regMMEA3_GMI_WR_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA3_GMI_WR_PRI_QUANT_PRI2 … #define regMMEA3_GMI_WR_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA3_GMI_WR_PRI_QUANT_PRI3 … #define regMMEA3_GMI_WR_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA3_IO_RD_CLI2GRP_MAP0 … #define regMMEA3_IO_RD_CLI2GRP_MAP0_BASE_IDX … #define regMMEA3_IO_RD_CLI2GRP_MAP1 … #define regMMEA3_IO_RD_CLI2GRP_MAP1_BASE_IDX … #define regMMEA3_IO_WR_CLI2GRP_MAP0 … #define regMMEA3_IO_WR_CLI2GRP_MAP0_BASE_IDX … #define regMMEA3_IO_WR_CLI2GRP_MAP1 … #define regMMEA3_IO_WR_CLI2GRP_MAP1_BASE_IDX … #define regMMEA3_IO_RD_COMBINE_FLUSH … #define regMMEA3_IO_RD_COMBINE_FLUSH_BASE_IDX … #define regMMEA3_IO_WR_COMBINE_FLUSH … #define regMMEA3_IO_WR_COMBINE_FLUSH_BASE_IDX … #define regMMEA3_IO_GROUP_BURST … #define regMMEA3_IO_GROUP_BURST_BASE_IDX … #define regMMEA3_IO_RD_PRI_AGE … #define regMMEA3_IO_RD_PRI_AGE_BASE_IDX … #define regMMEA3_IO_WR_PRI_AGE … #define regMMEA3_IO_WR_PRI_AGE_BASE_IDX … #define regMMEA3_IO_RD_PRI_QUEUING … #define regMMEA3_IO_RD_PRI_QUEUING_BASE_IDX … #define regMMEA3_IO_WR_PRI_QUEUING … #define regMMEA3_IO_WR_PRI_QUEUING_BASE_IDX … #define regMMEA3_IO_RD_PRI_FIXED … #define regMMEA3_IO_RD_PRI_FIXED_BASE_IDX … #define regMMEA3_IO_WR_PRI_FIXED … #define regMMEA3_IO_WR_PRI_FIXED_BASE_IDX … #define regMMEA3_IO_RD_PRI_URGENCY … #define regMMEA3_IO_RD_PRI_URGENCY_BASE_IDX … #define regMMEA3_IO_WR_PRI_URGENCY … #define regMMEA3_IO_WR_PRI_URGENCY_BASE_IDX … #define regMMEA3_IO_RD_PRI_URGENCY_MASKING … #define regMMEA3_IO_RD_PRI_URGENCY_MASKING_BASE_IDX … #define regMMEA3_IO_WR_PRI_URGENCY_MASKING … #define regMMEA3_IO_WR_PRI_URGENCY_MASKING_BASE_IDX … #define regMMEA3_IO_RD_PRI_QUANT_PRI1 … #define regMMEA3_IO_RD_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA3_IO_RD_PRI_QUANT_PRI2 … #define regMMEA3_IO_RD_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA3_IO_RD_PRI_QUANT_PRI3 … #define regMMEA3_IO_RD_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA3_IO_WR_PRI_QUANT_PRI1 … #define regMMEA3_IO_WR_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA3_IO_WR_PRI_QUANT_PRI2 … #define regMMEA3_IO_WR_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA3_IO_WR_PRI_QUANT_PRI3 … #define regMMEA3_IO_WR_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA3_SDP_ARB_DRAM … #define regMMEA3_SDP_ARB_DRAM_BASE_IDX … #define regMMEA3_SDP_ARB_GMI … #define regMMEA3_SDP_ARB_GMI_BASE_IDX … #define regMMEA3_SDP_ARB_FINAL … #define regMMEA3_SDP_ARB_FINAL_BASE_IDX … #define regMMEA3_SDP_DRAM_PRIORITY … #define regMMEA3_SDP_DRAM_PRIORITY_BASE_IDX … #define regMMEA3_SDP_GMI_PRIORITY … #define regMMEA3_SDP_GMI_PRIORITY_BASE_IDX … #define regMMEA3_SDP_IO_PRIORITY … #define regMMEA3_SDP_IO_PRIORITY_BASE_IDX … #define regMMEA3_SDP_CREDITS … #define regMMEA3_SDP_CREDITS_BASE_IDX … #define regMMEA3_SDP_TAG_RESERVE0 … #define regMMEA3_SDP_TAG_RESERVE0_BASE_IDX … #define regMMEA3_SDP_TAG_RESERVE1 … #define regMMEA3_SDP_TAG_RESERVE1_BASE_IDX … #define regMMEA3_SDP_VCC_RESERVE0 … #define regMMEA3_SDP_VCC_RESERVE0_BASE_IDX … #define regMMEA3_SDP_VCC_RESERVE1 … #define regMMEA3_SDP_VCC_RESERVE1_BASE_IDX … #define regMMEA3_SDP_VCD_RESERVE0 … #define regMMEA3_SDP_VCD_RESERVE0_BASE_IDX … #define regMMEA3_SDP_VCD_RESERVE1 … #define regMMEA3_SDP_VCD_RESERVE1_BASE_IDX … #define regMMEA3_SDP_REQ_CNTL … #define regMMEA3_SDP_REQ_CNTL_BASE_IDX … #define regMMEA3_MISC … #define regMMEA3_MISC_BASE_IDX … #define regMMEA3_LATENCY_SAMPLING … #define regMMEA3_LATENCY_SAMPLING_BASE_IDX … #define regMMEA3_PERFCOUNTER_LO … #define regMMEA3_PERFCOUNTER_LO_BASE_IDX … #define regMMEA3_PERFCOUNTER_HI … #define regMMEA3_PERFCOUNTER_HI_BASE_IDX … #define regMMEA3_PERFCOUNTER0_CFG … #define regMMEA3_PERFCOUNTER0_CFG_BASE_IDX … #define regMMEA3_PERFCOUNTER1_CFG … #define regMMEA3_PERFCOUNTER1_CFG_BASE_IDX … #define regMMEA3_PERFCOUNTER_RSLT_CNTL … #define regMMEA3_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define regMMEA3_UE_ERR_STATUS_LO … #define regMMEA3_UE_ERR_STATUS_LO_BASE_IDX … #define regMMEA3_UE_ERR_STATUS_HI … #define regMMEA3_UE_ERR_STATUS_HI_BASE_IDX … #define regMMEA3_DSM_CNTL … #define regMMEA3_DSM_CNTL_BASE_IDX … #define regMMEA3_DSM_CNTLA … #define regMMEA3_DSM_CNTLA_BASE_IDX … #define regMMEA3_DSM_CNTLB … #define regMMEA3_DSM_CNTLB_BASE_IDX … #define regMMEA3_DSM_CNTL2 … #define regMMEA3_DSM_CNTL2_BASE_IDX … #define regMMEA3_DSM_CNTL2A … #define regMMEA3_DSM_CNTL2A_BASE_IDX … #define regMMEA3_DSM_CNTL2B … #define regMMEA3_DSM_CNTL2B_BASE_IDX … #define regMMEA3_CGTT_CLK_CTRL … #define regMMEA3_CGTT_CLK_CTRL_BASE_IDX … #define regMMEA3_EDC_MODE … #define regMMEA3_EDC_MODE_BASE_IDX … #define regMMEA3_ERR_STATUS … #define regMMEA3_ERR_STATUS_BASE_IDX … #define regMMEA3_MISC2 … #define regMMEA3_MISC2_BASE_IDX … #define regMMEA3_CE_ERR_STATUS_LO … #define regMMEA3_CE_ERR_STATUS_LO_BASE_IDX … #define regMMEA3_MISC_AON … #define regMMEA3_MISC_AON_BASE_IDX … #define regMMEA3_CE_ERR_STATUS_HI … #define regMMEA3_CE_ERR_STATUS_HI_BASE_IDX … // addressBlock: aid_mmhub_ea_mmeadec4 // base address: 0x62000 #define regMMEA4_DRAM_RD_CLI2GRP_MAP0 … #define regMMEA4_DRAM_RD_CLI2GRP_MAP0_BASE_IDX … #define regMMEA4_DRAM_RD_CLI2GRP_MAP1 … #define regMMEA4_DRAM_RD_CLI2GRP_MAP1_BASE_IDX … #define regMMEA4_DRAM_WR_CLI2GRP_MAP0 … #define regMMEA4_DRAM_WR_CLI2GRP_MAP0_BASE_IDX … #define regMMEA4_DRAM_WR_CLI2GRP_MAP1 … #define regMMEA4_DRAM_WR_CLI2GRP_MAP1_BASE_IDX … #define regMMEA4_DRAM_RD_GRP2VC_MAP … #define regMMEA4_DRAM_RD_GRP2VC_MAP_BASE_IDX … #define regMMEA4_DRAM_WR_GRP2VC_MAP … #define regMMEA4_DRAM_WR_GRP2VC_MAP_BASE_IDX … #define regMMEA4_DRAM_RD_LAZY … #define regMMEA4_DRAM_RD_LAZY_BASE_IDX … #define regMMEA4_DRAM_WR_LAZY … #define regMMEA4_DRAM_WR_LAZY_BASE_IDX … #define regMMEA4_DRAM_RD_CAM_CNTL … #define regMMEA4_DRAM_RD_CAM_CNTL_BASE_IDX … #define regMMEA4_DRAM_WR_CAM_CNTL … #define regMMEA4_DRAM_WR_CAM_CNTL_BASE_IDX … #define regMMEA4_DRAM_PAGE_BURST … #define regMMEA4_DRAM_PAGE_BURST_BASE_IDX … #define regMMEA4_DRAM_RD_PRI_AGE … #define regMMEA4_DRAM_RD_PRI_AGE_BASE_IDX … #define regMMEA4_DRAM_WR_PRI_AGE … #define regMMEA4_DRAM_WR_PRI_AGE_BASE_IDX … #define regMMEA4_DRAM_RD_PRI_QUEUING … #define regMMEA4_DRAM_RD_PRI_QUEUING_BASE_IDX … #define regMMEA4_DRAM_WR_PRI_QUEUING … #define regMMEA4_DRAM_WR_PRI_QUEUING_BASE_IDX … #define regMMEA4_DRAM_RD_PRI_FIXED … #define regMMEA4_DRAM_RD_PRI_FIXED_BASE_IDX … #define regMMEA4_DRAM_WR_PRI_FIXED … #define regMMEA4_DRAM_WR_PRI_FIXED_BASE_IDX … #define regMMEA4_DRAM_RD_PRI_URGENCY … #define regMMEA4_DRAM_RD_PRI_URGENCY_BASE_IDX … #define regMMEA4_DRAM_WR_PRI_URGENCY … #define regMMEA4_DRAM_WR_PRI_URGENCY_BASE_IDX … #define regMMEA4_DRAM_RD_PRI_QUANT_PRI1 … #define regMMEA4_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA4_DRAM_RD_PRI_QUANT_PRI2 … #define regMMEA4_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA4_DRAM_RD_PRI_QUANT_PRI3 … #define regMMEA4_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA4_DRAM_WR_PRI_QUANT_PRI1 … #define regMMEA4_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA4_DRAM_WR_PRI_QUANT_PRI2 … #define regMMEA4_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA4_DRAM_WR_PRI_QUANT_PRI3 … #define regMMEA4_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA4_GMI_RD_CLI2GRP_MAP0 … #define regMMEA4_GMI_RD_CLI2GRP_MAP0_BASE_IDX … #define regMMEA4_GMI_RD_CLI2GRP_MAP1 … #define regMMEA4_GMI_RD_CLI2GRP_MAP1_BASE_IDX … #define regMMEA4_GMI_WR_CLI2GRP_MAP0 … #define regMMEA4_GMI_WR_CLI2GRP_MAP0_BASE_IDX … #define regMMEA4_GMI_WR_CLI2GRP_MAP1 … #define regMMEA4_GMI_WR_CLI2GRP_MAP1_BASE_IDX … #define regMMEA4_GMI_RD_GRP2VC_MAP … #define regMMEA4_GMI_RD_GRP2VC_MAP_BASE_IDX … #define regMMEA4_GMI_WR_GRP2VC_MAP … #define regMMEA4_GMI_WR_GRP2VC_MAP_BASE_IDX … #define regMMEA4_GMI_RD_LAZY … #define regMMEA4_GMI_RD_LAZY_BASE_IDX … #define regMMEA4_GMI_WR_LAZY … #define regMMEA4_GMI_WR_LAZY_BASE_IDX … #define regMMEA4_GMI_RD_CAM_CNTL … #define regMMEA4_GMI_RD_CAM_CNTL_BASE_IDX … #define regMMEA4_GMI_WR_CAM_CNTL … #define regMMEA4_GMI_WR_CAM_CNTL_BASE_IDX … #define regMMEA4_GMI_PAGE_BURST … #define regMMEA4_GMI_PAGE_BURST_BASE_IDX … #define regMMEA4_GMI_RD_PRI_AGE … #define regMMEA4_GMI_RD_PRI_AGE_BASE_IDX … #define regMMEA4_GMI_WR_PRI_AGE … #define regMMEA4_GMI_WR_PRI_AGE_BASE_IDX … #define regMMEA4_GMI_RD_PRI_QUEUING … #define regMMEA4_GMI_RD_PRI_QUEUING_BASE_IDX … #define regMMEA4_GMI_WR_PRI_QUEUING … #define regMMEA4_GMI_WR_PRI_QUEUING_BASE_IDX … #define regMMEA4_GMI_RD_PRI_FIXED … #define regMMEA4_GMI_RD_PRI_FIXED_BASE_IDX … #define regMMEA4_GMI_WR_PRI_FIXED … #define regMMEA4_GMI_WR_PRI_FIXED_BASE_IDX … #define regMMEA4_GMI_RD_PRI_URGENCY … #define regMMEA4_GMI_RD_PRI_URGENCY_BASE_IDX … #define regMMEA4_GMI_WR_PRI_URGENCY … #define regMMEA4_GMI_WR_PRI_URGENCY_BASE_IDX … #define regMMEA4_GMI_RD_PRI_URGENCY_MASKING … #define regMMEA4_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX … #define regMMEA4_GMI_WR_PRI_URGENCY_MASKING … #define regMMEA4_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX … #define regMMEA4_GMI_RD_PRI_QUANT_PRI1 … #define regMMEA4_GMI_RD_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA4_GMI_RD_PRI_QUANT_PRI2 … #define regMMEA4_GMI_RD_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA4_GMI_RD_PRI_QUANT_PRI3 … #define regMMEA4_GMI_RD_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA4_GMI_WR_PRI_QUANT_PRI1 … #define regMMEA4_GMI_WR_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA4_GMI_WR_PRI_QUANT_PRI2 … #define regMMEA4_GMI_WR_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA4_GMI_WR_PRI_QUANT_PRI3 … #define regMMEA4_GMI_WR_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA4_IO_RD_CLI2GRP_MAP0 … #define regMMEA4_IO_RD_CLI2GRP_MAP0_BASE_IDX … #define regMMEA4_IO_RD_CLI2GRP_MAP1 … #define regMMEA4_IO_RD_CLI2GRP_MAP1_BASE_IDX … #define regMMEA4_IO_WR_CLI2GRP_MAP0 … #define regMMEA4_IO_WR_CLI2GRP_MAP0_BASE_IDX … #define regMMEA4_IO_WR_CLI2GRP_MAP1 … #define regMMEA4_IO_WR_CLI2GRP_MAP1_BASE_IDX … #define regMMEA4_IO_RD_COMBINE_FLUSH … #define regMMEA4_IO_RD_COMBINE_FLUSH_BASE_IDX … #define regMMEA4_IO_WR_COMBINE_FLUSH … #define regMMEA4_IO_WR_COMBINE_FLUSH_BASE_IDX … #define regMMEA4_IO_GROUP_BURST … #define regMMEA4_IO_GROUP_BURST_BASE_IDX … #define regMMEA4_IO_RD_PRI_AGE … #define regMMEA4_IO_RD_PRI_AGE_BASE_IDX … #define regMMEA4_IO_WR_PRI_AGE … #define regMMEA4_IO_WR_PRI_AGE_BASE_IDX … #define regMMEA4_IO_RD_PRI_QUEUING … #define regMMEA4_IO_RD_PRI_QUEUING_BASE_IDX … #define regMMEA4_IO_WR_PRI_QUEUING … #define regMMEA4_IO_WR_PRI_QUEUING_BASE_IDX … #define regMMEA4_IO_RD_PRI_FIXED … #define regMMEA4_IO_RD_PRI_FIXED_BASE_IDX … #define regMMEA4_IO_WR_PRI_FIXED … #define regMMEA4_IO_WR_PRI_FIXED_BASE_IDX … #define regMMEA4_IO_RD_PRI_URGENCY … #define regMMEA4_IO_RD_PRI_URGENCY_BASE_IDX … #define regMMEA4_IO_WR_PRI_URGENCY … #define regMMEA4_IO_WR_PRI_URGENCY_BASE_IDX … #define regMMEA4_IO_RD_PRI_URGENCY_MASKING … #define regMMEA4_IO_RD_PRI_URGENCY_MASKING_BASE_IDX … #define regMMEA4_IO_WR_PRI_URGENCY_MASKING … #define regMMEA4_IO_WR_PRI_URGENCY_MASKING_BASE_IDX … #define regMMEA4_IO_RD_PRI_QUANT_PRI1 … #define regMMEA4_IO_RD_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA4_IO_RD_PRI_QUANT_PRI2 … #define regMMEA4_IO_RD_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA4_IO_RD_PRI_QUANT_PRI3 … #define regMMEA4_IO_RD_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA4_IO_WR_PRI_QUANT_PRI1 … #define regMMEA4_IO_WR_PRI_QUANT_PRI1_BASE_IDX … #define regMMEA4_IO_WR_PRI_QUANT_PRI2 … #define regMMEA4_IO_WR_PRI_QUANT_PRI2_BASE_IDX … #define regMMEA4_IO_WR_PRI_QUANT_PRI3 … #define regMMEA4_IO_WR_PRI_QUANT_PRI3_BASE_IDX … #define regMMEA4_SDP_ARB_DRAM … #define regMMEA4_SDP_ARB_DRAM_BASE_IDX … #define regMMEA4_SDP_ARB_GMI … #define regMMEA4_SDP_ARB_GMI_BASE_IDX … #define regMMEA4_SDP_ARB_FINAL … #define regMMEA4_SDP_ARB_FINAL_BASE_IDX … #define regMMEA4_SDP_DRAM_PRIORITY … #define regMMEA4_SDP_DRAM_PRIORITY_BASE_IDX … #define regMMEA4_SDP_GMI_PRIORITY … #define regMMEA4_SDP_GMI_PRIORITY_BASE_IDX … #define regMMEA4_SDP_IO_PRIORITY … #define regMMEA4_SDP_IO_PRIORITY_BASE_IDX … #define regMMEA4_SDP_CREDITS … #define regMMEA4_SDP_CREDITS_BASE_IDX … #define regMMEA4_SDP_TAG_RESERVE0 … #define regMMEA4_SDP_TAG_RESERVE0_BASE_IDX … #define regMMEA4_SDP_TAG_RESERVE1 … #define regMMEA4_SDP_TAG_RESERVE1_BASE_IDX … #define regMMEA4_SDP_VCC_RESERVE0 … #define regMMEA4_SDP_VCC_RESERVE0_BASE_IDX … #define regMMEA4_SDP_VCC_RESERVE1 … #define regMMEA4_SDP_VCC_RESERVE1_BASE_IDX … #define regMMEA4_SDP_VCD_RESERVE0 … #define regMMEA4_SDP_VCD_RESERVE0_BASE_IDX … #define regMMEA4_SDP_VCD_RESERVE1 … #define regMMEA4_SDP_VCD_RESERVE1_BASE_IDX … #define regMMEA4_SDP_REQ_CNTL … #define regMMEA4_SDP_REQ_CNTL_BASE_IDX … #define regMMEA4_MISC … #define regMMEA4_MISC_BASE_IDX … #define regMMEA4_LATENCY_SAMPLING … #define regMMEA4_LATENCY_SAMPLING_BASE_IDX … #define regMMEA4_PERFCOUNTER_LO … #define regMMEA4_PERFCOUNTER_LO_BASE_IDX … #define regMMEA4_PERFCOUNTER_HI … #define regMMEA4_PERFCOUNTER_HI_BASE_IDX … #define regMMEA4_PERFCOUNTER0_CFG … #define regMMEA4_PERFCOUNTER0_CFG_BASE_IDX … #define regMMEA4_PERFCOUNTER1_CFG … #define regMMEA4_PERFCOUNTER1_CFG_BASE_IDX … #define regMMEA4_PERFCOUNTER_RSLT_CNTL … #define regMMEA4_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define regMMEA4_UE_ERR_STATUS_LO … #define regMMEA4_UE_ERR_STATUS_LO_BASE_IDX … #define regMMEA4_UE_ERR_STATUS_HI … #define regMMEA4_UE_ERR_STATUS_HI_BASE_IDX … #define regMMEA4_DSM_CNTL … #define regMMEA4_DSM_CNTL_BASE_IDX … #define regMMEA4_DSM_CNTLA … #define regMMEA4_DSM_CNTLA_BASE_IDX … #define regMMEA4_DSM_CNTLB … #define regMMEA4_DSM_CNTLB_BASE_IDX … #define regMMEA4_DSM_CNTL2 … #define regMMEA4_DSM_CNTL2_BASE_IDX … #define regMMEA4_DSM_CNTL2A … #define regMMEA4_DSM_CNTL2A_BASE_IDX … #define regMMEA4_DSM_CNTL2B … #define regMMEA4_DSM_CNTL2B_BASE_IDX … #define regMMEA4_CGTT_CLK_CTRL … #define regMMEA4_CGTT_CLK_CTRL_BASE_IDX … #define regMMEA4_EDC_MODE … #define regMMEA4_EDC_MODE_BASE_IDX … #define regMMEA4_ERR_STATUS … #define regMMEA4_ERR_STATUS_BASE_IDX … #define regMMEA4_MISC2 … #define regMMEA4_MISC2_BASE_IDX … #define regMMEA4_CE_ERR_STATUS_LO … #define regMMEA4_CE_ERR_STATUS_LO_BASE_IDX … #define regMMEA4_MISC_AON … #define regMMEA4_MISC_AON_BASE_IDX … #define regMMEA4_CE_ERR_STATUS_HI … #define regMMEA4_CE_ERR_STATUS_HI_BASE_IDX … // addressBlock: aid_mmhub_pctldec0 // base address: 0x62a00 #define regPCTL0_CTRL … #define regPCTL0_CTRL_BASE_IDX … #define regPCTL0_MMHUB_DEEPSLEEP_IB … #define regPCTL0_MMHUB_DEEPSLEEP_IB_BASE_IDX … #define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE … #define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX … #define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB … #define regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX … #define regPCTL0_PG_IGNORE_DEEPSLEEP … #define regPCTL0_PG_IGNORE_DEEPSLEEP_BASE_IDX … #define regPCTL0_PG_IGNORE_DEEPSLEEP_IB … #define regPCTL0_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX … #define regPCTL0_SLICE0_CFG_DAGB_BUSY … #define regPCTL0_SLICE0_CFG_DAGB_BUSY_BASE_IDX … #define regPCTL0_SLICE0_CFG_DS_ALLOW … #define regPCTL0_SLICE0_CFG_DS_ALLOW_BASE_IDX … #define regPCTL0_SLICE0_CFG_DS_ALLOW_IB … #define regPCTL0_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX … #define regPCTL0_SLICE1_CFG_DAGB_BUSY … #define regPCTL0_SLICE1_CFG_DAGB_BUSY_BASE_IDX … #define regPCTL0_SLICE1_CFG_DS_ALLOW … #define regPCTL0_SLICE1_CFG_DS_ALLOW_BASE_IDX … #define regPCTL0_SLICE1_CFG_DS_ALLOW_IB … #define regPCTL0_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX … #define regPCTL0_SLICE2_CFG_DAGB_BUSY … #define regPCTL0_SLICE2_CFG_DAGB_BUSY_BASE_IDX … #define regPCTL0_SLICE2_CFG_DS_ALLOW … #define regPCTL0_SLICE2_CFG_DS_ALLOW_BASE_IDX … #define regPCTL0_SLICE2_CFG_DS_ALLOW_IB … #define regPCTL0_SLICE2_CFG_DS_ALLOW_IB_BASE_IDX … #define regPCTL0_SLICE3_CFG_DAGB_BUSY … #define regPCTL0_SLICE3_CFG_DAGB_BUSY_BASE_IDX … #define regPCTL0_SLICE3_CFG_DS_ALLOW … #define regPCTL0_SLICE3_CFG_DS_ALLOW_BASE_IDX … #define regPCTL0_SLICE3_CFG_DS_ALLOW_IB … #define regPCTL0_SLICE3_CFG_DS_ALLOW_IB_BASE_IDX … #define regPCTL0_SLICE4_CFG_DAGB_BUSY … #define regPCTL0_SLICE4_CFG_DAGB_BUSY_BASE_IDX … #define regPCTL0_SLICE4_CFG_DS_ALLOW … #define regPCTL0_SLICE4_CFG_DS_ALLOW_BASE_IDX … #define regPCTL0_SLICE4_CFG_DS_ALLOW_IB … #define regPCTL0_SLICE4_CFG_DS_ALLOW_IB_BASE_IDX … #define regPCTL0_UTCL2_MISC … #define regPCTL0_UTCL2_MISC_BASE_IDX … #define regPCTL0_SLICE0_MISC … #define regPCTL0_SLICE0_MISC_BASE_IDX … #define regPCTL0_SLICE1_MISC … #define regPCTL0_SLICE1_MISC_BASE_IDX … #define regPCTL0_SLICE2_MISC … #define regPCTL0_SLICE2_MISC_BASE_IDX … #define regPCTL0_SLICE3_MISC … #define regPCTL0_SLICE3_MISC_BASE_IDX … #define regPCTL0_SLICE4_MISC … #define regPCTL0_SLICE4_MISC_BASE_IDX … // addressBlock: aid_mmhub_l1tlb_vml1dec // base address: 0x62c00 #define regMC_VM_MX_L1_TLB0_STATUS … #define regMC_VM_MX_L1_TLB0_STATUS_BASE_IDX … #define regMC_VM_MX_L1_TLB1_STATUS … #define regMC_VM_MX_L1_TLB1_STATUS_BASE_IDX … #define regMC_VM_MX_L1_TLB2_STATUS … #define regMC_VM_MX_L1_TLB2_STATUS_BASE_IDX … #define regMC_VM_MX_L1_TLB3_STATUS … #define regMC_VM_MX_L1_TLB3_STATUS_BASE_IDX … #define regMC_VM_MX_L1_TLB4_STATUS … #define regMC_VM_MX_L1_TLB4_STATUS_BASE_IDX … #define regMC_VM_MX_L1_TLB5_STATUS … #define regMC_VM_MX_L1_TLB5_STATUS_BASE_IDX … #define regMC_VM_MX_L1_TLB6_STATUS … #define regMC_VM_MX_L1_TLB6_STATUS_BASE_IDX … #define regMC_VM_MX_L1_TLB7_STATUS … #define regMC_VM_MX_L1_TLB7_STATUS_BASE_IDX … // addressBlock: aid_mmhub_l1tlb_vml1pldec // base address: 0x62c80 #define regMC_VM_MX_L1_PERFCOUNTER0_CFG … #define regMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX … #define regMC_VM_MX_L1_PERFCOUNTER1_CFG … #define regMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX … #define regMC_VM_MX_L1_PERFCOUNTER2_CFG … #define regMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX … #define regMC_VM_MX_L1_PERFCOUNTER3_CFG … #define regMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX … #define regMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL … #define regMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: aid_mmhub_l1tlb_vml1prdec // base address: 0x62cc0 #define regMC_VM_MX_L1_PERFCOUNTER_LO … #define regMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX … #define regMC_VM_MX_L1_PERFCOUNTER_HI … #define regMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX … // addressBlock: aid_mmhub_utcl2_atcl2dec // base address: 0x62d00 #define regATC_L2_CNTL … #define regATC_L2_CNTL_BASE_IDX … #define regATC_L2_CNTL2 … #define regATC_L2_CNTL2_BASE_IDX … #define regATC_L2_CACHE_DATA0 … #define regATC_L2_CACHE_DATA0_BASE_IDX … #define regATC_L2_CACHE_DATA1 … #define regATC_L2_CACHE_DATA1_BASE_IDX … #define regATC_L2_CACHE_DATA2 … #define regATC_L2_CACHE_DATA2_BASE_IDX … #define regATC_L2_CACHE_DATA3 … #define regATC_L2_CACHE_DATA3_BASE_IDX … #define regATC_L2_CNTL3 … #define regATC_L2_CNTL3_BASE_IDX … #define regATC_L2_STATUS … #define regATC_L2_STATUS_BASE_IDX … #define regATC_L2_STATUS2 … #define regATC_L2_STATUS2_BASE_IDX … #define regATC_L2_MISC_CG … #define regATC_L2_MISC_CG_BASE_IDX … #define regATC_L2_MEM_POWER_LS … #define regATC_L2_MEM_POWER_LS_BASE_IDX … #define regATC_L2_CGTT_CLK_CTRL … #define regATC_L2_CGTT_CLK_CTRL_BASE_IDX … #define regATC_L2_CACHE_4K_DSM_INDEX … #define regATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX … #define regATC_L2_CACHE_32K_DSM_INDEX … #define regATC_L2_CACHE_32K_DSM_INDEX_BASE_IDX … #define regATC_L2_CACHE_2M_DSM_INDEX … #define regATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX … #define regATC_L2_CACHE_4K_DSM_CNTL … #define regATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX … #define regATC_L2_CACHE_32K_DSM_CNTL … #define regATC_L2_CACHE_32K_DSM_CNTL_BASE_IDX … #define regATC_L2_CACHE_2M_DSM_CNTL … #define regATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX … #define regATC_L2_CNTL4 … #define regATC_L2_CNTL4_BASE_IDX … #define regATC_L2_MM_GROUP_RT_CLASSES … #define regATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX … // addressBlock: aid_mmhub_utcl2_vml2pfdec // base address: 0x62d80 #define regVM_L2_CNTL … #define regVM_L2_CNTL_BASE_IDX … #define regVM_L2_CNTL2 … #define regVM_L2_CNTL2_BASE_IDX … #define regVM_L2_CNTL3 … #define regVM_L2_CNTL3_BASE_IDX … #define regVM_L2_STATUS … #define regVM_L2_STATUS_BASE_IDX … #define regVM_DUMMY_PAGE_FAULT_CNTL … #define regVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX … #define regVM_DUMMY_PAGE_FAULT_ADDR_LO32 … #define regVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX … #define regVM_DUMMY_PAGE_FAULT_ADDR_HI32 … #define regVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX … #define regVM_L2_PROTECTION_FAULT_CNTL … #define regVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX … #define regVM_L2_PROTECTION_FAULT_CNTL2 … #define regVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX … #define regVM_L2_PROTECTION_FAULT_MM_CNTL3 … #define regVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX … #define regVM_L2_PROTECTION_FAULT_MM_CNTL4 … #define regVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX … #define regVM_L2_PROTECTION_FAULT_STATUS … #define regVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX … #define regVM_L2_PROTECTION_FAULT_ADDR_LO32 … #define regVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX … #define regVM_L2_PROTECTION_FAULT_ADDR_HI32 … #define regVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX … #define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 … #define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX … #define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 … #define regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX … #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 … #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX … #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 … #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX … #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 … #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX … #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 … #define regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX … #define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 … #define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX … #define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 … #define regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX … #define regVM_L2_CNTL4 … #define regVM_L2_CNTL4_BASE_IDX … #define regVM_L2_CNTL5 … #define regVM_L2_CNTL5_BASE_IDX … #define regVM_L2_MM_GROUP_RT_CLASSES … #define regVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX … #define regVM_L2_BANK_SELECT_RESERVED_CID … #define regVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX … #define regVM_L2_BANK_SELECT_RESERVED_CID2 … #define regVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX … #define regVM_L2_CACHE_PARITY_CNTL … #define regVM_L2_CACHE_PARITY_CNTL_BASE_IDX … #define regVM_L2_CGTT_CLK_CTRL … #define regVM_L2_CGTT_CLK_CTRL_BASE_IDX … #define regVM_L2_CGTT_BUSY_CTRL … #define regVM_L2_CGTT_BUSY_CTRL_BASE_IDX … #define regVML2_MEM_ECC_INDEX … #define regVML2_MEM_ECC_INDEX_BASE_IDX … #define regVML2_WALKER_MEM_ECC_INDEX … #define regVML2_WALKER_MEM_ECC_INDEX_BASE_IDX … #define regUTCL2_MEM_ECC_INDEX … #define regUTCL2_MEM_ECC_INDEX_BASE_IDX … #define regVML2_MEM_ECC_CNTL … #define regVML2_MEM_ECC_CNTL_BASE_IDX … #define regVML2_WALKER_MEM_ECC_CNTL … #define regVML2_WALKER_MEM_ECC_CNTL_BASE_IDX … #define regUTCL2_MEM_ECC_CNTL … #define regUTCL2_MEM_ECC_CNTL_BASE_IDX … #define regVML2_MEM_ECC_STATUS … #define regVML2_MEM_ECC_STATUS_BASE_IDX … #define regVML2_WALKER_MEM_ECC_STATUS … #define regVML2_WALKER_MEM_ECC_STATUS_BASE_IDX … #define regUTCL2_MEM_ECC_STATUS … #define regUTCL2_MEM_ECC_STATUS_BASE_IDX … #define regUTCL2_EDC_MODE … #define regUTCL2_EDC_MODE_BASE_IDX … #define regUTCL2_EDC_CONFIG … #define regUTCL2_EDC_CONFIG_BASE_IDX … // addressBlock: aid_mmhub_utcl2_vml2vcdec // base address: 0x62e80 #define regVM_CONTEXT0_CNTL … #define regVM_CONTEXT0_CNTL_BASE_IDX … #define regVM_CONTEXT1_CNTL … #define regVM_CONTEXT1_CNTL_BASE_IDX … #define regVM_CONTEXT2_CNTL … #define regVM_CONTEXT2_CNTL_BASE_IDX … #define regVM_CONTEXT3_CNTL … #define regVM_CONTEXT3_CNTL_BASE_IDX … #define regVM_CONTEXT4_CNTL … #define regVM_CONTEXT4_CNTL_BASE_IDX … #define regVM_CONTEXT5_CNTL … #define regVM_CONTEXT5_CNTL_BASE_IDX … #define regVM_CONTEXT6_CNTL … #define regVM_CONTEXT6_CNTL_BASE_IDX … #define regVM_CONTEXT7_CNTL … #define regVM_CONTEXT7_CNTL_BASE_IDX … #define regVM_CONTEXT8_CNTL … #define regVM_CONTEXT8_CNTL_BASE_IDX … #define regVM_CONTEXT9_CNTL … #define regVM_CONTEXT9_CNTL_BASE_IDX … #define regVM_CONTEXT10_CNTL … #define regVM_CONTEXT10_CNTL_BASE_IDX … #define regVM_CONTEXT11_CNTL … #define regVM_CONTEXT11_CNTL_BASE_IDX … #define regVM_CONTEXT12_CNTL … #define regVM_CONTEXT12_CNTL_BASE_IDX … #define regVM_CONTEXT13_CNTL … #define regVM_CONTEXT13_CNTL_BASE_IDX … #define regVM_CONTEXT14_CNTL … #define regVM_CONTEXT14_CNTL_BASE_IDX … #define regVM_CONTEXT15_CNTL … #define regVM_CONTEXT15_CNTL_BASE_IDX … #define regVM_CONTEXTS_DISABLE … #define regVM_CONTEXTS_DISABLE_BASE_IDX … #define regVM_INVALIDATE_ENG0_SEM … #define regVM_INVALIDATE_ENG0_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG1_SEM … #define regVM_INVALIDATE_ENG1_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG2_SEM … #define regVM_INVALIDATE_ENG2_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG3_SEM … #define regVM_INVALIDATE_ENG3_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG4_SEM … #define regVM_INVALIDATE_ENG4_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG5_SEM … #define regVM_INVALIDATE_ENG5_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG6_SEM … #define regVM_INVALIDATE_ENG6_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG7_SEM … #define regVM_INVALIDATE_ENG7_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG8_SEM … #define regVM_INVALIDATE_ENG8_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG9_SEM … #define regVM_INVALIDATE_ENG9_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG10_SEM … #define regVM_INVALIDATE_ENG10_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG11_SEM … #define regVM_INVALIDATE_ENG11_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG12_SEM … #define regVM_INVALIDATE_ENG12_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG13_SEM … #define regVM_INVALIDATE_ENG13_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG14_SEM … #define regVM_INVALIDATE_ENG14_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG15_SEM … #define regVM_INVALIDATE_ENG15_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG16_SEM … #define regVM_INVALIDATE_ENG16_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG17_SEM … #define regVM_INVALIDATE_ENG17_SEM_BASE_IDX … #define regVM_INVALIDATE_ENG0_REQ … #define regVM_INVALIDATE_ENG0_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG1_REQ … #define regVM_INVALIDATE_ENG1_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG2_REQ … #define regVM_INVALIDATE_ENG2_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG3_REQ … #define regVM_INVALIDATE_ENG3_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG4_REQ … #define regVM_INVALIDATE_ENG4_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG5_REQ … #define regVM_INVALIDATE_ENG5_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG6_REQ … #define regVM_INVALIDATE_ENG6_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG7_REQ … #define regVM_INVALIDATE_ENG7_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG8_REQ … #define regVM_INVALIDATE_ENG8_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG9_REQ … #define regVM_INVALIDATE_ENG9_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG10_REQ … #define regVM_INVALIDATE_ENG10_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG11_REQ … #define regVM_INVALIDATE_ENG11_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG12_REQ … #define regVM_INVALIDATE_ENG12_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG13_REQ … #define regVM_INVALIDATE_ENG13_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG14_REQ … #define regVM_INVALIDATE_ENG14_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG15_REQ … #define regVM_INVALIDATE_ENG15_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG16_REQ … #define regVM_INVALIDATE_ENG16_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG17_REQ … #define regVM_INVALIDATE_ENG17_REQ_BASE_IDX … #define regVM_INVALIDATE_ENG0_ACK … #define regVM_INVALIDATE_ENG0_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG1_ACK … #define regVM_INVALIDATE_ENG1_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG2_ACK … #define regVM_INVALIDATE_ENG2_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG3_ACK … #define regVM_INVALIDATE_ENG3_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG4_ACK … #define regVM_INVALIDATE_ENG4_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG5_ACK … #define regVM_INVALIDATE_ENG5_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG6_ACK … #define regVM_INVALIDATE_ENG6_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG7_ACK … #define regVM_INVALIDATE_ENG7_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG8_ACK … #define regVM_INVALIDATE_ENG8_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG9_ACK … #define regVM_INVALIDATE_ENG9_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG10_ACK … #define regVM_INVALIDATE_ENG10_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG11_ACK … #define regVM_INVALIDATE_ENG11_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG12_ACK … #define regVM_INVALIDATE_ENG12_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG13_ACK … #define regVM_INVALIDATE_ENG13_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG14_ACK … #define regVM_INVALIDATE_ENG14_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG15_ACK … #define regVM_INVALIDATE_ENG15_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG16_ACK … #define regVM_INVALIDATE_ENG16_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG17_ACK … #define regVM_INVALIDATE_ENG17_ACK_BASE_IDX … #define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX … #define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 … #define regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX … #define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 … #define regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX … #define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 … #define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 … #define regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 … #define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 … #define regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 … #define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 … #define regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … // addressBlock: aid_mmhub_utcl2_vmsharedpfdec // base address: 0x63200 #define regMC_VM_NB_MMIOBASE … #define regMC_VM_NB_MMIOBASE_BASE_IDX … #define regMC_VM_NB_MMIOLIMIT … #define regMC_VM_NB_MMIOLIMIT_BASE_IDX … #define regMC_VM_NB_PCI_CTRL … #define regMC_VM_NB_PCI_CTRL_BASE_IDX … #define regMC_VM_NB_PCI_ARB … #define regMC_VM_NB_PCI_ARB_BASE_IDX … #define regMC_VM_NB_TOP_OF_DRAM_SLOT1 … #define regMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX … #define regMC_VM_NB_LOWER_TOP_OF_DRAM2 … #define regMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX … #define regMC_VM_NB_UPPER_TOP_OF_DRAM2 … #define regMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX … #define regMC_VM_FB_OFFSET … #define regMC_VM_FB_OFFSET_BASE_IDX … #define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB … #define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX … #define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB … #define regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX … #define regMC_VM_STEERING … #define regMC_VM_STEERING_BASE_IDX … #define regMC_SHARED_VIRT_RESET_REQ … #define regMC_SHARED_VIRT_RESET_REQ_BASE_IDX … #define regMC_MEM_POWER_LS … #define regMC_MEM_POWER_LS_BASE_IDX … #define regMC_VM_CACHEABLE_DRAM_ADDRESS_START … #define regMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX … #define regMC_VM_CACHEABLE_DRAM_ADDRESS_END … #define regMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX … #define regMC_VM_APT_CNTL … #define regMC_VM_APT_CNTL_BASE_IDX … #define regMC_VM_LOCAL_HBM_ADDRESS_START … #define regMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX … #define regMC_VM_LOCAL_HBM_ADDRESS_END … #define regMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX … #define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL … #define regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX … #define regUTCL2_CGTT_CLK_CTRL … #define regUTCL2_CGTT_CLK_CTRL_BASE_IDX … #define regMC_VM_XGMI_LFB_CNTL … #define regMC_VM_XGMI_LFB_CNTL_BASE_IDX … #define regMC_VM_XGMI_LFB_SIZE … #define regMC_VM_XGMI_LFB_SIZE_BASE_IDX … #define regMC_VM_CACHEABLE_DRAM_CNTL … #define regMC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX … #define regMC_VM_HOST_MAPPING … #define regMC_VM_HOST_MAPPING_BASE_IDX … // addressBlock: aid_mmhub_utcl2_vmsharedvcdec // base address: 0x63270 #define regMC_VM_FB_LOCATION_BASE … #define regMC_VM_FB_LOCATION_BASE_BASE_IDX … #define regMC_VM_FB_LOCATION_TOP … #define regMC_VM_FB_LOCATION_TOP_BASE_IDX … #define regMC_VM_AGP_TOP … #define regMC_VM_AGP_TOP_BASE_IDX … #define regMC_VM_AGP_BOT … #define regMC_VM_AGP_BOT_BASE_IDX … #define regMC_VM_AGP_BASE … #define regMC_VM_AGP_BASE_BASE_IDX … #define regMC_VM_SYSTEM_APERTURE_LOW_ADDR … #define regMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX … #define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR … #define regMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX … #define regMC_VM_MX_L1_TLB_CNTL … #define regMC_VM_MX_L1_TLB_CNTL_BASE_IDX … // addressBlock: aid_mmhub_utcl2_vmsharedhvdec // base address: 0x632b0 #define regMC_VM_FB_SIZE_OFFSET_VF0 … #define regMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF1 … #define regMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF2 … #define regMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF3 … #define regMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF4 … #define regMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF5 … #define regMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF6 … #define regMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF7 … #define regMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF8 … #define regMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF9 … #define regMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF10 … #define regMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF11 … #define regMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF12 … #define regMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF13 … #define regMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF14 … #define regMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX … #define regMC_VM_FB_SIZE_OFFSET_VF15 … #define regMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX … #define regVM_IOMMU_MMIO_CNTRL_1 … #define regVM_IOMMU_MMIO_CNTRL_1_BASE_IDX … #define regMC_VM_MARC_BASE_LO_0 … #define regMC_VM_MARC_BASE_LO_0_BASE_IDX … #define regMC_VM_MARC_BASE_LO_1 … #define regMC_VM_MARC_BASE_LO_1_BASE_IDX … #define regMC_VM_MARC_BASE_LO_2 … #define regMC_VM_MARC_BASE_LO_2_BASE_IDX … #define regMC_VM_MARC_BASE_LO_3 … #define regMC_VM_MARC_BASE_LO_3_BASE_IDX … #define regMC_VM_MARC_BASE_HI_0 … #define regMC_VM_MARC_BASE_HI_0_BASE_IDX … #define regMC_VM_MARC_BASE_HI_1 … #define regMC_VM_MARC_BASE_HI_1_BASE_IDX … #define regMC_VM_MARC_BASE_HI_2 … #define regMC_VM_MARC_BASE_HI_2_BASE_IDX … #define regMC_VM_MARC_BASE_HI_3 … #define regMC_VM_MARC_BASE_HI_3_BASE_IDX … #define regMC_VM_MARC_RELOC_LO_0 … #define regMC_VM_MARC_RELOC_LO_0_BASE_IDX … #define regMC_VM_MARC_RELOC_LO_1 … #define regMC_VM_MARC_RELOC_LO_1_BASE_IDX … #define regMC_VM_MARC_RELOC_LO_2 … #define regMC_VM_MARC_RELOC_LO_2_BASE_IDX … #define regMC_VM_MARC_RELOC_LO_3 … #define regMC_VM_MARC_RELOC_LO_3_BASE_IDX … #define regMC_VM_MARC_RELOC_HI_0 … #define regMC_VM_MARC_RELOC_HI_0_BASE_IDX … #define regMC_VM_MARC_RELOC_HI_1 … #define regMC_VM_MARC_RELOC_HI_1_BASE_IDX … #define regMC_VM_MARC_RELOC_HI_2 … #define regMC_VM_MARC_RELOC_HI_2_BASE_IDX … #define regMC_VM_MARC_RELOC_HI_3 … #define regMC_VM_MARC_RELOC_HI_3_BASE_IDX … #define regMC_VM_MARC_LEN_LO_0 … #define regMC_VM_MARC_LEN_LO_0_BASE_IDX … #define regMC_VM_MARC_LEN_LO_1 … #define regMC_VM_MARC_LEN_LO_1_BASE_IDX … #define regMC_VM_MARC_LEN_LO_2 … #define regMC_VM_MARC_LEN_LO_2_BASE_IDX … #define regMC_VM_MARC_LEN_LO_3 … #define regMC_VM_MARC_LEN_LO_3_BASE_IDX … #define regMC_VM_MARC_LEN_HI_0 … #define regMC_VM_MARC_LEN_HI_0_BASE_IDX … #define regMC_VM_MARC_LEN_HI_1 … #define regMC_VM_MARC_LEN_HI_1_BASE_IDX … #define regMC_VM_MARC_LEN_HI_2 … #define regMC_VM_MARC_LEN_HI_2_BASE_IDX … #define regMC_VM_MARC_LEN_HI_3 … #define regMC_VM_MARC_LEN_HI_3_BASE_IDX … #define regVM_IOMMU_CONTROL_REGISTER … #define regVM_IOMMU_CONTROL_REGISTER_BASE_IDX … #define regVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER … #define regVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX … #define regVM_PCIE_ATS_CNTL … #define regVM_PCIE_ATS_CNTL_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_0 … #define regVM_PCIE_ATS_CNTL_VF_0_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_1 … #define regVM_PCIE_ATS_CNTL_VF_1_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_2 … #define regVM_PCIE_ATS_CNTL_VF_2_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_3 … #define regVM_PCIE_ATS_CNTL_VF_3_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_4 … #define regVM_PCIE_ATS_CNTL_VF_4_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_5 … #define regVM_PCIE_ATS_CNTL_VF_5_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_6 … #define regVM_PCIE_ATS_CNTL_VF_6_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_7 … #define regVM_PCIE_ATS_CNTL_VF_7_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_8 … #define regVM_PCIE_ATS_CNTL_VF_8_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_9 … #define regVM_PCIE_ATS_CNTL_VF_9_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_10 … #define regVM_PCIE_ATS_CNTL_VF_10_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_11 … #define regVM_PCIE_ATS_CNTL_VF_11_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_12 … #define regVM_PCIE_ATS_CNTL_VF_12_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_13 … #define regVM_PCIE_ATS_CNTL_VF_13_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_14 … #define regVM_PCIE_ATS_CNTL_VF_14_BASE_IDX … #define regVM_PCIE_ATS_CNTL_VF_15 … #define regVM_PCIE_ATS_CNTL_VF_15_BASE_IDX … #define regMC_SHARED_ACTIVE_FCN_ID … #define regMC_SHARED_ACTIVE_FCN_ID_BASE_IDX … #define regMC_VM_XGMI_GPUIOV_ENABLE … #define regMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX … // addressBlock: aid_mmhub_utcl2_atcl2pfcntrdec // base address: 0x633b0 #define regATC_L2_PERFCOUNTER_LO … #define regATC_L2_PERFCOUNTER_LO_BASE_IDX … #define regATC_L2_PERFCOUNTER_HI … #define regATC_L2_PERFCOUNTER_HI_BASE_IDX … // addressBlock: aid_mmhub_utcl2_atcl2pfcntldec // base address: 0x633b8 #define regATC_L2_PERFCOUNTER0_CFG … #define regATC_L2_PERFCOUNTER0_CFG_BASE_IDX … #define regATC_L2_PERFCOUNTER1_CFG … #define regATC_L2_PERFCOUNTER1_CFG_BASE_IDX … #define regATC_L2_PERFCOUNTER_RSLT_CNTL … #define regATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: aid_mmhub_utcl2_vml2pldec // base address: 0x633d0 #define regMC_VM_L2_PERFCOUNTER0_CFG … #define regMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX … #define regMC_VM_L2_PERFCOUNTER1_CFG … #define regMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX … #define regMC_VM_L2_PERFCOUNTER2_CFG … #define regMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX … #define regMC_VM_L2_PERFCOUNTER3_CFG … #define regMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX … #define regMC_VM_L2_PERFCOUNTER4_CFG … #define regMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX … #define regMC_VM_L2_PERFCOUNTER5_CFG … #define regMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX … #define regMC_VM_L2_PERFCOUNTER6_CFG … #define regMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX … #define regMC_VM_L2_PERFCOUNTER7_CFG … #define regMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX … #define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL … #define regMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: aid_mmhub_utcl2_vml2prdec // base address: 0x63430 #define regMC_VM_L2_PERFCOUNTER_LO … #define regMC_VM_L2_PERFCOUNTER_LO_BASE_IDX … #define regMC_VM_L2_PERFCOUNTER_HI … #define regMC_VM_L2_PERFCOUNTER_HI_BASE_IDX … // addressBlock: aid_mmhub_utcl2_l2tlbdec // base address: 0x63470 #define regL2TLB_TLB0_STATUS … #define regL2TLB_TLB0_STATUS_BASE_IDX … #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO … #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX … #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI … #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX … #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO … #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX … #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI … #define regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX … // addressBlock: aid_mmhub_utcl2_l2tlbpldec // base address: 0x63490 #define regL2TLB_PERFCOUNTER0_CFG … #define regL2TLB_PERFCOUNTER0_CFG_BASE_IDX … #define regL2TLB_PERFCOUNTER1_CFG … #define regL2TLB_PERFCOUNTER1_CFG_BASE_IDX … #define regL2TLB_PERFCOUNTER2_CFG … #define regL2TLB_PERFCOUNTER2_CFG_BASE_IDX … #define regL2TLB_PERFCOUNTER3_CFG … #define regL2TLB_PERFCOUNTER3_CFG_BASE_IDX … #define regL2TLB_PERFCOUNTER_RSLT_CNTL … #define regL2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: aid_mmhub_utcl2_l2tlbprdec // base address: 0x634b0 #define regL2TLB_PERFCOUNTER_LO … #define regL2TLB_PERFCOUNTER_LO_BASE_IDX … #define regL2TLB_PERFCOUNTER_HI … #define regL2TLB_PERFCOUNTER_HI_BASE_IDX … // addressBlock: aid_mmhub_mm_cane_mmcanedec // base address: 0x635f0 #define regMM_CANE_ICG_CTRL … #define regMM_CANE_ICG_CTRL_BASE_IDX … #define regMM_CANE_ERR_STATUS … #define regMM_CANE_ERR_STATUS_BASE_IDX … #define regMM_CANE_UE_ERR_STATUS_LO … #define regMM_CANE_UE_ERR_STATUS_LO_BASE_IDX … #define regMM_CANE_UE_ERR_STATUS_HI … #define regMM_CANE_UE_ERR_STATUS_HI_BASE_IDX … #define regMM_CANE_CE_ERR_STATUS_LO … #define regMM_CANE_CE_ERR_STATUS_LO_BASE_IDX … #define regMM_CANE_CE_ERR_STATUS_HI … #define regMM_CANE_CE_ERR_STATUS_HI_BASE_IDX … #endif
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