/* * Copyright 2023 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "amdgpu.h" #include "mmhub_v3_3.h" #include "mmhub/mmhub_3_3_0_offset.h" #include "mmhub/mmhub_3_3_0_sh_mask.h" #include "navi10_enum.h" #include "soc15_common.h" #define regMMVM_L2_CNTL3_DEFAULT … #define regMMVM_L2_CNTL4_DEFAULT … #define regMMVM_L2_CNTL5_DEFAULT … #define regDAGB0_L1TLB_REG_RW_3_3 … #define regDAGB0_L1TLB_REG_RW_3_3_BASE_IDX … #define regDAGB1_L1TLB_REG_RW_3_3 … #define regDAGB1_L1TLB_REG_RW_3_3_BASE_IDX … static const char *mmhub_client_ids_v3_3[][2] = …; static uint32_t mmhub_v3_3_get_invalidate_req(unsigned int vmid, uint32_t flush_type) { … } static void mmhub_v3_3_print_l2_protection_fault_status(struct amdgpu_device *adev, uint32_t status) { … } static void mmhub_v3_3_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, uint64_t page_table_base) { … } static void mmhub_v3_3_init_gart_aperture_regs(struct amdgpu_device *adev) { … } static void mmhub_v3_3_init_system_aperture_regs(struct amdgpu_device *adev) { … } static void mmhub_v3_3_init_tlb_regs(struct amdgpu_device *adev) { … } static void mmhub_v3_3_init_cache_regs(struct amdgpu_device *adev) { … } static void mmhub_v3_3_enable_system_domain(struct amdgpu_device *adev) { … } static void mmhub_v3_3_disable_identity_aperture(struct amdgpu_device *adev) { … } static void mmhub_v3_3_setup_vmid_config(struct amdgpu_device *adev) { … } static void mmhub_v3_3_program_invalidation(struct amdgpu_device *adev) { … } static void mmhub_v3_3_init_saw_regs(struct amdgpu_device *adev) { … } static void mmhub_v3_3_enable_tls(struct amdgpu_device *adev) { … } static int mmhub_v3_3_gart_enable(struct amdgpu_device *adev) { … } static void mmhub_v3_3_gart_disable(struct amdgpu_device *adev) { … } /** * mmhub_v3_3_set_fault_enable_default - update GART/VM fault handling * * @adev: amdgpu_device pointer * @value: true redirects VM faults to the default page */ static void mmhub_v3_3_set_fault_enable_default(struct amdgpu_device *adev, bool value) { … } static const struct amdgpu_vmhub_funcs mmhub_v3_3_vmhub_funcs = …; static void mmhub_v3_3_init(struct amdgpu_device *adev) { … } static u64 mmhub_v3_3_get_fb_location(struct amdgpu_device *adev) { … } static u64 mmhub_v3_3_get_mc_fb_offset(struct amdgpu_device *adev) { … } static void mmhub_v3_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable) { … } static void mmhub_v3_3_update_medium_grain_light_sleep(struct amdgpu_device *adev, bool enable) { … } static int mmhub_v3_3_set_clockgating(struct amdgpu_device *adev, enum amd_clockgating_state state) { … } static void mmhub_v3_3_get_clockgating(struct amdgpu_device *adev, u64 *flags) { … } const struct amdgpu_mmhub_funcs mmhub_v3_3_funcs = …;
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