#include "amdgpu.h"
#include "amdgpu_ras.h"
#include "mmhub_v1_7.h"
#include "mmhub/mmhub_1_7_offset.h"
#include "mmhub/mmhub_1_7_sh_mask.h"
#include "vega10_enum.h"
#include "soc15_common.h"
#include "soc15.h"
#define regVM_L2_CNTL3_DEFAULT …
#define regVM_L2_CNTL4_DEFAULT …
static u64 mmhub_v1_7_get_fb_location(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_7_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
uint64_t page_table_base)
{ … }
static void mmhub_v1_7_init_gart_aperture_regs(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_7_init_tlb_regs(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_7_init_cache_regs(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_7_enable_system_domain(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_7_disable_identity_aperture(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_7_setup_vmid_config(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_7_program_invalidation(struct amdgpu_device *adev)
{ … }
static int mmhub_v1_7_gart_enable(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_7_gart_disable(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_7_set_fault_enable_default(struct amdgpu_device *adev, bool value)
{ … }
static void mmhub_v1_7_init(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
bool enable)
{ … }
static void mmhub_v1_7_update_medium_grain_light_sleep(struct amdgpu_device *adev,
bool enable)
{ … }
static int mmhub_v1_7_set_clockgating(struct amdgpu_device *adev,
enum amd_clockgating_state state)
{ … }
static void mmhub_v1_7_get_clockgating(struct amdgpu_device *adev, u64 *flags)
{ … }
static const struct soc15_ras_field_entry mmhub_v1_7_ras_fields[] = …;
static const struct soc15_reg_entry mmhub_v1_7_edc_cnt_regs[] = …;
static int mmhub_v1_7_get_ras_error_count(struct amdgpu_device *adev,
const struct soc15_reg_entry *reg,
uint32_t value,
uint32_t *sec_count,
uint32_t *ded_count)
{ … }
static void mmhub_v1_7_query_ras_error_count(struct amdgpu_device *adev,
void *ras_error_status)
{ … }
static void mmhub_v1_7_reset_ras_error_count(struct amdgpu_device *adev)
{ … }
static const struct soc15_reg_entry mmhub_v1_7_ea_err_status_regs[] = …;
static void mmhub_v1_7_query_ras_error_status(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_7_reset_ras_error_status(struct amdgpu_device *adev)
{ … }
struct amdgpu_ras_block_hw_ops mmhub_v1_7_ras_hw_ops = …;
struct amdgpu_mmhub_ras mmhub_v1_7_ras = …;
const struct amdgpu_mmhub_funcs mmhub_v1_7_funcs = …;