// SPDX-License-Identifier: GPL-2.0 /* * Library implementing the most common irq chip callback functions * * Copyright (C) 2011, Thomas Gleixner */ #include <linux/io.h> #include <linux/irq.h> #include <linux/slab.h> #include <linux/export.h> #include <linux/irqdomain.h> #include <linux/interrupt.h> #include <linux/kernel_stat.h> #include <linux/syscore_ops.h> #include "internals.h" static LIST_HEAD(gc_list); static DEFINE_RAW_SPINLOCK(gc_lock); /** * irq_gc_noop - NOOP function * @d: irq_data */ void irq_gc_noop(struct irq_data *d) { … } EXPORT_SYMBOL_GPL(…); /** * irq_gc_mask_disable_reg - Mask chip via disable register * @d: irq_data * * Chip has separate enable/disable registers instead of a single mask * register. */ void irq_gc_mask_disable_reg(struct irq_data *d) { … } EXPORT_SYMBOL_GPL(…); /** * irq_gc_mask_set_bit - Mask chip via setting bit in mask register * @d: irq_data * * Chip has a single mask register. Values of this register are cached * and protected by gc->lock */ void irq_gc_mask_set_bit(struct irq_data *d) { … } EXPORT_SYMBOL_GPL(…); /** * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register * @d: irq_data * * Chip has a single mask register. Values of this register are cached * and protected by gc->lock */ void irq_gc_mask_clr_bit(struct irq_data *d) { … } EXPORT_SYMBOL_GPL(…); /** * irq_gc_unmask_enable_reg - Unmask chip via enable register * @d: irq_data * * Chip has separate enable/disable registers instead of a single mask * register. */ void irq_gc_unmask_enable_reg(struct irq_data *d) { … } EXPORT_SYMBOL_GPL(…); /** * irq_gc_ack_set_bit - Ack pending interrupt via setting bit * @d: irq_data */ void irq_gc_ack_set_bit(struct irq_data *d) { … } EXPORT_SYMBOL_GPL(…); /** * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit * @d: irq_data */ void irq_gc_ack_clr_bit(struct irq_data *d) { … } /** * irq_gc_mask_disable_and_ack_set - Mask and ack pending interrupt * @d: irq_data * * This generic implementation of the irq_mask_ack method is for chips * with separate enable/disable registers instead of a single mask * register and where a pending interrupt is acknowledged by setting a * bit. * * Note: This is the only permutation currently used. Similar generic * functions should be added here if other permutations are required. */ void irq_gc_mask_disable_and_ack_set(struct irq_data *d) { … } /** * irq_gc_eoi - EOI interrupt * @d: irq_data */ void irq_gc_eoi(struct irq_data *d) { … } /** * irq_gc_set_wake - Set/clr wake bit for an interrupt * @d: irq_data * @on: Indicates whether the wake bit should be set or cleared * * For chips where the wake from suspend functionality is not * configured in a separate register and the wakeup active state is * just stored in a bitmask. */ int irq_gc_set_wake(struct irq_data *d, unsigned int on) { … } EXPORT_SYMBOL_GPL(…); static u32 irq_readl_be(void __iomem *addr) { … } static void irq_writel_be(u32 val, void __iomem *addr) { … } void irq_init_generic_chip(struct irq_chip_generic *gc, const char *name, int num_ct, unsigned int irq_base, void __iomem *reg_base, irq_flow_handler_t handler) { … } /** * irq_alloc_generic_chip - Allocate a generic chip and initialize it * @name: Name of the irq chip * @num_ct: Number of irq_chip_type instances associated with this * @irq_base: Interrupt base nr for this chip * @reg_base: Register base address (virtual) * @handler: Default flow handler associated with this chip * * Returns an initialized irq_chip_generic structure. The chip defaults * to the primary (index 0) irq_chip_type and @handler */ struct irq_chip_generic * irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base, void __iomem *reg_base, irq_flow_handler_t handler) { … } EXPORT_SYMBOL_GPL(…); static void irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags) { … } /** * irq_domain_alloc_generic_chips - Allocate generic chips for an irq domain * @d: irq domain for which to allocate chips * @info: Generic chip information * * Return: 0 on success, negative error code on failure */ int irq_domain_alloc_generic_chips(struct irq_domain *d, const struct irq_domain_chip_generic_info *info) { … } EXPORT_SYMBOL_GPL(…); /** * irq_domain_remove_generic_chips - Remove generic chips from an irq domain * @d: irq domain for which generic chips are to be removed */ void irq_domain_remove_generic_chips(struct irq_domain *d) { … } EXPORT_SYMBOL_GPL(…); /** * __irq_alloc_domain_generic_chips - Allocate generic chips for an irq domain * @d: irq domain for which to allocate chips * @irqs_per_chip: Number of interrupts each chip handles (max 32) * @num_ct: Number of irq_chip_type instances associated with this * @name: Name of the irq chip * @handler: Default flow handler associated with these chips * @clr: IRQ_* bits to clear in the mapping function * @set: IRQ_* bits to set in the mapping function * @gcflags: Generic chip specific setup flags */ int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, int num_ct, const char *name, irq_flow_handler_t handler, unsigned int clr, unsigned int set, enum irq_gc_flags gcflags) { … } EXPORT_SYMBOL_GPL(…); static struct irq_chip_generic * __irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq) { … } /** * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq * @d: irq domain pointer * @hw_irq: Hardware interrupt number */ struct irq_chip_generic * irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq) { … } EXPORT_SYMBOL_GPL(…); /* * Separate lockdep classes for interrupt chip which can nest irq_desc * lock and request mutex. */ static struct lock_class_key irq_nested_lock_class; static struct lock_class_key irq_nested_request_class; /* * irq_map_generic_chip - Map a generic chip for an irq domain */ int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, irq_hw_number_t hw_irq) { … } void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq) { … } const struct irq_domain_ops irq_generic_chip_ops = …; EXPORT_SYMBOL_GPL(…); /** * irq_setup_generic_chip - Setup a range of interrupts with a generic chip * @gc: Generic irq chip holding all data * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base * @flags: Flags for initialization * @clr: IRQ_* bits to clear * @set: IRQ_* bits to set * * Set up max. 32 interrupts starting from gc->irq_base. Note, this * initializes all interrupts to the primary irq_chip_type and its * associated handler. */ void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, enum irq_gc_flags flags, unsigned int clr, unsigned int set) { … } EXPORT_SYMBOL_GPL(…); /** * irq_setup_alt_chip - Switch to alternative chip * @d: irq_data for this interrupt * @type: Flow type to be initialized * * Only to be called from chip->irq_set_type() callbacks. */ int irq_setup_alt_chip(struct irq_data *d, unsigned int type) { … } EXPORT_SYMBOL_GPL(…); /** * irq_remove_generic_chip - Remove a chip * @gc: Generic irq chip holding all data * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base * @clr: IRQ_* bits to clear * @set: IRQ_* bits to set * * Remove up to 32 interrupts starting from gc->irq_base. */ void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, unsigned int clr, unsigned int set) { … } EXPORT_SYMBOL_GPL(…); static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc) { … } #ifdef CONFIG_PM static int irq_gc_suspend(void) { … } static void irq_gc_resume(void) { … } #else #define irq_gc_suspend … #define irq_gc_resume … #endif static void irq_gc_shutdown(void) { … } static struct syscore_ops irq_gc_syscore_ops = …; static int __init irq_gc_init_ops(void) { … } device_initcall(irq_gc_init_ops);
Codebase Browser
linux