/* * Copyright (C) 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _osssys_4_0_OFFSET_HEADER #define _osssys_4_0_OFFSET_HEADER // addressBlock: osssys_osssysdec // base address: 0x4280 #define mmIH_VMID_0_LUT … #define mmIH_VMID_0_LUT_BASE_IDX … #define mmIH_VMID_1_LUT … #define mmIH_VMID_1_LUT_BASE_IDX … #define mmIH_VMID_2_LUT … #define mmIH_VMID_2_LUT_BASE_IDX … #define mmIH_VMID_3_LUT … #define mmIH_VMID_3_LUT_BASE_IDX … #define mmIH_VMID_4_LUT … #define mmIH_VMID_4_LUT_BASE_IDX … #define mmIH_VMID_5_LUT … #define mmIH_VMID_5_LUT_BASE_IDX … #define mmIH_VMID_6_LUT … #define mmIH_VMID_6_LUT_BASE_IDX … #define mmIH_VMID_7_LUT … #define mmIH_VMID_7_LUT_BASE_IDX … #define mmIH_VMID_8_LUT … #define mmIH_VMID_8_LUT_BASE_IDX … #define mmIH_VMID_9_LUT … #define mmIH_VMID_9_LUT_BASE_IDX … #define mmIH_VMID_10_LUT … #define mmIH_VMID_10_LUT_BASE_IDX … #define mmIH_VMID_11_LUT … #define mmIH_VMID_11_LUT_BASE_IDX … #define mmIH_VMID_12_LUT … #define mmIH_VMID_12_LUT_BASE_IDX … #define mmIH_VMID_13_LUT … #define mmIH_VMID_13_LUT_BASE_IDX … #define mmIH_VMID_14_LUT … #define mmIH_VMID_14_LUT_BASE_IDX … #define mmIH_VMID_15_LUT … #define mmIH_VMID_15_LUT_BASE_IDX … #define mmIH_VMID_0_LUT_MM … #define mmIH_VMID_0_LUT_MM_BASE_IDX … #define mmIH_VMID_1_LUT_MM … #define mmIH_VMID_1_LUT_MM_BASE_IDX … #define mmIH_VMID_2_LUT_MM … #define mmIH_VMID_2_LUT_MM_BASE_IDX … #define mmIH_VMID_3_LUT_MM … #define mmIH_VMID_3_LUT_MM_BASE_IDX … #define mmIH_VMID_4_LUT_MM … #define mmIH_VMID_4_LUT_MM_BASE_IDX … #define mmIH_VMID_5_LUT_MM … #define mmIH_VMID_5_LUT_MM_BASE_IDX … #define mmIH_VMID_6_LUT_MM … #define mmIH_VMID_6_LUT_MM_BASE_IDX … #define mmIH_VMID_7_LUT_MM … #define mmIH_VMID_7_LUT_MM_BASE_IDX … #define mmIH_VMID_8_LUT_MM … #define mmIH_VMID_8_LUT_MM_BASE_IDX … #define mmIH_VMID_9_LUT_MM … #define mmIH_VMID_9_LUT_MM_BASE_IDX … #define mmIH_VMID_10_LUT_MM … #define mmIH_VMID_10_LUT_MM_BASE_IDX … #define mmIH_VMID_11_LUT_MM … #define mmIH_VMID_11_LUT_MM_BASE_IDX … #define mmIH_VMID_12_LUT_MM … #define mmIH_VMID_12_LUT_MM_BASE_IDX … #define mmIH_VMID_13_LUT_MM … #define mmIH_VMID_13_LUT_MM_BASE_IDX … #define mmIH_VMID_14_LUT_MM … #define mmIH_VMID_14_LUT_MM_BASE_IDX … #define mmIH_VMID_15_LUT_MM … #define mmIH_VMID_15_LUT_MM_BASE_IDX … #define mmIH_COOKIE_0 … #define mmIH_COOKIE_0_BASE_IDX … #define mmIH_COOKIE_1 … #define mmIH_COOKIE_1_BASE_IDX … #define mmIH_COOKIE_2 … #define mmIH_COOKIE_2_BASE_IDX … #define mmIH_COOKIE_3 … #define mmIH_COOKIE_3_BASE_IDX … #define mmIH_COOKIE_4 … #define mmIH_COOKIE_4_BASE_IDX … #define mmIH_COOKIE_5 … #define mmIH_COOKIE_5_BASE_IDX … #define mmIH_COOKIE_6 … #define mmIH_COOKIE_6_BASE_IDX … #define mmIH_COOKIE_7 … #define mmIH_COOKIE_7_BASE_IDX … #define mmIH_REGISTER_LAST_PART0 … #define mmIH_REGISTER_LAST_PART0_BASE_IDX … #define mmSEM_REQ_INPUT_0 … #define mmSEM_REQ_INPUT_0_BASE_IDX … #define mmSEM_REQ_INPUT_1 … #define mmSEM_REQ_INPUT_1_BASE_IDX … #define mmSEM_REQ_INPUT_2 … #define mmSEM_REQ_INPUT_2_BASE_IDX … #define mmSEM_REQ_INPUT_3 … #define mmSEM_REQ_INPUT_3_BASE_IDX … #define mmSEM_REGISTER_LAST_PART0 … #define mmSEM_REGISTER_LAST_PART0_BASE_IDX … #define mmIH_RB_CNTL … #define mmIH_RB_CNTL_BASE_IDX … #define mmIH_RB_BASE … #define mmIH_RB_BASE_BASE_IDX … #define mmIH_RB_BASE_HI … #define mmIH_RB_BASE_HI_BASE_IDX … #define mmIH_RB_RPTR … #define mmIH_RB_RPTR_BASE_IDX … #define mmIH_RB_WPTR … #define mmIH_RB_WPTR_BASE_IDX … #define mmIH_RB_WPTR_ADDR_HI … #define mmIH_RB_WPTR_ADDR_HI_BASE_IDX … #define mmIH_RB_WPTR_ADDR_LO … #define mmIH_RB_WPTR_ADDR_LO_BASE_IDX … #define mmIH_DOORBELL_RPTR … #define mmIH_DOORBELL_RPTR_BASE_IDX … #define mmIH_RB_CNTL_RING1 … #define mmIH_RB_CNTL_RING1_BASE_IDX … #define mmIH_RB_BASE_RING1 … #define mmIH_RB_BASE_RING1_BASE_IDX … #define mmIH_RB_BASE_HI_RING1 … #define mmIH_RB_BASE_HI_RING1_BASE_IDX … #define mmIH_RB_RPTR_RING1 … #define mmIH_RB_RPTR_RING1_BASE_IDX … #define mmIH_RB_WPTR_RING1 … #define mmIH_RB_WPTR_RING1_BASE_IDX … #define mmIH_DOORBELL_RPTR_RING1 … #define mmIH_DOORBELL_RPTR_RING1_BASE_IDX … #define mmIH_RB_CNTL_RING2 … #define mmIH_RB_CNTL_RING2_BASE_IDX … #define mmIH_RB_BASE_RING2 … #define mmIH_RB_BASE_RING2_BASE_IDX … #define mmIH_RB_BASE_HI_RING2 … #define mmIH_RB_BASE_HI_RING2_BASE_IDX … #define mmIH_RB_RPTR_RING2 … #define mmIH_RB_RPTR_RING2_BASE_IDX … #define mmIH_RB_WPTR_RING2 … #define mmIH_RB_WPTR_RING2_BASE_IDX … #define mmIH_DOORBELL_RPTR_RING2 … #define mmIH_DOORBELL_RPTR_RING2_BASE_IDX … #define mmIH_VERSION … #define mmIH_VERSION_BASE_IDX … #define mmIH_CNTL … #define mmIH_CNTL_BASE_IDX … #define mmIH_CNTL2 … #define mmIH_CNTL2_BASE_IDX … #define mmIH_STATUS … #define mmIH_STATUS_BASE_IDX … #define mmIH_PERFMON_CNTL … #define mmIH_PERFMON_CNTL_BASE_IDX … #define mmIH_PERFCOUNTER0_RESULT … #define mmIH_PERFCOUNTER0_RESULT_BASE_IDX … #define mmIH_PERFCOUNTER1_RESULT … #define mmIH_PERFCOUNTER1_RESULT_BASE_IDX … #define mmIH_DSM_MATCH_VALUE_BIT_31_0 … #define mmIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX … #define mmIH_DSM_MATCH_VALUE_BIT_63_32 … #define mmIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX … #define mmIH_DSM_MATCH_VALUE_BIT_95_64 … #define mmIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX … #define mmIH_DSM_MATCH_FIELD_CONTROL … #define mmIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX … #define mmIH_DSM_MATCH_DATA_CONTROL … #define mmIH_DSM_MATCH_DATA_CONTROL_BASE_IDX … #define mmIH_DSM_MATCH_FCN_ID … #define mmIH_DSM_MATCH_FCN_ID_BASE_IDX … #define mmIH_LIMIT_INT_RATE_CNTL … #define mmIH_LIMIT_INT_RATE_CNTL_BASE_IDX … #define mmIH_VF_RB_STATUS … #define mmIH_VF_RB_STATUS_BASE_IDX … #define mmIH_VF_RB_STATUS2 … #define mmIH_VF_RB_STATUS2_BASE_IDX … #define mmIH_VF_RB1_STATUS … #define mmIH_VF_RB1_STATUS_BASE_IDX … #define mmIH_VF_RB1_STATUS2 … #define mmIH_VF_RB1_STATUS2_BASE_IDX … #define mmIH_VF_RB2_STATUS … #define mmIH_VF_RB2_STATUS_BASE_IDX … #define mmIH_VF_RB2_STATUS2 … #define mmIH_VF_RB2_STATUS2_BASE_IDX … #define mmIH_INT_FLOOD_CNTL … #define mmIH_INT_FLOOD_CNTL_BASE_IDX … #define mmIH_RB0_INT_FLOOD_STATUS … #define mmIH_RB0_INT_FLOOD_STATUS_BASE_IDX … #define mmIH_RB1_INT_FLOOD_STATUS … #define mmIH_RB1_INT_FLOOD_STATUS_BASE_IDX … #define mmIH_RB2_INT_FLOOD_STATUS … #define mmIH_RB2_INT_FLOOD_STATUS_BASE_IDX … #define mmIH_INT_FLOOD_STATUS … #define mmIH_INT_FLOOD_STATUS_BASE_IDX … #define mmIH_STORM_CLIENT_LIST_CNTL … #define mmIH_STORM_CLIENT_LIST_CNTL_BASE_IDX … #define mmIH_CLK_CTRL … #define mmIH_CLK_CTRL_BASE_IDX … #define mmIH_INT_FLAGS … #define mmIH_INT_FLAGS_BASE_IDX … #define mmIH_LAST_INT_INFO0 … #define mmIH_LAST_INT_INFO0_BASE_IDX … #define mmIH_LAST_INT_INFO1 … #define mmIH_LAST_INT_INFO1_BASE_IDX … #define mmIH_LAST_INT_INFO2 … #define mmIH_LAST_INT_INFO2_BASE_IDX … #define mmIH_SCRATCH … #define mmIH_SCRATCH_BASE_IDX … #define mmIH_CLIENT_CREDIT_ERROR … #define mmIH_CLIENT_CREDIT_ERROR_BASE_IDX … #define mmIH_GPU_IOV_VIOLATION_LOG … #define mmIH_GPU_IOV_VIOLATION_LOG_BASE_IDX … #define mmIH_COOKIE_REC_VIOLATION_LOG … #define mmIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX … #define mmIH_CREDIT_STATUS … #define mmIH_CREDIT_STATUS_BASE_IDX … #define mmIH_MMHUB_ERROR … #define mmIH_MMHUB_ERROR_BASE_IDX … #define mmIH_REGISTER_LAST_PART2 … #define mmIH_REGISTER_LAST_PART2_BASE_IDX … #define mmSEM_CLK_CTRL … #define mmSEM_CLK_CTRL_BASE_IDX … #define mmSEM_UTC_CREDIT … #define mmSEM_UTC_CREDIT_BASE_IDX … #define mmSEM_UTC_CONFIG … #define mmSEM_UTC_CONFIG_BASE_IDX … #define mmSEM_UTCL2_TRAN_EN_LUT … #define mmSEM_UTCL2_TRAN_EN_LUT_BASE_IDX … #define mmSEM_MCIF_CONFIG … #define mmSEM_MCIF_CONFIG_BASE_IDX … #define mmSEM_PERFMON_CNTL … #define mmSEM_PERFMON_CNTL_BASE_IDX … #define mmSEM_PERFCOUNTER0_RESULT … #define mmSEM_PERFCOUNTER0_RESULT_BASE_IDX … #define mmSEM_PERFCOUNTER1_RESULT … #define mmSEM_PERFCOUNTER1_RESULT_BASE_IDX … #define mmSEM_STATUS … #define mmSEM_STATUS_BASE_IDX … #define mmSEM_MAILBOX_CLIENTCONFIG … #define mmSEM_MAILBOX_CLIENTCONFIG_BASE_IDX … #define mmSEM_MAILBOX … #define mmSEM_MAILBOX_BASE_IDX … #define mmSEM_MAILBOX_CONTROL … #define mmSEM_MAILBOX_CONTROL_BASE_IDX … #define mmSEM_CHICKEN_BITS … #define mmSEM_CHICKEN_BITS_BASE_IDX … #define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA … #define mmSEM_MAILBOX_CLIENTCONFIG_EXTRA_BASE_IDX … #define mmSEM_GPU_IOV_VIOLATION_LOG … #define mmSEM_GPU_IOV_VIOLATION_LOG_BASE_IDX … #define mmSEM_OUTSTANDING_THRESHOLD … #define mmSEM_OUTSTANDING_THRESHOLD_BASE_IDX … #define mmSEM_REGISTER_LAST_PART2 … #define mmSEM_REGISTER_LAST_PART2_BASE_IDX … #define mmIH_ACTIVE_FCN_ID … #define mmIH_ACTIVE_FCN_ID_BASE_IDX … #define mmIH_VIRT_RESET_REQ … #define mmIH_VIRT_RESET_REQ_BASE_IDX … #define mmIH_CLIENT_CFG … #define mmIH_CLIENT_CFG_BASE_IDX … #define mmIH_CLIENT_CFG_INDEX … #define mmIH_CLIENT_CFG_INDEX_BASE_IDX … #define mmIH_CLIENT_CFG_DATA … #define mmIH_CLIENT_CFG_DATA_BASE_IDX … #define mmIH_CID_REMAP_INDEX … #define mmIH_CID_REMAP_INDEX_BASE_IDX … #define mmIH_CID_REMAP_DATA … #define mmIH_CID_REMAP_DATA_BASE_IDX … #define mmIH_CHICKEN … #define mmIH_CHICKEN_BASE_IDX … #define mmIH_MMHUB_CNTL … #define mmIH_MMHUB_CNTL_BASE_IDX … #define mmIH_REGISTER_LAST_PART1 … #define mmIH_REGISTER_LAST_PART1_BASE_IDX … #define mmSEM_ACTIVE_FCN_ID … #define mmSEM_ACTIVE_FCN_ID_BASE_IDX … #define mmSEM_VIRT_RESET_REQ … #define mmSEM_VIRT_RESET_REQ_BASE_IDX … #define mmSEM_RESP_SDMA0 … #define mmSEM_RESP_SDMA0_BASE_IDX … #define mmSEM_RESP_SDMA1 … #define mmSEM_RESP_SDMA1_BASE_IDX … #define mmSEM_RESP_UVD … #define mmSEM_RESP_UVD_BASE_IDX … #define mmSEM_RESP_VCE_0 … #define mmSEM_RESP_VCE_0_BASE_IDX … #define mmSEM_RESP_ACP … #define mmSEM_RESP_ACP_BASE_IDX … #define mmSEM_RESP_ISP … #define mmSEM_RESP_ISP_BASE_IDX … #define mmSEM_RESP_VCE_1 … #define mmSEM_RESP_VCE_1_BASE_IDX … #define mmSEM_RESP_VP8 … #define mmSEM_RESP_VP8_BASE_IDX … #define mmSEM_RESP_GC … #define mmSEM_RESP_GC_BASE_IDX … #define mmSEM_CID_REMAP_INDEX … #define mmSEM_CID_REMAP_INDEX_BASE_IDX … #define mmSEM_CID_REMAP_DATA … #define mmSEM_CID_REMAP_DATA_BASE_IDX … #define mmSEM_ATOMIC_OP_LUT … #define mmSEM_ATOMIC_OP_LUT_BASE_IDX … #define mmSEM_EDC_CONFIG … #define mmSEM_EDC_CONFIG_BASE_IDX … #define mmSEM_CHICKEN_BITS2 … #define mmSEM_CHICKEN_BITS2_BASE_IDX … #define mmSEM_MMHUB_CNTL … #define mmSEM_MMHUB_CNTL_BASE_IDX … #define mmSEM_REGISTER_LAST_PART1 … #define mmSEM_REGISTER_LAST_PART1_BASE_IDX … #endif
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