/* * Copyright 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef SOC15_H #define SOC15_H #define GFX9_NUM_GFX_RINGS … #define GFX9_NUM_COMPUTE_RINGS … /* * PM4 */ #define PACKET_TYPE0 … #define PACKET_TYPE1 … #define PACKET_TYPE2 … #define PACKET_TYPE3 … #define CP_PACKET_GET_TYPE(h) … #define CP_PACKET_GET_COUNT(h) … #define CP_PACKET0_GET_REG(h) … #define CP_PACKET3_GET_OPCODE(h) … #define PACKET0(reg, n) … #define CP_PACKET2 … #define PACKET2_PAD_SHIFT … #define PACKET2_PAD_MASK … #define PACKET2(v) … #define PACKET3(op, n) … #define PACKET3_COMPUTE(op, n) … #define PACKETJ_CONDITION_CHECK0 … #define PACKETJ_CONDITION_CHECK1 … #define PACKETJ_CONDITION_CHECK2 … #define PACKETJ_CONDITION_CHECK3 … #define PACKETJ_CONDITION_CHECK4 … #define PACKETJ_CONDITION_CHECK5 … #define PACKETJ_CONDITION_CHECK6 … #define PACKETJ_CONDITION_CHECK7 … #define PACKETJ_TYPE0 … #define PACKETJ_TYPE1 … #define PACKETJ_TYPE2 … #define PACKETJ_TYPE3 … #define PACKETJ_TYPE4 … #define PACKETJ_TYPE5 … #define PACKETJ_TYPE6 … #define PACKETJ_TYPE7 … #define PACKETJ(reg, r, cond, type) … /* Packet 3 types */ #define PACKET3_NOP … #define PACKET3_SET_BASE … #define PACKET3_BASE_INDEX(x) … #define CE_PARTITION_BASE … #define PACKET3_CLEAR_STATE … #define PACKET3_INDEX_BUFFER_SIZE … #define PACKET3_DISPATCH_DIRECT … #define PACKET3_DISPATCH_INDIRECT … #define PACKET3_ATOMIC_GDS … #define PACKET3_ATOMIC_MEM … #define PACKET3_OCCLUSION_QUERY … #define PACKET3_SET_PREDICATION … #define PACKET3_REG_RMW … #define PACKET3_COND_EXEC … #define PACKET3_PRED_EXEC … #define PACKET3_DRAW_INDIRECT … #define PACKET3_DRAW_INDEX_INDIRECT … #define PACKET3_INDEX_BASE … #define PACKET3_DRAW_INDEX_2 … #define PACKET3_CONTEXT_CONTROL … #define PACKET3_INDEX_TYPE … #define PACKET3_DRAW_INDIRECT_MULTI … #define PACKET3_DRAW_INDEX_AUTO … #define PACKET3_NUM_INSTANCES … #define PACKET3_DRAW_INDEX_MULTI_AUTO … #define PACKET3_INDIRECT_BUFFER_CONST … #define PACKET3_STRMOUT_BUFFER_UPDATE … #define PACKET3_DRAW_INDEX_OFFSET_2 … #define PACKET3_DRAW_PREAMBLE … #define PACKET3_WRITE_DATA … #define WRITE_DATA_DST_SEL(x) … /* 0 - register * 1 - memory (sync - via GRBM) * 2 - gl2 * 3 - gds * 4 - reserved * 5 - memory (async - direct) */ #define WR_ONE_ADDR … #define WR_CONFIRM … #define WRITE_DATA_CACHE_POLICY(x) … /* 0 - LRU * 1 - Stream */ #define WRITE_DATA_ENGINE_SEL(x) … /* 0 - me * 1 - pfp * 2 - ce */ #define PACKET3_DRAW_INDEX_INDIRECT_MULTI … #define PACKET3_MEM_SEMAPHORE … #define PACKET3_SEM_USE_MAILBOX … #define PACKET3_SEM_SEL_SIGNAL_TYPE … #define PACKET3_SEM_SEL_SIGNAL … #define PACKET3_SEM_SEL_WAIT … #define PACKET3_WAIT_REG_MEM … #define WAIT_REG_MEM_FUNCTION(x) … /* 0 - always * 1 - < * 2 - <= * 3 - == * 4 - != * 5 - >= * 6 - > */ #define WAIT_REG_MEM_MEM_SPACE(x) … /* 0 - reg * 1 - mem */ #define WAIT_REG_MEM_OPERATION(x) … /* 0 - wait_reg_mem * 1 - wr_wait_wr_reg */ #define WAIT_REG_MEM_ENGINE(x) … /* 0 - me * 1 - pfp */ #define PACKET3_INDIRECT_BUFFER … #define INDIRECT_BUFFER_VALID … #define INDIRECT_BUFFER_CACHE_POLICY(x) … /* 0 - LRU * 1 - Stream * 2 - Bypass */ #define INDIRECT_BUFFER_PRE_ENB(x) … #define INDIRECT_BUFFER_PRE_RESUME(x) … #define PACKET3_COPY_DATA … #define PACKET3_PFP_SYNC_ME … #define PACKET3_COND_WRITE … #define PACKET3_EVENT_WRITE … #define EVENT_TYPE(x) … #define EVENT_INDEX(x) … /* 0 - any non-TS event * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* * 2 - SAMPLE_PIPELINESTAT * 3 - SAMPLE_STREAMOUTSTAT* * 4 - *S_PARTIAL_FLUSH */ #define PACKET3_RELEASE_MEM … #define EVENT_TYPE(x) … #define EVENT_INDEX(x) … #define EOP_TCL1_VOL_ACTION_EN … #define EOP_TC_VOL_ACTION_EN … #define EOP_TC_WB_ACTION_EN … #define EOP_TCL1_ACTION_EN … #define EOP_TC_ACTION_EN … #define EOP_TC_NC_ACTION_EN … #define EOP_TC_MD_ACTION_EN … #define EOP_EXEC … #define DATA_SEL(x) … /* 0 - discard * 1 - send low 32bit data * 2 - send 64bit data * 3 - send 64bit GPU counter value * 4 - send 64bit sys counter value */ #define INT_SEL(x) … /* 0 - none * 1 - interrupt only (DATA_SEL = 0) * 2 - interrupt when data write is confirmed */ #define DST_SEL(x) … /* 0 - MC * 1 - TC/L2 */ #define PACKET3_PREAMBLE_CNTL … #define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE … #define PACKET3_PREAMBLE_END_CLEAR_STATE … #define PACKET3_DMA_DATA … /* 1. header * 2. CONTROL * 3. SRC_ADDR_LO or DATA [31:0] * 4. SRC_ADDR_HI [31:0] * 5. DST_ADDR_LO [31:0] * 6. DST_ADDR_HI [7:0] * 7. COMMAND [30:21] | BYTE_COUNT [20:0] */ /* CONTROL */ #define PACKET3_DMA_DATA_ENGINE(x) … /* 0 - ME * 1 - PFP */ #define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) … /* 0 - LRU * 1 - Stream */ #define PACKET3_DMA_DATA_DST_SEL(x) … /* 0 - DST_ADDR using DAS * 1 - GDS * 3 - DST_ADDR using L2 */ #define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) … /* 0 - LRU * 1 - Stream */ #define PACKET3_DMA_DATA_SRC_SEL(x) … /* 0 - SRC_ADDR using SAS * 1 - GDS * 2 - DATA * 3 - SRC_ADDR using L2 */ #define PACKET3_DMA_DATA_CP_SYNC … /* COMMAND */ #define PACKET3_DMA_DATA_CMD_SAS … /* 0 - memory * 1 - register */ #define PACKET3_DMA_DATA_CMD_DAS … /* 0 - memory * 1 - register */ #define PACKET3_DMA_DATA_CMD_SAIC … #define PACKET3_DMA_DATA_CMD_DAIC … #define PACKET3_DMA_DATA_CMD_RAW_WAIT … #define PACKET3_ACQUIRE_MEM … /* 1. HEADER * 2. COHER_CNTL [30:0] * 2.1 ENGINE_SEL [31:31] * 3. COHER_SIZE [31:0] * 4. COHER_SIZE_HI [7:0] * 5. COHER_BASE_LO [31:0] * 6. COHER_BASE_HI [23:0] * 7. POLL_INTERVAL [15:0] */ /* COHER_CNTL fields for CP_COHER_CNTL */ #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA(x) … #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WC_ACTION_ENA(x) … #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_INV_METADATA_ACTION_ENA(x) … #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_VOL_ACTION_ENA(x) … #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(x) … #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(x) … #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(x) … #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_CB_ACTION_ENA(x) … #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_DB_ACTION_ENA(x) … #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(x) … #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_VOL_ACTION_ENA(x) … #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(x) … #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_WB_ACTION_ENA(x) … #define PACKET3_REWIND … #define PACKET3_LOAD_UCONFIG_REG … #define PACKET3_LOAD_SH_REG … #define PACKET3_LOAD_CONFIG_REG … #define PACKET3_LOAD_CONTEXT_REG … #define PACKET3_SET_CONFIG_REG … #define PACKET3_SET_CONFIG_REG_START … #define PACKET3_SET_CONFIG_REG_END … #define PACKET3_SET_CONTEXT_REG … #define PACKET3_SET_CONTEXT_REG_START … #define PACKET3_SET_CONTEXT_REG_END … #define PACKET3_SET_CONTEXT_REG_INDIRECT … #define PACKET3_SET_SH_REG … #define PACKET3_SET_SH_REG_START … #define PACKET3_SET_SH_REG_END … #define PACKET3_SET_SH_REG_OFFSET … #define PACKET3_SET_QUEUE_REG … #define PACKET3_SET_UCONFIG_REG … #define PACKET3_SET_UCONFIG_REG_START … #define PACKET3_SET_UCONFIG_REG_END … #define PACKET3_SET_UCONFIG_REG_INDEX_TYPE … #define PACKET3_SCRATCH_RAM_WRITE … #define PACKET3_SCRATCH_RAM_READ … #define PACKET3_LOAD_CONST_RAM … #define PACKET3_WRITE_CONST_RAM … #define PACKET3_DUMP_CONST_RAM … #define PACKET3_INCREMENT_CE_COUNTER … #define PACKET3_INCREMENT_DE_COUNTER … #define PACKET3_WAIT_ON_CE_COUNTER … #define PACKET3_WAIT_ON_DE_COUNTER_DIFF … #define PACKET3_SWITCH_BUFFER … #define PACKET3_FRAME_CONTROL … #define FRAME_TMZ … #define FRAME_CMD(x) … /* * x=0: tmz_begin * x=1: tmz_end */ #define PACKET3_INVALIDATE_TLBS … #define PACKET3_INVALIDATE_TLBS_DST_SEL(x) … #define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) … #define PACKET3_INVALIDATE_TLBS_PASID(x) … #define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x) … #define PACKET3_SET_RESOURCES … /* 1. header * 2. CONTROL * 3. QUEUE_MASK_LO [31:0] * 4. QUEUE_MASK_HI [31:0] * 5. GWS_MASK_LO [31:0] * 6. GWS_MASK_HI [31:0] * 7. OAC_MASK [15:0] * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] */ #define PACKET3_SET_RESOURCES_VMID_MASK(x) … #define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) … #define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) … #define PACKET3_MAP_QUEUES … /* 1. header * 2. CONTROL * 3. CONTROL2 * 4. MQD_ADDR_LO [31:0] * 5. MQD_ADDR_HI [31:0] * 6. WPTR_ADDR_LO [31:0] * 7. WPTR_ADDR_HI [31:0] */ /* CONTROL */ #define PACKET3_MAP_QUEUES_QUEUE_SEL(x) … #define PACKET3_MAP_QUEUES_VMID(x) … #define PACKET3_MAP_QUEUES_QUEUE(x) … #define PACKET3_MAP_QUEUES_PIPE(x) … #define PACKET3_MAP_QUEUES_ME(x) … #define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) … #define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) … #define PACKET3_MAP_QUEUES_ENGINE_SEL(x) … #define PACKET3_MAP_QUEUES_NUM_QUEUES(x) … /* CONTROL2 */ #define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) … #define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) … #define PACKET3_UNMAP_QUEUES … /* 1. header * 2. CONTROL * 3. CONTROL2 * 4. CONTROL3 * 5. CONTROL4 * 6. CONTROL5 */ /* CONTROL */ #define PACKET3_UNMAP_QUEUES_ACTION(x) … /* 0 - PREEMPT_QUEUES * 1 - RESET_QUEUES * 2 - DISABLE_PROCESS_QUEUES * 3 - PREEMPT_QUEUES_NO_UNMAP */ #define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) … #define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) … #define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) … /* CONTROL2a */ #define PACKET3_UNMAP_QUEUES_PASID(x) … /* CONTROL2b */ #define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) … /* CONTROL3a */ #define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) … /* CONTROL3b */ #define PACKET3_UNMAP_QUEUES_RB_WPTR(x) … /* CONTROL4 */ #define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) … /* CONTROL5 */ #define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) … #define PACKET3_QUERY_STATUS … /* 1. header * 2. CONTROL * 3. CONTROL2 * 4. ADDR_LO [31:0] * 5. ADDR_HI [31:0] * 6. DATA_LO [31:0] * 7. DATA_HI [31:0] */ /* CONTROL */ #define PACKET3_QUERY_STATUS_CONTEXT_ID(x) … #define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) … #define PACKET3_QUERY_STATUS_COMMAND(x) … /* CONTROL2a */ #define PACKET3_QUERY_STATUS_PASID(x) … /* CONTROL2b */ #define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) … #define PACKET3_QUERY_STATUS_ENG_SEL(x) … #define VCE_CMD_NO_OP … #define VCE_CMD_END … #define VCE_CMD_IB … #define VCE_CMD_FENCE … #define VCE_CMD_TRAP … #define VCE_CMD_IB_AUTO … #define VCE_CMD_SEMAPHORE … #define VCE_CMD_IB_VM … #define VCE_CMD_WAIT_GE … #define VCE_CMD_UPDATE_PTB … #define VCE_CMD_FLUSH_TLB … #define VCE_CMD_REG_WRITE … #define VCE_CMD_REG_WAIT … #define HEVC_ENC_CMD_NO_OP … #define HEVC_ENC_CMD_END … #define HEVC_ENC_CMD_FENCE … #define HEVC_ENC_CMD_TRAP … #define HEVC_ENC_CMD_IB_VM … #define HEVC_ENC_CMD_REG_WRITE … #define HEVC_ENC_CMD_REG_WAIT … #endif
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