linux/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include <linux/firmware.h>
#include <linux/pci.h>

#include <drm/drm_cache.h>

#include "amdgpu.h"
#include "gmc_v9_0.h"
#include "amdgpu_atomfirmware.h"
#include "amdgpu_gem.h"

#include "gc/gc_9_0_sh_mask.h"
#include "dce/dce_12_0_offset.h"
#include "dce/dce_12_0_sh_mask.h"
#include "vega10_enum.h"
#include "mmhub/mmhub_1_0_offset.h"
#include "athub/athub_1_0_sh_mask.h"
#include "athub/athub_1_0_offset.h"
#include "oss/osssys_4_0_offset.h"

#include "soc15.h"
#include "soc15d.h"
#include "soc15_common.h"
#include "umc/umc_6_0_sh_mask.h"

#include "gfxhub_v1_0.h"
#include "mmhub_v1_0.h"
#include "athub_v1_0.h"
#include "gfxhub_v1_1.h"
#include "gfxhub_v1_2.h"
#include "mmhub_v9_4.h"
#include "mmhub_v1_7.h"
#include "mmhub_v1_8.h"
#include "umc_v6_1.h"
#include "umc_v6_0.h"
#include "umc_v6_7.h"
#include "umc_v12_0.h"
#include "hdp_v4_0.h"
#include "mca_v3_0.h"

#include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"

#include "amdgpu_ras.h"
#include "amdgpu_xgmi.h"

/* add these here since we already include dce12 headers and these are for DCN */
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX
#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT
#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT
#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK
#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK
#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0
#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX

#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX

#define MAX_MEM_RANGES

static const char * const gfxhub_client_ids[] =;

static const char *mmhub_client_ids_raven[][2] =;

static const char *mmhub_client_ids_renoir[][2] =;

static const char *mmhub_client_ids_vega10[][2] =;

static const char *mmhub_client_ids_vega12[][2] =;

static const char *mmhub_client_ids_vega20[][2] =;

static const char *mmhub_client_ids_arcturus[][2] =;

static const char *mmhub_client_ids_aldebaran[][2] =;

static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =;

static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =;

static const uint32_t ecc_umc_mcumc_ctrl_addrs[] =;

static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] =;

static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
		struct amdgpu_irq_src *src,
		unsigned int type,
		enum amdgpu_interrupt_state state)
{}

static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
					struct amdgpu_irq_src *src,
					unsigned int type,
					enum amdgpu_interrupt_state state)
{}

static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
				      struct amdgpu_irq_src *source,
				      struct amdgpu_iv_entry *entry)
{}

static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs =;


static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs =;

static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
{}

static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
					uint32_t flush_type)
{}

/**
 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
 *
 * @adev: amdgpu_device pointer
 * @vmhub: vmhub type
 *
 */
static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
				       uint32_t vmhub)
{}

static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
					uint8_t vmid, uint16_t *p_pasid)
{}

/*
 * GART
 * VMID 0 is the physical GPU addresses as used by the kernel.
 * VMIDs 1-15 are used for userspace clients and are handled
 * by the amdgpu vm/hsa code.
 */

/**
 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
 *
 * @adev: amdgpu_device pointer
 * @vmid: vm instance to flush
 * @vmhub: which hub to flush
 * @flush_type: the flush type
 *
 * Flush the TLB for the requested page table using certain type.
 */
static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
					uint32_t vmhub, uint32_t flush_type)
{}

/**
 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
 *
 * @adev: amdgpu_device pointer
 * @pasid: pasid to be flush
 * @flush_type: the flush type
 * @all_hub: flush all hubs
 * @inst: is used to select which instance of KIQ to use for the invalidation
 *
 * Flush the TLB for the requested pasid.
 */
static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
					 uint16_t pasid, uint32_t flush_type,
					 bool all_hub, uint32_t inst)
{}

static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
					    unsigned int vmid, uint64_t pd_addr)
{}

static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
					unsigned int pasid)
{}

/*
 * PTE format on VEGA 10:
 * 63:59 reserved
 * 58:57 mtype
 * 56 F
 * 55 L
 * 54 P
 * 53 SW
 * 52 T
 * 50:48 reserved
 * 47:12 4k physical page base address
 * 11:7 fragment
 * 6 write
 * 5 read
 * 4 exe
 * 3 Z
 * 2 snooped
 * 1 system
 * 0 valid
 *
 * PDE format on VEGA 10:
 * 63:59 block fragment size
 * 58:55 reserved
 * 54 P
 * 53:48 reserved
 * 47:6 physical base address of PD or PTE
 * 5:3 reserved
 * 2 C
 * 1 system
 * 0 valid
 */

static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)

{}

static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
				uint64_t *addr, uint64_t *flags)
{}

static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev,
					 struct amdgpu_bo *bo,
					 struct amdgpu_bo_va_mapping *mapping,
					 uint64_t *flags)
{}

static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
				struct amdgpu_bo_va_mapping *mapping,
				uint64_t *flags)
{}

static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev,
					   struct amdgpu_vm *vm,
					   uint64_t addr, uint64_t *flags)
{}

static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
{}

static enum amdgpu_memory_partition
gmc_v9_0_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes)
{}

static enum amdgpu_memory_partition
gmc_v9_0_query_memory_partition(struct amdgpu_device *adev)
{}

static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs =;

static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
{}

static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
{}

static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
{}

static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev)
{}

static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev)
{}

static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev)
{}

static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev)
{}

static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev)
{}

static int gmc_v9_0_early_init(void *handle)
{}

static int gmc_v9_0_late_init(void *handle)
{}

static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
					struct amdgpu_gmc *mc)
{}

/**
 * gmc_v9_0_mc_init - initialize the memory controller driver params
 *
 * @adev: amdgpu_device pointer
 *
 * Look up the amount of vram, vram width, and decide how to place
 * vram and gart within the GPU's physical address space.
 * Returns 0 for success.
 */
static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
{}

static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
{}

/**
 * gmc_v9_0_save_registers - saves regs
 *
 * @adev: amdgpu_device pointer
 *
 * This saves potential register values that should be
 * restored upon resume
 */
static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
{}

static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev)
{}

static bool gmc_v9_0_is_node_present(int *node_ids, int num_ids, int nid)
{}

static void
gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device *adev,
			      struct amdgpu_mem_partition_info *mem_ranges)
{}

static void
gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev,
			    struct amdgpu_mem_partition_info *mem_ranges)
{}

static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev)
{}

static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev)
{}

static int gmc_v9_0_sw_init(void *handle)
{}

static int gmc_v9_0_sw_fini(void *handle)
{}

static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
{}

/**
 * gmc_v9_0_restore_registers - restores regs
 *
 * @adev: amdgpu_device pointer
 *
 * This restores register values, saved at suspend.
 */
void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
{}

/**
 * gmc_v9_0_gart_enable - gart enable
 *
 * @adev: amdgpu_device pointer
 */
static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
{}

static int gmc_v9_0_hw_init(void *handle)
{}

/**
 * gmc_v9_0_gart_disable - gart disable
 *
 * @adev: amdgpu_device pointer
 *
 * This disables all VM page table.
 */
static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
{}

static int gmc_v9_0_hw_fini(void *handle)
{}

static int gmc_v9_0_suspend(void *handle)
{}

static int gmc_v9_0_resume(void *handle)
{}

static bool gmc_v9_0_is_idle(void *handle)
{}

static int gmc_v9_0_wait_for_idle(void *handle)
{}

static int gmc_v9_0_soft_reset(void *handle)
{}

static int gmc_v9_0_set_clockgating_state(void *handle,
					enum amd_clockgating_state state)
{}

static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags)
{}

static int gmc_v9_0_set_powergating_state(void *handle,
					enum amd_powergating_state state)
{}

const struct amd_ip_funcs gmc_v9_0_ip_funcs =;

const struct amdgpu_ip_block_version gmc_v9_0_ip_block =;