/* * Copyright (C) 2020 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _umc_8_7_0_SH_MASK_HEADER #define _umc_8_7_0_SH_MASK_HEADER //UMCCH0_0_GeccErrCntSel #define UMCCH0_0_GeccErrCntSel__GeccErrCntCsSel__SHIFT … #define UMCCH0_0_GeccErrCntSel__GeccErrInt__SHIFT … #define UMCCH0_0_GeccErrCntSel__GeccErrCntEn__SHIFT … #define UMCCH0_0_GeccErrCntSel__PoisonCntEn__SHIFT … #define UMCCH0_0_GeccErrCntSel__GeccErrCntCsSel_MASK … #define UMCCH0_0_GeccErrCntSel__GeccErrInt_MASK … #define UMCCH0_0_GeccErrCntSel__GeccErrCntEn_MASK … #define UMCCH0_0_GeccErrCntSel__PoisonCntEn_MASK … //UMCCH0_0_GeccErrCnt #define UMCCH0_0_GeccErrCnt__GeccErrCnt__SHIFT … #define UMCCH0_0_GeccErrCnt__GeccUnCorrErrCnt__SHIFT … #define UMCCH0_0_GeccErrCnt__GeccErrCnt_MASK … #define UMCCH0_0_GeccErrCnt__GeccUnCorrErrCnt_MASK … //MCA_UMC_UMC0_MCUMC_STATUST0 #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV22__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__AddrLsb__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV30__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV38__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV41__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__Poison__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__UECC__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__CECC__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV47__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV54__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__TCC__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__PCC__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__En__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__UC__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__Val__SHIFT … #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV22_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__AddrLsb_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV30_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV38_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV41_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__Poison_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__UECC_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__CECC_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV47_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV54_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__TCC_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__PCC_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__En_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__UC_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow_MASK … #define MCA_UMC_UMC0_MCUMC_STATUST0__Val_MASK … //MCA_UMC_UMC0_MCUMC_ADDRT0 #define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr__SHIFT … #define MCA_UMC_UMC0_MCUMC_ADDRT0__LSB__SHIFT … #define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved__SHIFT … #define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr_MASK … #define MCA_UMC_UMC0_MCUMC_ADDRT0__LSB_MASK … #define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved_MASK … #endif
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