/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Meson-AXG clock tree IDs
*
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
*/
#ifndef __AXG_CLKC_H
#define __AXG_CLKC_H
#define CLKID_SYS_PLL 0
#define CLKID_FIXED_PLL 1
#define CLKID_FCLK_DIV2 2
#define CLKID_FCLK_DIV3 3
#define CLKID_FCLK_DIV4 4
#define CLKID_FCLK_DIV5 5
#define CLKID_FCLK_DIV7 6
#define CLKID_GP0_PLL 7
#define CLKID_MPEG_SEL 8
#define CLKID_MPEG_DIV 9
#define CLKID_CLK81 10
#define CLKID_MPLL0 11
#define CLKID_MPLL1 12
#define CLKID_MPLL2 13
#define CLKID_MPLL3 14
#define CLKID_DDR 15
#define CLKID_AUDIO_LOCKER 16
#define CLKID_MIPI_DSI_HOST 17
#define CLKID_ISA 18
#define CLKID_PL301 19
#define CLKID_PERIPHS 20
#define CLKID_SPICC0 21
#define CLKID_I2C 22
#define CLKID_RNG0 23
#define CLKID_UART0 24
#define CLKID_MIPI_DSI_PHY 25
#define CLKID_SPICC1 26
#define CLKID_PCIE_A 27
#define CLKID_PCIE_B 28
#define CLKID_HIU_IFACE 29
#define CLKID_ASSIST_MISC 30
#define CLKID_SD_EMMC_B 31
#define CLKID_SD_EMMC_C 32
#define CLKID_DMA 33
#define CLKID_SPI 34
#define CLKID_AUDIO 35
#define CLKID_ETH 36
#define CLKID_UART1 37
#define CLKID_G2D 38
#define CLKID_USB0 39
#define CLKID_USB1 40
#define CLKID_RESET 41
#define CLKID_USB 42
#define CLKID_AHB_ARB0 43
#define CLKID_EFUSE 44
#define CLKID_BOOT_ROM 45
#define CLKID_AHB_DATA_BUS 46
#define CLKID_AHB_CTRL_BUS 47
#define CLKID_USB1_DDR_BRIDGE 48
#define CLKID_USB0_DDR_BRIDGE 49
#define CLKID_MMC_PCLK 50
#define CLKID_VPU_INTR 51
#define CLKID_SEC_AHB_AHB3_BRIDGE 52
#define CLKID_GIC 53
#define CLKID_AO_MEDIA_CPU 54
#define CLKID_AO_AHB_SRAM 55
#define CLKID_AO_AHB_BUS 56
#define CLKID_AO_IFACE 57
#define CLKID_AO_I2C 58
#define CLKID_SD_EMMC_B_CLK0 59
#define CLKID_SD_EMMC_C_CLK0 60
#define CLKID_SD_EMMC_B_CLK0_SEL 61
#define CLKID_SD_EMMC_B_CLK0_DIV 62
#define CLKID_SD_EMMC_C_CLK0_SEL 63
#define CLKID_SD_EMMC_C_CLK0_DIV 64
#define CLKID_MPLL0_DIV 65
#define CLKID_MPLL1_DIV 66
#define CLKID_MPLL2_DIV 67
#define CLKID_MPLL3_DIV 68
#define CLKID_HIFI_PLL 69
#define CLKID_MPLL_PREDIV 70
#define CLKID_FCLK_DIV2_DIV 71
#define CLKID_FCLK_DIV3_DIV 72
#define CLKID_FCLK_DIV4_DIV 73
#define CLKID_FCLK_DIV5_DIV 74
#define CLKID_FCLK_DIV7_DIV 75
#define CLKID_PCIE_PLL 76
#define CLKID_PCIE_MUX 77
#define CLKID_PCIE_REF 78
#define CLKID_PCIE_CML_EN0 79
#define CLKID_PCIE_CML_EN1 80
#define CLKID_GEN_CLK_SEL 82
#define CLKID_GEN_CLK_DIV 83
#define CLKID_GEN_CLK 84
#define CLKID_SYS_PLL_DCO 85
#define CLKID_FIXED_PLL_DCO 86
#define CLKID_GP0_PLL_DCO 87
#define CLKID_HIFI_PLL_DCO 88
#define CLKID_PCIE_PLL_DCO 89
#define CLKID_PCIE_PLL_OD 90
#define CLKID_VPU_0_DIV 91
#define CLKID_VPU_0_SEL 92
#define CLKID_VPU_0 93
#define CLKID_VPU_1_DIV 94
#define CLKID_VPU_1_SEL 95
#define CLKID_VPU_1 96
#define CLKID_VPU 97
#define CLKID_VAPB_0_DIV 98
#define CLKID_VAPB_0_SEL 99
#define CLKID_VAPB_0 100
#define CLKID_VAPB_1_DIV 101
#define CLKID_VAPB_1_SEL 102
#define CLKID_VAPB_1 103
#define CLKID_VAPB_SEL 104
#define CLKID_VAPB 105
#define CLKID_VCLK 106
#define CLKID_VCLK2 107
#define CLKID_VCLK_SEL 108
#define CLKID_VCLK2_SEL 109
#define CLKID_VCLK_INPUT 110
#define CLKID_VCLK2_INPUT 111
#define CLKID_VCLK_DIV 112
#define CLKID_VCLK2_DIV 113
#define CLKID_VCLK_DIV2_EN 114
#define CLKID_VCLK_DIV4_EN 115
#define CLKID_VCLK_DIV6_EN 116
#define CLKID_VCLK_DIV12_EN 117
#define CLKID_VCLK2_DIV2_EN 118
#define CLKID_VCLK2_DIV4_EN 119
#define CLKID_VCLK2_DIV6_EN 120
#define CLKID_VCLK2_DIV12_EN 121
#define CLKID_VCLK_DIV1 122
#define CLKID_VCLK_DIV2 123
#define CLKID_VCLK_DIV4 124
#define CLKID_VCLK_DIV6 125
#define CLKID_VCLK_DIV12 126
#define CLKID_VCLK2_DIV1 127
#define CLKID_VCLK2_DIV2 128
#define CLKID_VCLK2_DIV4 129
#define CLKID_VCLK2_DIV6 130
#define CLKID_VCLK2_DIV12 131
#define CLKID_CTS_ENCL_SEL 132
#define CLKID_CTS_ENCL 133
#define CLKID_VDIN_MEAS_SEL 134
#define CLKID_VDIN_MEAS_DIV 135
#define CLKID_VDIN_MEAS 136
#endif /* __AXG_CLKC_H */
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