[
{
"ArchStdEvent": "SW_INCR"
},
{
"ArchStdEvent": "INST_RETIRED"
},
{
"ArchStdEvent": "EXC_RETURN"
},
{
"ArchStdEvent": "CID_WRITE_RETIRED"
},
{
"ArchStdEvent": "INST_SPEC"
},
{
"ArchStdEvent": "LDREX_SPEC"
},
{
"ArchStdEvent": "STREX_SPEC"
},
{
"ArchStdEvent": "LD_SPEC"
},
{
"ArchStdEvent": "ST_SPEC"
},
{
"ArchStdEvent": "LDST_SPEC"
},
{
"ArchStdEvent": "DP_SPEC"
},
{
"ArchStdEvent": "ASE_SPEC"
},
{
"ArchStdEvent": "VFP_SPEC"
},
{
"ArchStdEvent": "PC_WRITE_SPEC"
},
{
"ArchStdEvent": "CRYPTO_SPEC"
},
{
"ArchStdEvent": "BR_IMMED_SPEC"
},
{
"ArchStdEvent": "BR_RETURN_SPEC"
},
{
"ArchStdEvent": "BR_INDIRECT_SPEC"
},
{
"ArchStdEvent": "ISB_SPEC"
},
{
"ArchStdEvent": "DSB_SPEC"
},
{
"ArchStdEvent": "DMB_SPEC"
},
{
"PublicDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction.",
"EventCode": "0x9F",
"EventName": "DCZVA_SPEC",
"BriefDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction."
},
{
"PublicDescription": "This event counts architecturally executed floating-point move operations.",
"EventCode": "0x105",
"EventName": "FP_MV_SPEC",
"BriefDescription": "This event counts architecturally executed floating-point move operations."
},
{
"PublicDescription": "This event counts architecturally executed operations that using predicate register.",
"EventCode": "0x108",
"EventName": "PRD_SPEC",
"BriefDescription": "This event counts architecturally executed operations that using predicate register."
},
{
"PublicDescription": "This event counts architecturally executed inter-element manipulation operations.",
"EventCode": "0x109",
"EventName": "IEL_SPEC",
"BriefDescription": "This event counts architecturally executed inter-element manipulation operations."
},
{
"PublicDescription": "This event counts architecturally executed inter-register manipulation operations.",
"EventCode": "0x10A",
"EventName": "IREG_SPEC",
"BriefDescription": "This event counts architecturally executed inter-register manipulation operations."
},
{
"PublicDescription": "This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers.",
"EventCode": "0x112",
"EventName": "FP_LD_SPEC",
"BriefDescription": "This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers."
},
{
"PublicDescription": "This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers.",
"EventCode": "0x113",
"EventName": "FP_ST_SPEC",
"BriefDescription": "This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers."
},
{
"PublicDescription": "This event counts architecturally executed SIMD broadcast floating-point load operations.",
"EventCode": "0x11A",
"EventName": "BC_LD_SPEC",
"BriefDescription": "This event counts architecturally executed SIMD broadcast floating-point load operations."
},
{
"PublicDescription": "This event counts architecturally executed instructions, excluding the MOVPRFX instruction.",
"EventCode": "0x121",
"EventName": "EFFECTIVE_INST_SPEC",
"BriefDescription": "This event counts architecturally executed instructions, excluding the MOVPRFX instruction."
},
{
"PublicDescription": "This event counts architecturally executed operations that uses 'pre-index' as its addressing mode.",
"EventCode": "0x123",
"EventName": "PRE_INDEX_SPEC",
"BriefDescription": "This event counts architecturally executed operations that uses 'pre-index' as its addressing mode."
},
{
"PublicDescription": "This event counts architecturally executed operations that uses 'post-index' as its addressing mode.",
"EventCode": "0x124",
"EventName": "POST_INDEX_SPEC",
"BriefDescription": "This event counts architecturally executed operations that uses 'post-index' as its addressing mode."
}
]
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