linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/cache.json

[
    {
        "ArchStdEvent": "L1I_CACHE_REFILL"
    },
    {
        "ArchStdEvent": "L1I_TLB_REFILL"
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL"
    },
    {
        "ArchStdEvent": "L1D_CACHE"
    },
    {
        "ArchStdEvent": "L1D_TLB_REFILL"
    },
    {
        "ArchStdEvent": "L1I_CACHE"
    },
    {
        "ArchStdEvent": "L1D_CACHE_WB"
    },
    {
        "ArchStdEvent": "L2D_CACHE"
    },
    {
        "ArchStdEvent": "L2D_CACHE_REFILL"
    },
    {
        "ArchStdEvent": "L2D_CACHE_WB"
    },
    {
        "ArchStdEvent": "L2D_CACHE_ALLOCATE"
    },
    {
        "ArchStdEvent": "L1D_TLB"
    },
    {
        "ArchStdEvent": "L1I_TLB"
    },
    {
        "ArchStdEvent": "L3D_CACHE_ALLOCATE"
    },
    {
        "ArchStdEvent": "L3D_CACHE_REFILL"
    },
    {
        "ArchStdEvent": "L3D_CACHE"
    },
    {
        "ArchStdEvent": "L2D_TLB_REFILL"
    },
    {
        "ArchStdEvent": "L2D_TLB"
    },
    {
        "ArchStdEvent": "DTLB_WALK"
    },
    {
        "ArchStdEvent": "ITLB_WALK"
    },
    {
        "ArchStdEvent": "LL_CACHE_RD"
    },
    {
        "ArchStdEvent": "LL_CACHE_MISS_RD"
    },
    {
        "ArchStdEvent": "L1D_CACHE_RD"
    },
    {
        "ArchStdEvent": "L1D_CACHE_WR"
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL_RD"
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL_WR"
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL_INNER"
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
    },
    {
        "ArchStdEvent": "L1D_CACHE_WB_VICTIM"
    },
    {
        "ArchStdEvent": "L1D_CACHE_WB_CLEAN"
    },
    {
        "ArchStdEvent": "L1D_CACHE_INVAL"
    },
    {
        "ArchStdEvent": "L1D_TLB_REFILL_RD"
    },
    {
        "ArchStdEvent": "L1D_TLB_REFILL_WR"
    },
    {
        "ArchStdEvent": "L1D_TLB_RD"
    },
    {
        "ArchStdEvent": "L1D_TLB_WR"
    },
    {
        "ArchStdEvent": "L2D_CACHE_RD"
    },
    {
        "ArchStdEvent": "L2D_CACHE_WR"
    },
    {
        "ArchStdEvent": "L2D_CACHE_REFILL_RD"
    },
    {
        "ArchStdEvent": "L2D_CACHE_REFILL_WR"
    },
    {
        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
    },
    {
        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
    },
    {
        "ArchStdEvent": "L2D_CACHE_INVAL"
    },
    {
        "ArchStdEvent": "L2D_TLB_REFILL_RD"
    },
    {
        "ArchStdEvent": "L2D_TLB_REFILL_WR"
    },
    {
        "ArchStdEvent": "L2D_TLB_RD"
    },
    {
        "ArchStdEvent": "L2D_TLB_WR"
    },
    {
        "ArchStdEvent": "L3D_CACHE_RD"
    }
]