// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/reset/qcom,gcc-msm8960.h>
#include <dt-bindings/clock/qcom,lcc-msm8960.h>
#include <dt-bindings/mfd/qcom-rpm.h>
#include <dt-bindings/soc/qcom,gsbi.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Qualcomm MSM8960";
compatible = "qcom,msm8960";
interrupt-parent = <&intc>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_PPI 14 0x304>;
cpu@0 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
};
cpu@1 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
};
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0>;
};
cpu-pmu {
compatible = "qcom,krait-pmu";
interrupts = <GIC_PPI 10 0x304>;
qcom,no-pc-write;
};
clocks {
cxo_board: cxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
clock-output-names = "cxo_board";
};
pxo_board: pxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
clock-output-names = "pxo_board";
};
sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "sleep_clk";
};
};
/* Temporary fixed regulator */
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
regulator-name = "SDCC Power";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
regulator-always-on;
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "simple-bus";
intc: interrupt-controller@2000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x02000000 0x1000>,
<0x02002000 0x1000>;
};
timer@200a000 {
compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer",
"qcom,msm-timer";
interrupts = <GIC_PPI 1 0x301>,
<GIC_PPI 2 0x301>,
<GIC_PPI 3 0x301>;
reg = <0x0200a000 0x100>;
clock-frequency = <27000000>;
cpu-offset = <0x80000>;
};
msmgpio: pinctrl@800000 {
compatible = "qcom,msm8960-pinctrl";
gpio-controller;
gpio-ranges = <&msmgpio 0 0 152>;
#gpio-cells = <2>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x800000 0x4000>;
};
gcc: clock-controller@900000 {
compatible = "qcom,gcc-msm8960";
#clock-cells = <1>;
#reset-cells = <1>;
reg = <0x900000 0x4000>;
clocks = <&cxo_board>,
<&pxo_board>,
<&lcc PLL4>;
clock-names = "cxo", "pxo", "pll4";
};
lcc: clock-controller@28000000 {
compatible = "qcom,lcc-msm8960";
reg = <0x28000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&pxo_board>,
<&gcc PLL4_VOTE>,
<0>,
<0>, <0>,
<0>, <0>,
<0>;
clock-names = "pxo",
"pll4_vote",
"mi2s_codec_clk",
"codec_i2s_mic_codec_clk",
"spare_i2s_mic_codec_clk",
"codec_i2s_spkr_codec_clk",
"spare_i2s_spkr_codec_clk",
"pcm_codec_clk";
};
clock-controller@4000000 {
compatible = "qcom,mmcc-msm8960";
reg = <0x4000000 0x1000>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
clocks = <&pxo_board>,
<&gcc PLL3>,
<&gcc PLL8_VOTE>,
<0>,
<0>,
<0>,
<0>,
<0>;
clock-names = "pxo",
"pll3",
"pll8_vote",
"dsi1pll",
"dsi1pllbyte",
"dsi2pll",
"dsi2pllbyte",
"hdmipll";
};
l2cc: clock-controller@2011000 {
compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon";
reg = <0x2011000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
#clock-cells = <0>;
};
rpm: rpm@108000 {
compatible = "qcom,rpm-msm8960";
reg = <0x108000 0x1000>;
qcom,ipc = <&l2cc 0x8 2>;
interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ack", "err", "wakeup";
};
acc0: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu0_aux";
#clock-cells = <0>;
};
acc1: clock-controller@2098000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu1_aux";
#clock-cells = <0>;
};
saw0: power-manager@2089000 {
compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
saw0_vreg: regulator {
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1300000>;
};
};
saw1: power-manager@2099000 {
compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
saw1_vreg: regulator {
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1300000>;
};
};
gsbi5: gsbi@16400000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <5>;
reg = <0x16400000 0x100>;
clocks = <&gcc GSBI5_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
ranges;
syscon-tcsr = <&tcsr>;
gsbi5_serial: serial@16440000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16440000 0x1000>,
<0x16400000 0x1000>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
};
ssbi: ssbi@500000 {
compatible = "qcom,ssbi";
reg = <0x500000 0x1000>;
qcom,controller-type = "pmic-arbiter";
};
rng@1a500000 {
compatible = "qcom,prng";
reg = <0x1a500000 0x200>;
clocks = <&gcc PRNG_CLK>;
clock-names = "core";
};
sdcc3: mmc@12180000 {
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";
reg = <0x12180000 0x8000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <192000000>;
no-1-8-v;
vmmc-supply = <&vsdcc_fixed>;
};
sdcc1: mmc@12400000 {
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
reg = <0x12400000 0x8000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
max-frequency = <96000000>;
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
vmmc-supply = <&vsdcc_fixed>;
};
tcsr: syscon@1a400000 {
compatible = "qcom,tcsr-msm8960", "syscon";
reg = <0x1a400000 0x100>;
};
gsbi1: gsbi@16000000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <1>;
reg = <0x16000000 0x100>;
clocks = <&gcc GSBI1_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
ranges;
gsbi1_spi: spi@16080000 {
compatible = "qcom,spi-qup-v1.1.1";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x16080000 0x1000>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
cs-gpios = <&msmgpio 8 0>;
clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
};
usb1: usb@12500000 {
compatible = "qcom,ci-hdrc";
reg = <0x12500000 0x200>,
<0x12500200 0x200>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
clock-names = "core", "iface";
assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
assigned-clock-rates = <60000000>;
resets = <&gcc USB_HS1_RESET>;
reset-names = "core";
phy_type = "ulpi";
ahb-burst-config = <0>;
phys = <&usb_hs1_phy>;
phy-names = "usb-phy";
#reset-cells = <1>;
status = "disabled";
ulpi {
usb_hs1_phy: phy {
compatible = "qcom,usb-hs-phy-msm8960",
"qcom,usb-hs-phy";
clocks = <&sleep_clk>, <&cxo_board>;
clock-names = "sleep", "ref";
resets = <&usb1 0>;
reset-names = "por";
#phy-cells = <0>;
};
};
};
gsbi3: gsbi@16200000 {
compatible = "qcom,gsbi-v1.0.0";
reg = <0x16200000 0x100>;
ranges;
cell-index = <3>;
clocks = <&gcc GSBI3_H_CLK>;
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
gsbi3_i2c: i2c@16280000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x16280000 0x1000>;
pinctrl-0 = <&i2c3_default_state>;
pinctrl-1 = <&i2c3_sleep_state>;
pinctrl-names = "default", "sleep";
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI3_QUP_CLK>,
<&gcc GSBI3_H_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
};
};
#include "qcom-msm8960-pins.dtsi"
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