// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#include "imx8mp.dtsi"
#include <dt-bindings/leds/common.h>
/ {
aliases {
/* some of this aliases like backlight0, ethernetX and switch0
* are needed for the bootloader.
*/
backlight0 = &backlight;
ethernet0 = &eqos;
ethernet1 = &lan1;
ethernet2 = &lan2;
rtc0 = &i2c_rtc;
rtc1 = &snvs_rtc;
switch0 = &switch;
};
/*
* Backlight is present only on some of boards, so it is disabled by
* default.
*/
backlight: backlight {
compatible = "pwm-backlight";
pinctrl-0 = <&pinctrl_backlight>;
pwms = <&pwm1 0 20000 0>;
power-supply = <®_24v>;
enable-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
brightness-levels = <0 255>;
num-interpolated-steps = <17>;
default-brightness-level = <8>;
status = "disabled";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
led-0 {
label = "D1";
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_STATUS;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led-1 {
label = "D2";
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-2 {
label = "D3";
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
reg_1v2: regulator-1v2 {
compatible = "regulator-fixed";
vin-supply = <®_5v_p>;
regulator-name = "1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
reg_2v5: regulator-2v5 {
compatible = "regulator-fixed";
vin-supply = <®_5v_s>;
regulator-name = "2V5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
vin-supply = <®_5v_s>;
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
/*
* This regulator will provide power as long as possible even if
* undervoltage is detected.
*/
reg_5v_p: regulator-5v-p {
compatible = "regulator-fixed";
regulator-name = "5V_P";
vin-supply = <®_24v>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
/*
* This regulator will be automatically shutdown if undervoltage is
* detected.
*/
reg_5v_s: regulator-5v-s {
compatible = "regulator-fixed";
regulator-name = "5V_S";
vin-supply = <®_24v>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_24v: regulator-24v {
compatible = "regulator-fixed";
regulator-name = "24V";
regulator-min-microvolt = <24000000>;
regulator-max-microvolt = <24000000>;
};
reg_can2rs: regulator-can2rs {
compatible = "regulator-fixed";
regulator-name = "CAN2RS";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can2rs>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 22 GPIO_ACTIVE_LOW>;
};
reg_canrs: regulator-canrs {
compatible = "regulator-fixed";
regulator-name = "CANRS";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_canrs>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
};
reg_tft_vcom: regulator-tft-vcom {
compatible = "pwm-regulator";
pwms = <&pwm4 0 20000 0>;
regulator-name = "VCOM";
vin-supply = <®_5v_s>;
regulator-min-microvolt = <3600000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
voltage-table = <3600000 26>;
status = "disabled";
};
reg_vsd_3v3: regulator-vsd-3v3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_vsd_3v3>;
vin-supply = <®_vdd_3v3>;
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&A53_0 {
cpu-supply = <®_vdd_arm>;
};
&A53_1 {
cpu-supply = <®_vdd_arm>;
};
&A53_2 {
cpu-supply = <®_vdd_arm>;
};
&A53_3 {
cpu-supply = <®_vdd_arm>;
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
adc: adc@0 {
compatible = "microchip,mcp3002";
reg = <0>;
vref-supply = <®_vdd_3v3>;
spi-max-frequency = <1000000>;
#io-channel-cells = <1>;
};
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-txid";
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <®_canrs>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <®_can2rs>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupts-extended = <&gpio1 3 IRQ_TYPE_EDGE_RISING>;
sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
regulators {
reg_vdd_soc: BUCK1 {
regulator-name = "VDD_SOC";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
vin-supply = <®_5v_p>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
reg_vdd_arm: BUCK2 {
regulator-name = "VDD_ARM";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
vin-supply = <®_5v_p>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
reg_vdd_3v3: BUCK4 {
regulator-name = "VDD_3V3";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
vin-supply = <®_5v_p>;
regulator-boot-on;
regulator-always-on;
};
reg_vdd_1v8: BUCK5 {
regulator-name = "VDD_1V8";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
vin-supply = <®_5v_p>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_dram_1v1: BUCK6 {
regulator-name = "NVCC_DRAM_1V1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
vin-supply = <®_5v_p>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_snvs_1v8: LDO1 {
regulator-name = "NVCC_SNVS_1V8";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
vin-supply = <®_5v_p>;
regulator-boot-on;
regulator-always-on;
};
reg_vdda_1v8: LDO3 {
regulator-name = "VDDA_1V8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
vin-supply = <®_5v_p>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_sd2: LDO5 {
regulator-name = "NVCC_SD2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
vin-supply = <®_5v_p>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
i2c_rtc: rtc@51 {
compatible = "nxp,pcf85063tp";
reg = <0x51>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupts-extended = <&gpio4 31 IRQ_TYPE_EDGE_FALLING>;
quartz-load-femtofarads = <12500>;
};
};
&i2c4 {
clock-frequency = <380000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
switch: switch@5f {
compatible = "microchip,ksz9893";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_switch>;
reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
reg = <0x5f>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
lan1: port@0 {
reg = <0>;
phy-mode = "internal";
label = "lan1";
};
lan2: port@1 {
reg = <1>;
phy-mode = "internal";
label = "lan2";
};
port@2 {
reg = <2>;
label = "cpu";
ethernet = <&eqos>;
phy-mode = "rgmii";
/* 2ns RX delay is implemented on PCB */
tx-internal-delay-ps = <2000>;
rx-internal-delay-ps = <0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
/* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb3_phy0 {
vbus-supply = <®_3v3>;
status = "okay";
};
&usb3_phy1 {
vbus-supply = <®_3v3>;
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "host";
};
&usb_dwc3_1 {
dr_mode = "host";
};
/* SD Card */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
vmmc-supply = <®_vsd_3v3>;
vqmmc-supply = <®_nvcc_sd2>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
status = "okay";
};
/* eMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
vmmc-supply = <®_vdd_3v3>;
vqmmc-supply = <®_vdd_1v8>;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_backlight: backlightgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x0100
>;
};
pinctrl_can2rs: can2rsgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x154
>;
};
pinctrl_canrs: canrsgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x154
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154
MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x19
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x41
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x116
>;
};
pinctrl_reg_vsd_3v3: regvsd3v3grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x41
>;
};
pinctrl_switch: switchgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x41
MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x41
>;
};
pinctrl_touchscreen: touchscreengrp {
fsl,pins = <
/* external 10 k pull up */
/* CTP_INT */
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x41
/* CTP_RST */
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x41
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x1c4
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
>;
};
};
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