// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2016-2022, AngeloGioacchino Del Regno
* <[email protected]>
* Copyright (c) 2022, Konrad Dybcio <[email protected]>
* Copyright (c) 2022, Marijn Suijten <[email protected]>
*/
#include <dt-bindings/clock/qcom,gcc-msm8976.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/qcom-rpmpd.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
cpu-idle-states = <&little_cpu_sleep_0>;
capacity-dmips-mhz = <573>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
cpu-idle-states = <&little_cpu_sleep_0>;
capacity-dmips-mhz = <573>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
enable-method = "psci";
cpu-idle-states = <&little_cpu_sleep_0>;
capacity-dmips-mhz = <573>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
enable-method = "psci";
cpu-idle-states = <&little_cpu_sleep_0>;
capacity-dmips-mhz = <573>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
CPU4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x100>;
enable-method = "psci";
cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
CPU5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x101>;
enable-method = "psci";
cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
CPU6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x102>;
enable-method = "psci";
cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
CPU7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x103>;
enable-method = "psci";
cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
};
idle-states {
entry-method = "psci";
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "little-power-collapse";
arm,psci-suspend-param = <0x40000003>;
entry-latency-us = <181>;
exit-latency-us = <149>;
min-residency-us = <703>;
local-timer-stop;
};
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "big-retention";
arm,psci-suspend-param = <0x00000002>;
entry-latency-us = <142>;
exit-latency-us = <99>;
min-residency-us = <242>;
};
big_cpu_sleep_1: cpu-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "big-power-collapse";
arm,psci-suspend-param = <0x40000003>;
entry-latency-us = <158>;
exit-latency-us = <144>;
min-residency-us = <863>;
local-timer-stop;
};
};
l2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
firmware {
scm: scm {
compatible = "qcom,scm-msm8976", "qcom,scm";
clocks = <&gcc GCC_CRYPTO_CLK>,
<&gcc GCC_CRYPTO_AXI_CLK>,
<&gcc GCC_CRYPTO_AHB_CLK>;
clock-names = "core", "bus", "iface";
#reset-cells = <1>;
qcom,dload-mode = <&tcsr 0x6100>;
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0x0 0x80000000 0x0 0x0>;
};
pmu-a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
pmu_a72: pmu-a72 {
compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0xf0) | IRQ_TYPE_LEVEL_HIGH)>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
rpm: remoteproc {
compatible = "qcom,msm8976-rpm-proc", "qcom,rpm-proc";
smd-edge {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs 0>;
qcom,smd-edge = <15>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8976";
qcom,smd-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc";
clocks = <&xo_board>;
clock-names = "xo";
#clock-cells = <1>;
};
rpmpd: power-controller {
compatible = "qcom,msm8976-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp_ret: opp1 {
opp-level = <RPM_SMD_LEVEL_RETENTION>;
};
rpmpd_opp_ret_plus: opp2 {
opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
};
rpmpd_opp_min_svs: opp3 {
opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
};
rpmpd_opp_low_svs: opp4 {
opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
};
rpmpd_opp_svs: opp5 {
opp-level = <RPM_SMD_LEVEL_SVS>;
};
rpmpd_opp_svs_plus: opp6 {
opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
};
rpmpd_opp_nom: opp7 {
opp-level = <RPM_SMD_LEVEL_NOM>;
};
rpmpd_opp_nom_plus: opp8 {
opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
};
rpmpd_opp_turbo: opp9 {
opp-level = <RPM_SMD_LEVEL_TURBO>;
};
rpmpd_opp_turbo_no_cpr: opp10 {
opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
};
rpmpd_opp_turbo_high: opp111 {
opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>;
};
};
};
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
ext-region@85b00000 {
reg = <0x0 0x85b00000 0x0 0x500000>;
no-map;
};
smem@86300000 {
compatible = "qcom,smem";
reg = <0x0 0x86300000 0x0 0x100000>;
no-map;
hwlocks = <&tcsr_mutex 3>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
};
reserved@86400000 {
reg = <0x0 0x86400000 0x0 0x800000>;
no-map;
};
mpss_mem: mpss@86c00000 {
reg = <0x0 0x86c00000 0x0 0x5600000>;
no-map;
};
lpass_mem: lpass@8c200000 {
reg = <0x0 0x8c200000 0x0 0x1000000>;
no-map;
};
wcnss_fw_mem: wcnss@8d200000 {
reg = <0x0 0x8d200000 0x0 0x800000>;
no-map;
};
venus_mem: memory@8da00000 {
reg = <0x0 0x8da00000 0x0 0x2600000>;
no-map;
};
tz-apps@8dd00000 {
reg = <0x0 0x8dd00000 0x0 0x1400000>;
no-map;
};
};
smp2p-hexagon {
compatible = "qcom,smp2p";
interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs 10>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
qcom,smem = <443>, <429>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-modem {
compatible = "qcom,smp2p";
interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
qcom,smem = <435>, <428>;
modem_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
modem_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-wcnss {
compatible = "qcom,smp2p";
interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs 18>;
qcom,local-pid = <0>;
qcom,remote-pid = <4>;
qcom,smem = <451>, <431>;
wcnss_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
wcnss_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smsm {
compatible = "qcom,smsm";
#address-cells = <1>;
#size-cells = <0>;
mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>;
apps_smsm: apps@0 {
reg = <0>;
#qcom,smem-state-cells = <1>;
};
hexagon_smsm: hexagon@1 {
reg = <1>;
interrupts = <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
};
wcnss_smsm: wcnss@6 {
reg = <6>;
interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
soc: soc@0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
rng@22000 {
compatible = "qcom,prng";
reg = <0x00022000 0x140>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
rpm_msg_ram: sram@60000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x00060000 0x8000>;
};
usb_hs_phy: phy@6c000 {
compatible = "qcom,usb-hs-28nm-femtophy";
reg = <0x0006c000 0x200>;
#phy-cells = <0>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB2A_PHY_SLEEP_CLK>;
clock-names = "ref", "ahb", "sleep";
resets = <&gcc RST_QUSB2_PHY_BCR>,
<&gcc RST_USB2_HS_PHY_ONLY_BCR>;
reset-names = "phy", "por";
status = "disabled";
};
qfprom: qfprom@a4000 {
compatible = "qcom,msm8976-qfprom", "qcom,qfprom";
reg = <0x000a4000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
tsens_base1: base1@218 {
reg = <0x218 1>;
bits = <0 8>;
};
tsens_s0_p1: s0-p1@219 {
reg = <0x219 0x1>;
bits = <0 6>;
};
tsens_s0_p2: s0-p2@219 {
reg = <0x219 0x2>;
bits = <6 6>;
};
tsens_s1_p1: s1-p1@21a {
reg = <0x21a 0x2>;
bits = <4 6>;
};
tsens_s1_p2: s1-p2@21b {
reg = <0x21b 0x1>;
bits = <2 6>;
};
tsens_s2_p1: s2-p1@21c {
reg = <0x21c 0x1>;
bits = <0 6>;
};
tsens_s2_p2: s2-p2@21c {
reg = <0x21c 0x2>;
bits = <6 6>;
};
tsens_s3_p1: s3-p1@21d {
reg = <0x21d 0x2>;
bits = <4 6>;
};
tsens_s3_p2: s3-p2@21e {
reg = <0x21e 0x1>;
bits = <2 6>;
};
tsens_base2: base2@220 {
reg = <0x220 1>;
bits = <0 8>;
};
tsens_s4_p1: s4-p1@221 {
reg = <0x221 0x1>;
bits = <0 6>;
};
tsens_s4_p2: s4-p2@221 {
reg = <0x221 0x2>;
bits = <6 6>;
};
tsens_s5_p1: s5-p1@222 {
reg = <0x222 0x2>;
bits = <4 6>;
};
tsens_s5_p2: s5-p2@223 {
reg = <0x224 0x1>;
bits = <2 6>;
};
tsens_s6_p1: s6-p1@224 {
reg = <0x224 0x1>;
bits = <0 6>;
};
tsens_s6_p2: s6-p2@224 {
reg = <0x224 0x2>;
bits = <6 6>;
};
tsens_s7_p1: s7-p1@225 {
reg = <0x225 0x2>;
bits = <4 6>;
};
tsens_s7_p2: s7-p2@226 {
reg = <0x226 0x2>;
bits = <2 6>;
};
tsens_mode: mode@228 {
reg = <0x228 1>;
bits = <0 3>;
};
tsens_s8_p1: s8-p1@228 {
reg = <0x228 0x2>;
bits = <3 6>;
};
tsens_s8_p2: s8-p2@229 {
reg = <0x229 0x1>;
bits = <1 6>;
};
tsens_s9_p1: s9-p1@229 {
reg = <0x229 0x2>;
bits = <7 6>;
};
tsens_s9_p2: s9-p2@22a {
reg = <0x22a 0x2>;
bits = <5 6>;
};
tsens_s10_p1: s10-p1@22b {
reg = <0x22b 0x2>;
bits = <3 6>;
};
tsens_s10_p2: s10-p2@22c {
reg = <0x22c 0x1>;
bits = <1 6>;
};
};
tsens: thermal-sensor@4a9000 {
compatible = "qcom,msm8976-tsens", "qcom,tsens-v1";
reg = <0x004a9000 0x1000>, /* TM */
<0x004a8000 0x1000>; /* SROT */
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";
nvmem-cells = <&tsens_mode>,
<&tsens_base1>, <&tsens_base2>,
<&tsens_s0_p1>, <&tsens_s0_p2>,
<&tsens_s1_p1>, <&tsens_s1_p2>,
<&tsens_s2_p1>, <&tsens_s2_p2>,
<&tsens_s3_p1>, <&tsens_s3_p2>,
<&tsens_s4_p1>, <&tsens_s4_p2>,
<&tsens_s5_p1>, <&tsens_s5_p2>,
<&tsens_s6_p1>, <&tsens_s6_p2>,
<&tsens_s7_p1>, <&tsens_s7_p2>,
<&tsens_s8_p1>, <&tsens_s8_p2>,
<&tsens_s9_p1>, <&tsens_s9_p2>,
<&tsens_s10_p1>, <&tsens_s10_p2>;
nvmem-cell-names = "mode",
"base1", "base2",
"s0_p1", "s0_p2",
"s1_p1", "s1_p2",
"s2_p1", "s2_p2",
"s3_p1", "s3_p2",
"s4_p1", "s4_p2",
"s5_p1", "s5_p2",
"s6_p1", "s6_p2",
"s7_p1", "s7_p2",
"s8_p1", "s8_p2",
"s9_p1", "s9_p2",
"s10_p1", "s10_p2";
#qcom,sensors = <11>;
#thermal-sensor-cells = <1>;
};
tlmm: pinctrl@1000000 {
compatible = "qcom,msm8976-pinctrl";
reg = <0x01000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 145>;
interrupt-controller;
#interrupt-cells = <2>;
spi1_default: spi0-default-state {
spi-pins {
pins = "gpio0", "gpio1", "gpio3";
function = "blsp_spi1";
drive-strength = <12>;
bias-disable;
};
cs-pins {
pins = "gpio2";
function = "blsp_spi1";
drive-strength = <2>;
bias-disable;
};
};
spi1_sleep: spi0-sleep-state {
spi-pins {
pins = "gpio0", "gpio1", "gpio3";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
cs-pins {
pins = "gpio2";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};
blsp1_i2c2_default: blsp1-i2c2-default-state {
pins = "gpio6", "gpio7";
function = "blsp_i2c2";
drive-strength = <2>;
bias-disable;
};
blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
pins = "gpio6", "gpio7";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
blsp1_i2c4_default: blsp1-i2c4-default-state {
pins = "gpio14", "gpio15";
function = "blsp_i2c4";
drive-strength = <2>;
bias-disable;
};
blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
pins = "gpio14", "gpio15";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
blsp2_uart2_active: blsp2-uart2-active-state {
pins = "gpio20", "gpio21";
function = "blsp_uart6";
drive-strength = <4>;
bias-disable;
};
blsp2_uart2_sleep: blsp2-uart2-sleep-state {
pins = "gpio20", "gpio21";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
/* 4 (not 6!) interfaces per QUP, BLSP2 indexes are numbered (n)+4 */
blsp2_i2c2_default: blsp2-i2c2-default-state {
pins = "gpio22", "gpio23";
function = "blsp_i2c6";
drive-strength = <2>;
bias-disable;
};
blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
pins = "gpio22", "gpio23";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
blsp2_i2c4_default: blsp2-i2c4-default-state {
pins = "gpio18", "gpio19";
function = "blsp_i2c8";
drive-strength = <2>;
bias-disable;
};
blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
pins = "gpio18", "gpio19";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wcss_wlan_default: wcss-wlan-default-state {
wcss-wlan2-pins {
pins = "gpio40";
function = "wcss_wlan2";
drive-strength = <6>;
bias-pull-up;
};
wcss-wlan1-pins {
pins = "gpio41";
function = "wcss_wlan1";
drive-strength = <6>;
bias-pull-up;
};
wcss-wlan0-pins {
pins = "gpio42";
function = "wcss_wlan0";
drive-strength = <6>;
bias-pull-up;
};
wcss-wlan-pins {
pins = "gpio43", "gpio44";
function = "wcss_wlan";
drive-strength = <6>;
bias-pull-up;
};
};
};
gcc: clock-controller@1800000 {
compatible = "qcom,gcc-msm8976";
reg = <0x01800000 0x80000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
assigned-clocks = <&gcc GPLL3>;
assigned-clock-rates = <1100000000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&rpmcc RPM_SMD_XO_A_CLK_SRC>,
<&mdss_dsi0_phy 1>,
<&mdss_dsi0_phy 0>,
<&mdss_dsi1_phy 1>,
<&mdss_dsi1_phy 0>;
clock-names = "xo",
"xo_a",
"dsi0pll",
"dsi0pllbyte",
"dsi1pll",
"dsi1pllbyte";
};
tcsr_mutex: hwlock@1905000 {
compatible = "qcom,tcsr-mutex";
reg = <0x01905000 0x20000>;
#hwlock-cells = <1>;
};
tcsr: syscon@1937000 {
compatible = "qcom,msm8976-tcsr", "syscon";
reg = <0x01937000 0x30000>;
};
mdss: display-subsystem@1a00000 {
compatible = "qcom,mdss";
reg = <0x01a00000 0x1000>,
<0x01ab0000 0x3000>;
reg-names = "mdss_phys", "vbif_phys";
power-domains = <&gcc MDSS_GDSC>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_VSYNC_CLK>,
<&gcc GCC_MDSS_MDP_CLK>;
clock-names = "iface",
"bus",
"vsync",
"core";
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
mdss_mdp: display-controller@1a01000 {
compatible = "qcom,msm8976-mdp5", "qcom,mdp5";
reg = <0x01a01000 0x89000>;
reg-names = "mdp_phys";
interrupt-parent = <&mdss>;
interrupts = <0>;
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_VSYNC_CLK>,
<&gcc GCC_MDP_TBU_CLK>,
<&gcc GCC_MDP_RT_TBU_CLK>;
clock-names = "iface",
"bus",
"core",
"vsync",
"tbu",
"tbu_rt";
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&gcc MDSS_GDSC>;
iommus = <&apps_iommu 22>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_mdp5_intf1_out: endpoint {
remote-endpoint = <&mdss_dsi0_in>;
};
};
port@1 {
reg = <1>;
mdss_mdp5_intf2_out: endpoint {
remote-endpoint = <&mdss_dsi1_in>;
};
};
};
mdp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-177780000 {
opp-hz = /bits/ 64 <177780000>;
required-opps = <&rpmpd_opp_svs>;
};
opp-270000000 {
opp-hz = /bits/ 64 <270000000>;
required-opps = <&rpmpd_opp_svs_plus>;
};
opp-320000000 {
opp-hz = /bits/ 64 <320000000>;
required-opps = <&rpmpd_opp_nom>;
};
opp-360000000 {
opp-hz = /bits/ 64 <360000000>;
required-opps = <&rpmpd_opp_turbo>;
};
};
};
mdss_dsi0: dsi@1a94000 {
compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x01a94000 0x300>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
clocks = <&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_BYTE0_CLK>,
<&gcc GCC_MDSS_PCLK0_CLK>,
<&gcc GCC_MDSS_ESC0_CLK>;
clock-names = "mdp_core",
"iface",
"bus",
"byte",
"pixel",
"core";
assigned-clocks = <&gcc GCC_MDSS_BYTE0_CLK_SRC>,
<&gcc GCC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>;
phys = <&mdss_dsi0_phy>;
operating-points-v2 = <&dsi0_opp_table>;
power-domains = <&gcc MDSS_GDSC>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dsi0_in: endpoint {
remote-endpoint = <&mdss_mdp5_intf1_out>;
};
};
port@1 {
reg = <1>;
mdss_dsi0_out: endpoint {
};
};
};
dsi0_opp_table: opp-table {
compatible = "operating-points-v2";
opp-125000000 {
opp-hz = /bits/ 64 <125000000>;
required-opps = <&rpmpd_opp_svs>;
};
opp-161250000 {
opp-hz = /bits/ 64 <161250000>;
required-opps = <&rpmpd_opp_svs_plus>;
};
opp-187500000 {
opp-hz = /bits/ 64 <187500000>;
required-opps = <&rpmpd_opp_nom>;
};
};
};
mdss_dsi1: dsi@1a96000 {
compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x01a96000 0x300>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <5>;
clocks = <&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_BYTE1_CLK>,
<&gcc GCC_MDSS_PCLK1_CLK>,
<&gcc GCC_MDSS_ESC1_CLK>;
clock-names = "mdp_core",
"iface",
"bus",
"byte",
"pixel",
"core";
assigned-clocks = <&gcc GCC_MDSS_BYTE1_CLK_SRC>,
<&gcc GCC_MDSS_PCLK1_CLK_SRC>;
assigned-clock-parents = <&mdss_dsi1_phy 0>,
<&mdss_dsi1_phy 1>;
phys = <&mdss_dsi1_phy>;
operating-points-v2 = <&dsi0_opp_table>;
power-domains = <&gcc MDSS_GDSC>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dsi1_in: endpoint {
remote-endpoint = <&mdss_mdp5_intf2_out>;
};
};
port@1 {
reg = <1>;
mdss_dsi1_out: endpoint {
};
};
};
};
mdss_dsi0_phy: phy@1a94a00 {
compatible = "qcom,dsi-phy-28nm-hpm-fam-b";
reg = <0x01a94a00 0xd4>,
<0x01a94400 0x280>,
<0x01a94b80 0x30>;
reg-names = "dsi_pll",
"dsi_phy",
"dsi_phy_regulator";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "ref";
status = "disabled";
};
mdss_dsi1_phy: phy@1a96a00 {
compatible = "qcom,dsi-phy-28nm-hpm-fam-b";
reg = <0x01a96a00 0xd4>,
<0x01a96400 0x280>,
<0x01a96b80 0x30>;
reg-names = "dsi_pll",
"dsi_phy",
"dsi_phy_regulator";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "ref";
status = "disabled";
};
};
adreno_gpu: gpu@1c00000 {
compatible = "qcom,adreno-510.0", "qcom,adreno";
reg = <0x01c00000 0x40000>;
reg-names = "kgsl_3d0_reg_memory";
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "kgsl_3d0_irq";
clocks = <&gcc GCC_GFX3D_OXILI_CLK>,
<&gcc GCC_GFX3D_OXILI_AHB_CLK>,
<&gcc GCC_GFX3D_OXILI_GMEM_CLK>,
<&gcc GCC_GFX3D_BIMC_CLK>,
<&gcc GCC_GFX3D_OXILI_TIMER_CLK>,
<&gcc GCC_GFX3D_OXILI_AON_CLK>;
clock-names = "core",
"iface",
"mem",
"mem_iface",
"rbbmtimer",
"alwayson";
power-domains = <&gcc OXILI_GX_GDSC>;
iommus = <&gpu_iommu 0>;
operating-points-v2 = <&gpu_opp_table>;
status = "disabled";
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
required-opps = <&rpmpd_opp_low_svs>;
opp-supported-hw = <0xff>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmpd_opp_svs>;
opp-supported-hw = <0xff>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
required-opps = <&rpmpd_opp_nom>;
opp-supported-hw = <0xff>;
};
opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
required-opps = <&rpmpd_opp_nom_plus>;
opp-supported-hw = <0xff>;
};
opp-540000000 {
opp-hz = /bits/ 64 <540000000>;
required-opps = <&rpmpd_opp_turbo>;
opp-supported-hw = <0xff>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
required-opps = <&rpmpd_opp_turbo>;
opp-supported-hw = <0xff>;
};
};
};
apps_iommu: iommu@1ee0000 {
compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2";
reg = <0x01ee0000 0x3000>;
ranges = <0 0x01e20000 0x20000>;
clocks = <&gcc GCC_SMMU_CFG_CLK>,
<&gcc GCC_APSS_TCU_CLK>;
clock-names = "iface", "bus";
qcom,iommu-secure-id = <17>;
#address-cells = <1>;
#size-cells = <1>;
#iommu-cells = <1>;
/* VFE */
iommu-ctx@15000 {
compatible = "qcom,msm-iommu-v2-ns";
reg = <0x15000 0x1000>;
qcom,ctx-asid = <20>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
};
/* VENUS NS */
iommu-ctx@16000 {
compatible = "qcom,msm-iommu-v2-ns";
reg = <0x16000 0x1000>;
qcom,ctx-asid = <21>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
};
/* MDP0 */
iommu-ctx@17000 {
compatible = "qcom,msm-iommu-v2-ns";
reg = <0x17000 0x1000>;
qcom,ctx-asid = <22>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
};
};
gpu_iommu: iommu@1f08000 {
compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2";
ranges = <0 0x01f08000 0x8000>;
clocks = <&gcc GCC_SMMU_CFG_CLK>,
<&gcc GCC_GFX3D_TCU_CLK>;
clock-names = "iface", "bus";
power-domains = <&gcc OXILI_CX_GDSC>;
qcom,iommu-secure-id = <18>;
#address-cells = <1>;
#size-cells = <1>;
#iommu-cells = <1>;
/* gfx3d user */
iommu-ctx@0 {
compatible = "qcom,msm-iommu-v2-ns";
reg = <0x0 0x1000>;
qcom,ctx-asid = <0>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
};
/* gfx3d secure */
iommu-ctx@1000 {
compatible = "qcom,msm-iommu-v2-sec";
reg = <0x1000 0x1000>;
qcom,ctx-asid = <2>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
};
/* gfx3d priv */
iommu-ctx@2000 {
compatible = "qcom,msm-iommu-v2-sec";
reg = <0x2000 0x1000>;
qcom,ctx-asid = <1>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
};
};
spmi_bus: spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0200f000 0x1000>,
<0x02400000 0x800000>,
<0x02c00000 0x800000>,
<0x03800000 0x200000>,
<0x0200a000 0x2100>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
qcom,channel = <0>;
qcom,ee = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
};
sdhc_1: mmc@7824900 {
compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
reg = <0x07824900 0x500>, <0x07824000 0x800>;
reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "core", "xo";
status = "disabled";
};
sdhc_2: mmc@7864900 {
compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
reg = <0x07864900 0x11c>, <0x07864000 0x800>;
reg-names = "hc", "core";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "core", "xo";
status = "disabled";
};
blsp1_dma: dma-controller@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07884000 0x1f000>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
};
blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078af000 0x200>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
dma-names = "tx", "rx";
status = "disabled";
};
blsp1_uart2: serial@78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078b0000 0x200>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
dma-names = "tx", "rx";
status = "disabled";
};
blsp1_spi1: spi@78b5000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b5000 0x500>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi1_default>;
pinctrl-1 = <&spi1_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp1_i2c2: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b6000 0x500>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c2_default>;
pinctrl-1 = <&blsp1_i2c2_default>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp1_i2c4: i2c@78b8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b8000 0x500>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c4_default>;
pinctrl-1 = <&blsp1_i2c4_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
otg: usb@78db000 {
compatible = "qcom,ci-hdrc";
reg = <0x078db000 0x200>,
<0x078db200 0x200>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_USB_HS_AHB_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>;
clock-names = "iface", "core";
assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
assigned-clock-rates = <80000000>;
resets = <&gcc RST_USB_HS_BCR>;
reset-names = "core";
ahb-burst-config = <0>;
dr_mode = "peripheral";
phy_type = "ulpi";
phy-names = "usb-phy";
phys = <&usb_hs_phy>;
status = "disabled";
#reset-cells = <1>;
};
sdhc_3: mmc@7a24900 {
compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
reg = <0x07a24900 0x11c>, <0x07a24000 0x800>;
reg-names = "hc", "core";
interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC3_AHB_CLK>,
<&gcc GCC_SDCC3_APPS_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "core", "xo";
status = "disabled";
};
blsp2_dma: dma-controller@7ac4000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07ac4000 0x1f000>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
};
blsp2_uart2: serial@7af0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x07af0000 0x200>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
dma-names = "tx", "rx";
status = "disabled";
};
blsp2_i2c2: i2c@7af6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07af6000 0x600>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c2_default>;
pinctrl-1 = <&blsp2_i2c2_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_i2c4: i2c@7af8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07af8000 0x600>;
interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c4_default>;
pinctrl-1 = <&blsp2_i2c4_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
wcnss: remoteproc@a204000 {
compatible = "qcom,pronto-v3-pil", "qcom,pronto";
reg = <0x0a204000 0x2000>,
<0x0a202000 0x1000>,
<0x0a21b000 0x3000>;
reg-names = "ccu",
"dxe",
"pmu";
memory-region = <&wcnss_fw_mem>;
interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
<&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack";
power-domains = <&rpmpd MSM8976_VDDCX>,
<&rpmpd MSM8976_VDDMX>;
power-domain-names = "cx", "mx";
qcom,smem-states = <&wcnss_smp2p_out 0>;
qcom,smem-state-names = "stop";
pinctrl-0 = <&wcss_wlan_default>;
pinctrl-names = "default";
status = "disabled";
wcnss_iris: iris {
/* Separate chip, compatible is board-specific */
clocks = <&rpmcc RPM_SMD_RF_CLK2>;
clock-names = "xo";
};
smd-edge {
interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs 17>;
qcom,smd-edge = <6>;
qcom,remote-pid = <4>;
label = "pronto";
wcnss_ctrl: wcnss {
compatible = "qcom,wcnss";
qcom,smd-channels = "WCNSS_CTRL";
qcom,mmio = <&wcnss>;
wcnss_bt: bluetooth {
compatible = "qcom,wcnss-bt";
};
wcnss_wifi: wifi {
compatible = "qcom,wcnss-wlan";
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
qcom,smem-states = <&apps_smsm 10>,
<&apps_smsm 9>;
qcom,smem-state-names = "tx-enable",
"tx-rings-empty";
};
};
};
};
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
interrupt-controller;
#interrupt-cells = <3>;
};
apcs: mailbox@b011000 {
compatible = "qcom,msm8976-apcs-kpss-global",
"qcom,msm8994-apcs-kpss-global", "syscon";
reg = <0x0b011000 0x1000>;
#mbox-cells = <1>;
};
timer@b120000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0b120000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clock-frequency = <19200000>;
frame@b121000 {
reg = <0x0b121000 0x1000>, <0x0b122000 0x1000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <0>;
};
frame@b123000 {
reg = <0x0b123000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <1>;
status = "disabled";
};
frame@b124000 {
reg = <0x0b124000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <2>;
status = "disabled";
};
frame@b125000 {
reg = <0x0b125000 0x1000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <3>;
status = "disabled";
};
frame@b126000 {
reg = <0x0b126000 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <4>;
status = "disabled";
};
frame@b127000 {
reg = <0x0b127000 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <5>;
status = "disabled";
};
frame@b128000 {
reg = <0x0b128000 0x1000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <6>;
status = "disabled";
};
};
imem: sram@8600000 {
compatible = "qcom,msm8976-imem", "syscon", "simple-mfd";
reg = <0x08600000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x08600000 0x1000>;
pil-reloc@94c {
compatible = "qcom,pil-reloc-info";
reg = <0x94c 0xc8>;
};
};
};
thermal-zones {
aoss0-thermal {
polling-delay-passive = <250>;
thermal-sensors = <&tsens 0>;
trips {
aoss0_alert0: trip-point0 {
temperature = <75000>;
hysteresis = <2000>;
type = "hot";
};
};
};
modem-thermal {
polling-delay-passive = <250>;
thermal-sensors = <&tsens 1>;
trips {
modem_alert0: trip-point0 {
temperature = <75000>;
hysteresis = <2000>;
type = "hot";
};
};
};
qdsp-thermal {
polling-delay-passive = <250>;
thermal-sensors = <&tsens 2>;
trips {
qdsp_alert0: trip-point0 {
temperature = <75000>;
hysteresis = <2000>;
type = "hot";
};
};
};
cam-isp-thermal {
polling-delay-passive = <250>;
thermal-sensors = <&tsens 3>;
trips {
cam_isp_alert0: trip-point0 {
temperature = <75000>;
hysteresis = <2000>;
type = "hot";
};
};
};
cpu4-thermal {
polling-delay-passive = <250>;
thermal-sensors = <&tsens 4>;
trips {
cpu4_alert0: trip-point0 {
temperature = <50000>;
hysteresis = <2000>;
type = "hot";
};
cpu4_alert1: trip-point1 {
temperature = <55000>;
hysteresis = <2000>;
type = "passive";
};
cpu4_crit: cpu-crit {
temperature = <75000>;
hysteresis = <2000>;
type = "critical";
};
};
};
cpu5-thermal {
polling-delay-passive = <250>;
thermal-sensors = <&tsens 5>;
trips {
cpu5_alert0: trip-point0 {
temperature = <50000>;
hysteresis = <2000>;
type = "hot";
};
cpu5_alert1: trip-point1 {
temperature = <55000>;
hysteresis = <2000>;
type = "passive";
};
cpu5_crit: cpu-crit {
temperature = <75000>;
hysteresis = <2000>;
type = "critical";
};
};
};
cpu6-thermal {
polling-delay-passive = <250>;
thermal-sensors = <&tsens 6>;
trips {
cpu6_alert0: trip-point0 {
temperature = <50000>;
hysteresis = <2000>;
type = "hot";
};
cpu6_alert1: trip-point1 {
temperature = <55000>;
hysteresis = <2000>;
type = "passive";
};
cpu6_crit: cpu-crit {
temperature = <75000>;
hysteresis = <2000>;
type = "critical";
};
};
};
cpu7-thermal {
polling-delay-passive = <250>;
thermal-sensors = <&tsens 7>;
trips {
cpu7_alert0: trip-point0 {
temperature = <50000>;
hysteresis = <2000>;
type = "hot";
};
cpu7_alert1: trip-point1 {
temperature = <55000>;
hysteresis = <2000>;
type = "passive";
};
cpu7_crit: cpu-crit {
temperature = <75000>;
hysteresis = <2000>;
type = "critical";
};
};
};
big-l2-thermal {
polling-delay-passive = <250>;
thermal-sensors = <&tsens 8>;
trips {
l2_alert0: trip-point0 {
temperature = <50000>;
hysteresis = <2000>;
type = "hot";
};
l2_alert1: trip-point1 {
temperature = <55000>;
hysteresis = <2000>;
type = "passive";
};
l2_crit: l2-crit {
temperature = <75000>;
hysteresis = <2000>;
type = "critical";
};
};
};
cpu0-thermal {
polling-delay-passive = <250>;
thermal-sensors = <&tsens 9>;
trips {
cpu0_alert0: trip-point0 {
temperature = <50000>;
hysteresis = <2000>;
type = "hot";
};
cpu0_alert1: trip-point1 {
temperature = <55000>;
hysteresis = <2000>;
type = "passive";
};
cpu0_crit: cpu-crit {
temperature = <75000>;
hysteresis = <2000>;
type = "critical";
};
};
};
gpu-thermal {
polling-delay-passive = <250>;
thermal-sensors = <&tsens 10>;
trips {
gpu_alert0: trip-point0 {
temperature = <50000>;
hysteresis = <2000>;
type = "hot";
};
gpu_alert1: trip-point1 {
temperature = <55000>;
hysteresis = <2000>;
type = "passive";
};
gpu_crit: gpu-crit {
temperature = <75000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
};
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