/* SPDX-License-Identifier: GPL-2.0 */ /* * R-Car LVDS Interface Registers Definitions * * Copyright (C) 2013-2015 Renesas Electronics Corporation * * Contact: Laurent Pinchart ([email protected]) */ #ifndef __RCAR_LVDS_REGS_H__ #define __RCAR_LVDS_REGS_H__ #define LVDCR0 … #define LVDCR0_DUSEL … #define LVDCR0_DMD … #define LVDCR0_LVMD_MASK … #define LVDCR0_LVMD_SHIFT … #define LVDCR0_PLLON … #define LVDCR0_PWD … #define LVDCR0_BEN … #define LVDCR0_LVEN … #define LVDCR0_LVRES … #define LVDCR1 … #define LVDCR1_CKSEL … #define LVDCR1_CHSTBY(n) … #define LVDCR1_CLKSTBY … #define LVDPLLCR … /* Gen2 & V3M */ #define LVDPLLCR_CEEN … #define LVDPLLCR_FBEN … #define LVDPLLCR_COSEL … #define LVDPLLCR_PLLDLYCNT_150M … #define LVDPLLCR_PLLDLYCNT_121M … #define LVDPLLCR_PLLDLYCNT_60M … #define LVDPLLCR_PLLDLYCNT_38M … #define LVDPLLCR_PLLDLYCNT_MASK … /* Gen3 but V3M,D3 and E3 */ #define LVDPLLCR_PLLDIVCNT_42M … #define LVDPLLCR_PLLDIVCNT_85M … #define LVDPLLCR_PLLDIVCNT_128M … #define LVDPLLCR_PLLDIVCNT_148M … #define LVDPLLCR_PLLDIVCNT_MASK … /* D3 and E3 */ #define LVDPLLCR_PLLON … #define LVDPLLCR_PLLSEL_PLL0 … #define LVDPLLCR_PLLSEL_LVX … #define LVDPLLCR_PLLSEL_PLL1 … #define LVDPLLCR_CKSEL_LVX … #define LVDPLLCR_CKSEL_EXTAL … #define LVDPLLCR_CKSEL_DU_DOTCLKIN(n) … #define LVDPLLCR_OCKSEL … #define LVDPLLCR_STP_CLKOUTE … #define LVDPLLCR_OUTCLKSEL … #define LVDPLLCR_CLKOUT … #define LVDPLLCR_PLLE(n) … #define LVDPLLCR_PLLN(n) … #define LVDPLLCR_PLLM(n) … #define LVDCTRCR … #define LVDCTRCR_CTR3SEL_ZERO … #define LVDCTRCR_CTR3SEL_ODD … #define LVDCTRCR_CTR3SEL_CDE … #define LVDCTRCR_CTR3SEL_MASK … #define LVDCTRCR_CTR2SEL_DISP … #define LVDCTRCR_CTR2SEL_ODD … #define LVDCTRCR_CTR2SEL_CDE … #define LVDCTRCR_CTR2SEL_HSYNC … #define LVDCTRCR_CTR2SEL_VSYNC … #define LVDCTRCR_CTR2SEL_MASK … #define LVDCTRCR_CTR1SEL_VSYNC … #define LVDCTRCR_CTR1SEL_DISP … #define LVDCTRCR_CTR1SEL_ODD … #define LVDCTRCR_CTR1SEL_CDE … #define LVDCTRCR_CTR1SEL_HSYNC … #define LVDCTRCR_CTR1SEL_MASK … #define LVDCTRCR_CTR0SEL_HSYNC … #define LVDCTRCR_CTR0SEL_VSYNC … #define LVDCTRCR_CTR0SEL_DISP … #define LVDCTRCR_CTR0SEL_ODD … #define LVDCTRCR_CTR0SEL_CDE … #define LVDCTRCR_CTR0SEL_MASK … #define LVDCHCR … #define LVDCHCR_CHSEL_CH(n, c) … #define LVDCHCR_CHSEL_MASK(n) … /* All registers below are specific to D3 and E3 */ #define LVDSTRIPE … #define LVDSTRIPE_ST_TRGSEL_DISP … #define LVDSTRIPE_ST_TRGSEL_HSYNC_R … #define LVDSTRIPE_ST_TRGSEL_HSYNC_F … #define LVDSTRIPE_ST_SWAP … #define LVDSTRIPE_ST_ON … #define LVDSCR … #define LVDSCR_DEPTH(n) … #define LVDSCR_BANDSET … #define LVDSCR_TWGCNT(n) … #define LVDSCR_SDIV(n) … #define LVDSCR_MODE … #define LVDSCR_RSTN … #define LVDDIV … #define LVDDIV_DIVSEL … #define LVDDIV_DIVRESET … #define LVDDIV_DIVSTP … #define LVDDIV_DIV(n) … #endif /* __RCAR_LVDS_REGS_H__ */
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