#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <video/mipi_display.h>
#include <drm/bridge/dw_mipi_dsi.h>
#include <drm/drm_mipi_dsi.h>
#include <drm/drm_print.h>
#define HWVER_130 …
#define HWVER_131 …
#define DSI_VERSION …
#define VERSION …
#define DSI_WCFGR …
#define WCFGR_DSIM …
#define WCFGR_COLMUX …
#define DSI_WCR …
#define WCR_DSIEN …
#define DSI_WISR …
#define WISR_PLLLS …
#define WISR_RRS …
#define DSI_WPCR0 …
#define WPCR0_UIX4 …
#define WPCR0_TDDL …
#define DSI_WRPCR …
#define WRPCR_PLLEN …
#define WRPCR_NDIV …
#define WRPCR_IDF …
#define WRPCR_ODF …
#define WRPCR_REGEN …
#define WRPCR_BGREN …
#define IDF_MIN …
#define IDF_MAX …
#define NDIV_MIN …
#define NDIV_MAX …
#define ODF_MIN …
#define ODF_MAX …
enum dsi_color { … };
#define LANE_MIN_KBPS …
#define LANE_MAX_KBPS …
#define SLEEP_US …
#define TIMEOUT_US …
struct dw_mipi_dsi_stm { … };
static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val)
{ … }
static inline u32 dsi_read(struct dw_mipi_dsi_stm *dsi, u32 reg)
{ … }
static inline void dsi_set(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask)
{ … }
static inline void dsi_clear(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask)
{ … }
static inline void dsi_update_bits(struct dw_mipi_dsi_stm *dsi, u32 reg,
u32 mask, u32 val)
{ … }
static enum dsi_color dsi_color_from_mipi(enum mipi_dsi_pixel_format fmt)
{ … }
static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf)
{ … }
static int dsi_pll_get_params(struct dw_mipi_dsi_stm *dsi,
int clkin_khz, int clkout_khz,
int *idf, int *ndiv, int *odf)
{ … }
#define clk_to_dw_mipi_dsi_stm(clk) …
static void dw_mipi_dsi_clk_disable(struct clk_hw *clk)
{ … }
static int dw_mipi_dsi_clk_enable(struct clk_hw *clk)
{ … }
static int dw_mipi_dsi_clk_is_enabled(struct clk_hw *hw)
{ … }
static unsigned long dw_mipi_dsi_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{ … }
static long dw_mipi_dsi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{ … }
static int dw_mipi_dsi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{ … }
static void dw_mipi_dsi_clk_unregister(void *data)
{ … }
static const struct clk_ops dw_mipi_dsi_stm_clk_ops = …;
static struct clk_init_data cdata_init = …;
static int dw_mipi_dsi_clk_register(struct dw_mipi_dsi_stm *dsi,
struct device *dev)
{ … }
static int dw_mipi_dsi_phy_init(void *priv_data)
{ … }
static void dw_mipi_dsi_phy_power_on(void *priv_data)
{ … }
static void dw_mipi_dsi_phy_power_off(void *priv_data)
{ … }
static int
dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
unsigned long mode_flags, u32 lanes, u32 format,
unsigned int *lane_mbps)
{ … }
#define DSI_PHY_DELAY(fp, vp, mbps) …
static int
dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
struct dw_mipi_dsi_dphy_timing *timing)
{ … }
#define CLK_TOLERANCE_HZ …
static enum drm_mode_status
dw_mipi_dsi_stm_mode_valid(void *priv_data,
const struct drm_display_mode *mode,
unsigned long mode_flags, u32 lanes, u32 format)
{ … }
static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_stm_phy_ops = …;
static struct dw_mipi_dsi_plat_data dw_mipi_dsi_stm_plat_data = …;
static const struct of_device_id dw_mipi_dsi_stm_dt_ids[] = …;
MODULE_DEVICE_TABLE(of, dw_mipi_dsi_stm_dt_ids);
static int dw_mipi_dsi_stm_probe(struct platform_device *pdev)
{ … }
static void dw_mipi_dsi_stm_remove(struct platform_device *pdev)
{ … }
static int dw_mipi_dsi_stm_suspend(struct device *dev)
{ … }
static int dw_mipi_dsi_stm_resume(struct device *dev)
{ … }
static const struct dev_pm_ops dw_mipi_dsi_stm_pm_ops = …;
static struct platform_driver dw_mipi_dsi_stm_driver = …;
module_platform_driver(…) …;
MODULE_AUTHOR(…) …;
MODULE_AUTHOR(…) …;
MODULE_DESCRIPTION(…) …;
MODULE_LICENSE(…) …;