// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) STMicroelectronics SA 2017 * * Authors: Philippe Cornu <[email protected]> * Yannick Fertre <[email protected]> * Fabien Dessenne <[email protected]> * Mickael Reulier <[email protected]> */ #include <linux/clk.h> #include <linux/component.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/media-bus-format.h> #include <linux/module.h> #include <linux/of_graph.h> #include <linux/pinctrl/consumer.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/reset.h> #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_blend.h> #include <drm/drm_bridge.h> #include <drm/drm_device.h> #include <drm/drm_edid.h> #include <drm/drm_fb_dma_helper.h> #include <drm/drm_fourcc.h> #include <drm/drm_framebuffer.h> #include <drm/drm_gem_atomic_helper.h> #include <drm/drm_gem_dma_helper.h> #include <drm/drm_of.h> #include <drm/drm_probe_helper.h> #include <drm/drm_simple_kms_helper.h> #include <drm/drm_vblank.h> #include <video/videomode.h> #include "ltdc.h" #define NB_CRTC … #define CRTC_MASK … #define MAX_IRQ … #define HWVER_10200 … #define HWVER_10300 … #define HWVER_20101 … #define HWVER_40100 … /* * The address of some registers depends on the HW version: such registers have * an extra offset specified with layer_ofs. */ #define LAY_OFS_0 … #define LAY_OFS_1 … #define LAY_OFS … /* Global register offsets */ #define LTDC_IDR … #define LTDC_LCR … #define LTDC_SSCR … #define LTDC_BPCR … #define LTDC_AWCR … #define LTDC_TWCR … #define LTDC_GCR … #define LTDC_GC1R … #define LTDC_GC2R … #define LTDC_SRCR … #define LTDC_GACR … #define LTDC_BCCR … #define LTDC_IER … #define LTDC_ISR … #define LTDC_ICR … #define LTDC_LIPCR … #define LTDC_CPSR … #define LTDC_CDSR … #define LTDC_EDCR … #define LTDC_CCRCR … #define LTDC_FUT … /* Layer register offsets */ #define LTDC_L1C0R … #define LTDC_L1C1R … #define LTDC_L1RCR … #define LTDC_L1CR … #define LTDC_L1WHPCR … #define LTDC_L1WVPCR … #define LTDC_L1CKCR … #define LTDC_L1PFCR … #define LTDC_L1CACR … #define LTDC_L1DCCR … #define LTDC_L1BFCR … #define LTDC_L1BLCR … #define LTDC_L1PCR … #define LTDC_L1CFBAR … #define LTDC_L1CFBLR … #define LTDC_L1CFBLNR … #define LTDC_L1AFBA0R … #define LTDC_L1AFBA1R … #define LTDC_L1AFBLR … #define LTDC_L1AFBLNR … #define LTDC_L1CLUTWR … #define LTDC_L1CYR0R … #define LTDC_L1CYR1R … #define LTDC_L1FPF0R … #define LTDC_L1FPF1R … /* Bit definitions */ #define SSCR_VSH … #define SSCR_HSW … #define BPCR_AVBP … #define BPCR_AHBP … #define AWCR_AAH … #define AWCR_AAW … #define TWCR_TOTALH … #define TWCR_TOTALW … #define GCR_LTDCEN … #define GCR_DEN … #define GCR_CRCEN … #define GCR_PCPOL … #define GCR_DEPOL … #define GCR_VSPOL … #define GCR_HSPOL … #define GC1R_WBCH … #define GC1R_WGCH … #define GC1R_WRCH … #define GC1R_PBEN … #define GC1R_DT … #define GC1R_GCT … #define GC1R_SHREN … #define GC1R_BCP … #define GC1R_BBEN … #define GC1R_LNIP … #define GC1R_TP … #define GC1R_IPP … #define GC1R_SPP … #define GC1R_DWP … #define GC1R_STREN … #define GC1R_BMEN … #define GC2R_EDCA … #define GC2R_STSAEN … #define GC2R_DVAEN … #define GC2R_DPAEN … #define GC2R_BW … #define GC2R_EDCEN … #define SRCR_IMR … #define SRCR_VBR … #define BCCR_BCBLACK … #define BCCR_BCBLUE … #define BCCR_BCGREEN … #define BCCR_BCRED … #define BCCR_BCWHITE … #define IER_LIE … #define IER_FUWIE … #define IER_TERRIE … #define IER_RRIE … #define IER_FUEIE … #define IER_CRCIE … #define CPSR_CYPOS … #define ISR_LIF … #define ISR_FUWIF … #define ISR_TERRIF … #define ISR_RRIF … #define ISR_FUEIF … #define ISR_CRCIF … #define EDCR_OCYEN … #define EDCR_OCYSEL … #define EDCR_OCYCO … #define LXCR_LEN … #define LXCR_COLKEN … #define LXCR_CLUTEN … #define LXCR_HMEN … #define LXWHPCR_WHSTPOS … #define LXWHPCR_WHSPPOS … #define LXWVPCR_WVSTPOS … #define LXWVPCR_WVSPPOS … #define LXPFCR_PF … #define PF_FLEXIBLE … #define LXCACR_CONSTA … #define LXBFCR_BF2 … #define LXBFCR_BF1 … #define LXBFCR_BOR … #define LXCFBLR_CFBLL … #define LXCFBLR_CFBP … #define LXCFBLNR_CFBLN … #define LXCR_C1R_YIA … #define LXCR_C1R_YSPA … #define LXCR_C1R_YFPA … #define LXCR_C1R_SCA … #define LxPCR_YREN … #define LxPCR_OF … #define LxPCR_CBF … #define LxPCR_YF … #define LxPCR_YCM … #define YCM_I … #define YCM_SP … #define YCM_FP … #define LxPCR_YCEN … #define LXRCR_IMR … #define LXRCR_VBR … #define LXRCR_GRMSK … #define CLUT_SIZE … #define CONSTA_MAX … #define BF1_PAXCA … #define BF1_CA … #define BF2_1PAXCA … #define BF2_1CA … #define NB_PF … #define FUT_DFT … /* * Skip the first value and the second in case CRC was enabled during * the thread irq. This is to be sure CRC value is relevant for the * frame. */ #define CRC_SKIP_FRAMES … enum ltdc_pix_fmt { … }; /* The index gives the encoding of the pixel format for an HW version */ static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = …; static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = …; static const enum ltdc_pix_fmt ltdc_pix_fmt_a2[NB_PF] = …; static const u32 ltdc_drm_fmt_a0[] = …; static const u32 ltdc_drm_fmt_a1[] = …; static const u32 ltdc_drm_fmt_a2[] = …; static const u32 ltdc_drm_fmt_ycbcr_cp[] = …; static const u32 ltdc_drm_fmt_ycbcr_sp[] = …; static const u32 ltdc_drm_fmt_ycbcr_fp[] = …; /* Layer register offsets */ static const u32 ltdc_layer_regs_a0[] = …; static const u32 ltdc_layer_regs_a1[] = …; static const u32 ltdc_layer_regs_a2[] = …; static const u64 ltdc_format_modifiers[] = …; static const struct regmap_config stm32_ltdc_regmap_cfg = …; static const u32 ltdc_ycbcr2rgb_coeffs[DRM_COLOR_ENCODING_MAX][DRM_COLOR_RANGE_MAX][2] = …; static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc) { … } static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane) { … } static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc) { … } static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt) { … } static inline u32 ltdc_set_flexible_pixel_format(struct drm_plane *plane, enum ltdc_pix_fmt pix_fmt) { … } /* * All non-alpha color formats derived from native alpha color formats are * either characterized by a FourCC format code */ static inline u32 is_xrgb(u32 drm) { … } static inline void ltdc_set_ycbcr_config(struct drm_plane *plane, u32 drm_pix_fmt) { … } static inline void ltdc_set_ycbcr_coeffs(struct drm_plane *plane) { … } static inline void ltdc_irq_crc_handle(struct ltdc_device *ldev, struct drm_crtc *crtc) { … } static irqreturn_t ltdc_irq_thread(int irq, void *arg) { … } static irqreturn_t ltdc_irq(int irq, void *arg) { … } /* * DRM_CRTC */ static void ltdc_crtc_update_clut(struct drm_crtc *crtc) { … } static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state) { … } static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state) { … } #define CLK_TOLERANCE_HZ … static enum drm_mode_status ltdc_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) { … } static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { … } static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) { … } static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state) { … } static bool ltdc_crtc_get_scanout_position(struct drm_crtc *crtc, bool in_vblank_irq, int *vpos, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode) { … } static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = …; static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc) { … } static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc) { … } static int ltdc_crtc_set_crc_source(struct drm_crtc *crtc, const char *source) { … } static int ltdc_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source, size_t *values_cnt) { … } static void ltdc_crtc_atomic_print_state(struct drm_printer *p, const struct drm_crtc_state *state) { … } static const struct drm_crtc_funcs ltdc_crtc_funcs = …; static const struct drm_crtc_funcs ltdc_crtc_with_crc_support_funcs = …; /* * DRM_PLANE */ static int ltdc_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) { … } static void ltdc_plane_atomic_update(struct drm_plane *plane, struct drm_atomic_state *state) { … } static void ltdc_plane_atomic_disable(struct drm_plane *plane, struct drm_atomic_state *state) { … } static void ltdc_plane_atomic_print_state(struct drm_printer *p, const struct drm_plane_state *state) { … } static const struct drm_plane_funcs ltdc_plane_funcs = …; static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = …; static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, enum drm_plane_type type, int index) { … } static void ltdc_plane_destroy_all(struct drm_device *ddev) { … } static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) { … } static void ltdc_encoder_disable(struct drm_encoder *encoder) { … } static void ltdc_encoder_enable(struct drm_encoder *encoder) { … } static void ltdc_encoder_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { … } static const struct drm_encoder_helper_funcs ltdc_encoder_helper_funcs = …; static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge) { … } static int ltdc_get_caps(struct drm_device *ddev) { … } void ltdc_suspend(struct drm_device *ddev) { … } int ltdc_resume(struct drm_device *ddev) { … } int ltdc_load(struct drm_device *ddev) { … } void ltdc_unload(struct drm_device *ddev) { … } MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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