/* SPDX-License-Identifier: GPL-2.0-only */ /* * HDMI header definition for OMAP4 HDMI core IP * * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef _HDMI4_CORE_H_ #define _HDMI4_CORE_H_ #include "hdmi.h" /* OMAP4 HDMI IP Core System */ #define HDMI_CORE_SYS_VND_IDL … #define HDMI_CORE_SYS_DEV_IDL … #define HDMI_CORE_SYS_DEV_IDH … #define HDMI_CORE_SYS_DEV_REV … #define HDMI_CORE_SYS_SRST … #define HDMI_CORE_SYS_SYS_CTRL1 … #define HDMI_CORE_SYS_SYS_STAT … #define HDMI_CORE_SYS_SYS_CTRL3 … #define HDMI_CORE_SYS_DCTL … #define HDMI_CORE_SYS_DE_DLY … #define HDMI_CORE_SYS_DE_CTRL … #define HDMI_CORE_SYS_DE_TOP … #define HDMI_CORE_SYS_DE_CNTL … #define HDMI_CORE_SYS_DE_CNTH … #define HDMI_CORE_SYS_DE_LINL … #define HDMI_CORE_SYS_DE_LINH_1 … #define HDMI_CORE_SYS_HRES_L … #define HDMI_CORE_SYS_HRES_H … #define HDMI_CORE_SYS_VRES_L … #define HDMI_CORE_SYS_VRES_H … #define HDMI_CORE_SYS_IADJUST … #define HDMI_CORE_SYS_POLDETECT … #define HDMI_CORE_SYS_HWIDTH1 … #define HDMI_CORE_SYS_HWIDTH2 … #define HDMI_CORE_SYS_VWIDTH … #define HDMI_CORE_SYS_VID_CTRL … #define HDMI_CORE_SYS_VID_ACEN … #define HDMI_CORE_SYS_VID_MODE … #define HDMI_CORE_SYS_VID_BLANK1 … #define HDMI_CORE_SYS_VID_BLANK2 … #define HDMI_CORE_SYS_VID_BLANK3 … #define HDMI_CORE_SYS_DC_HEADER … #define HDMI_CORE_SYS_VID_DITHER … #define HDMI_CORE_SYS_RGB2XVYCC_CT … #define HDMI_CORE_SYS_R2Y_COEFF_LOW … #define HDMI_CORE_SYS_R2Y_COEFF_UP … #define HDMI_CORE_SYS_G2Y_COEFF_LOW … #define HDMI_CORE_SYS_G2Y_COEFF_UP … #define HDMI_CORE_SYS_B2Y_COEFF_LOW … #define HDMI_CORE_SYS_B2Y_COEFF_UP … #define HDMI_CORE_SYS_R2CB_COEFF_LOW … #define HDMI_CORE_SYS_R2CB_COEFF_UP … #define HDMI_CORE_SYS_G2CB_COEFF_LOW … #define HDMI_CORE_SYS_G2CB_COEFF_UP … #define HDMI_CORE_SYS_B2CB_COEFF_LOW … #define HDMI_CORE_SYS_B2CB_COEFF_UP … #define HDMI_CORE_SYS_R2CR_COEFF_LOW … #define HDMI_CORE_SYS_R2CR_COEFF_UP … #define HDMI_CORE_SYS_G2CR_COEFF_LOW … #define HDMI_CORE_SYS_G2CR_COEFF_UP … #define HDMI_CORE_SYS_B2CR_COEFF_LOW … #define HDMI_CORE_SYS_B2CR_COEFF_UP … #define HDMI_CORE_SYS_RGB_OFFSET_LOW … #define HDMI_CORE_SYS_RGB_OFFSET_UP … #define HDMI_CORE_SYS_Y_OFFSET_LOW … #define HDMI_CORE_SYS_Y_OFFSET_UP … #define HDMI_CORE_SYS_CBCR_OFFSET_LOW … #define HDMI_CORE_SYS_CBCR_OFFSET_UP … #define HDMI_CORE_SYS_INTR_STATE … #define HDMI_CORE_SYS_INTR1 … #define HDMI_CORE_SYS_INTR2 … #define HDMI_CORE_SYS_INTR3 … #define HDMI_CORE_SYS_INTR4 … #define HDMI_CORE_SYS_INTR_UNMASK1 … #define HDMI_CORE_SYS_INTR_UNMASK2 … #define HDMI_CORE_SYS_INTR_UNMASK3 … #define HDMI_CORE_SYS_INTR_UNMASK4 … #define HDMI_CORE_SYS_INTR_CTRL … #define HDMI_CORE_SYS_TMDS_CTRL … /* value definitions for HDMI_CORE_SYS_SYS_CTRL1 fields */ #define HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC … #define HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC … #define HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS … #define HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE … /* HDMI DDC E-DID */ #define HDMI_CORE_DDC_ADDR … #define HDMI_CORE_DDC_SEGM … #define HDMI_CORE_DDC_OFFSET … #define HDMI_CORE_DDC_COUNT1 … #define HDMI_CORE_DDC_COUNT2 … #define HDMI_CORE_DDC_STATUS … #define HDMI_CORE_DDC_CMD … #define HDMI_CORE_DDC_DATA … /* HDMI IP Core Audio Video */ #define HDMI_CORE_AV_ACR_CTRL … #define HDMI_CORE_AV_FREQ_SVAL … #define HDMI_CORE_AV_N_SVAL1 … #define HDMI_CORE_AV_N_SVAL2 … #define HDMI_CORE_AV_N_SVAL3 … #define HDMI_CORE_AV_CTS_SVAL1 … #define HDMI_CORE_AV_CTS_SVAL2 … #define HDMI_CORE_AV_CTS_SVAL3 … #define HDMI_CORE_AV_CTS_HVAL1 … #define HDMI_CORE_AV_CTS_HVAL2 … #define HDMI_CORE_AV_CTS_HVAL3 … #define HDMI_CORE_AV_AUD_MODE … #define HDMI_CORE_AV_SPDIF_CTRL … #define HDMI_CORE_AV_HW_SPDIF_FS … #define HDMI_CORE_AV_SWAP_I2S … #define HDMI_CORE_AV_SPDIF_ERTH … #define HDMI_CORE_AV_I2S_IN_MAP … #define HDMI_CORE_AV_I2S_IN_CTRL … #define HDMI_CORE_AV_I2S_CHST0 … #define HDMI_CORE_AV_I2S_CHST1 … #define HDMI_CORE_AV_I2S_CHST2 … #define HDMI_CORE_AV_I2S_CHST4 … #define HDMI_CORE_AV_I2S_CHST5 … #define HDMI_CORE_AV_ASRC … #define HDMI_CORE_AV_I2S_IN_LEN … #define HDMI_CORE_AV_HDMI_CTRL … #define HDMI_CORE_AV_AUDO_TXSTAT … #define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 … #define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 … #define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 … #define HDMI_CORE_AV_TEST_TXCTRL … #define HDMI_CORE_AV_DPD … #define HDMI_CORE_AV_PB_CTRL1 … #define HDMI_CORE_AV_PB_CTRL2 … #define HDMI_CORE_AV_AVI_BASE … #define HDMI_CORE_AV_AVI_TYPE … #define HDMI_CORE_AV_AVI_VERS … #define HDMI_CORE_AV_AVI_LEN … #define HDMI_CORE_AV_AVI_CHSUM … #define HDMI_CORE_AV_AVI_DBYTE(n) … #define HDMI_CORE_AV_SPD_TYPE … #define HDMI_CORE_AV_SPD_VERS … #define HDMI_CORE_AV_SPD_LEN … #define HDMI_CORE_AV_SPD_CHSUM … #define HDMI_CORE_AV_SPD_DBYTE(n) … #define HDMI_CORE_AV_AUDIO_TYPE … #define HDMI_CORE_AV_AUDIO_VERS … #define HDMI_CORE_AV_AUDIO_LEN … #define HDMI_CORE_AV_AUDIO_CHSUM … #define HDMI_CORE_AV_AUD_DBYTE(n) … #define HDMI_CORE_AV_MPEG_TYPE … #define HDMI_CORE_AV_MPEG_VERS … #define HDMI_CORE_AV_MPEG_LEN … #define HDMI_CORE_AV_MPEG_CHSUM … #define HDMI_CORE_AV_MPEG_DBYTE(n) … #define HDMI_CORE_AV_GEN_DBYTE(n) … #define HDMI_CORE_AV_CP_BYTE1 … #define HDMI_CORE_AV_GEN2_DBYTE(n) … #define HDMI_CORE_AV_CEC_ADDR_ID … #define HDMI_CORE_AV_SPD_DBYTE_ELSIZE … #define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE … #define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE … #define HDMI_CORE_AV_GEN_DBYTE_ELSIZE … #define HDMI_CORE_AV_AVI_DBYTE_NELEMS … #define HDMI_CORE_AV_SPD_DBYTE_NELEMS … #define HDMI_CORE_AV_AUD_DBYTE_NELEMS … #define HDMI_CORE_AV_MPEG_DBYTE_NELEMS … #define HDMI_CORE_AV_GEN_DBYTE_NELEMS … #define HDMI_CORE_AV_GEN2_DBYTE_NELEMS … enum hdmi_core_inputbus_width { … }; enum hdmi_core_dither_trunc { … }; enum hdmi_core_deepcolor_ed { … }; enum hdmi_core_packet_mode { … }; enum hdmi_core_tclkselclkmult { … }; enum hdmi_core_packet_ctrl { … }; enum hdmi_audio_i2s_config { … }; struct hdmi_core_video_config { … }; struct hdmi_core_packet_enable_repeat { … }; int hdmi4_core_ddc_init(struct hdmi_core_data *core); int hdmi4_core_ddc_read(void *data, u8 *buf, unsigned int block, size_t len); void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, struct hdmi_config *cfg); void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s); int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core); int hdmi4_core_enable(struct hdmi_core_data *core); void hdmi4_core_disable(struct hdmi_core_data *core); void hdmi4_core_powerdown_disable(struct hdmi_core_data *core); int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp); void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp); int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, struct omap_dss_audio *audio, u32 pclk); #endif
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