linux/drivers/gpu/drm/omapdrm/dss/omapdss.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
 * Author: Tomi Valkeinen <[email protected]>
 */

#ifndef __OMAP_DRM_DSS_H
#define __OMAP_DRM_DSS_H

#include <drm/drm_color_mgmt.h>
#include <drm/drm_crtc.h>
#include <drm/drm_mode.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/platform_data/omapdss.h>
#include <video/videomode.h>

#define DISPC_IRQ_FRAMEDONE …
#define DISPC_IRQ_VSYNC …
#define DISPC_IRQ_EVSYNC_EVEN …
#define DISPC_IRQ_EVSYNC_ODD …
#define DISPC_IRQ_ACBIAS_COUNT_STAT …
#define DISPC_IRQ_PROG_LINE_NUM …
#define DISPC_IRQ_GFX_FIFO_UNDERFLOW …
#define DISPC_IRQ_GFX_END_WIN …
#define DISPC_IRQ_PAL_GAMMA_MASK …
#define DISPC_IRQ_OCP_ERR …
#define DISPC_IRQ_VID1_FIFO_UNDERFLOW …
#define DISPC_IRQ_VID1_END_WIN …
#define DISPC_IRQ_VID2_FIFO_UNDERFLOW …
#define DISPC_IRQ_VID2_END_WIN …
#define DISPC_IRQ_SYNC_LOST …
#define DISPC_IRQ_SYNC_LOST_DIGIT …
#define DISPC_IRQ_WAKEUP …
#define DISPC_IRQ_SYNC_LOST2 …
#define DISPC_IRQ_VSYNC2 …
#define DISPC_IRQ_VID3_END_WIN …
#define DISPC_IRQ_VID3_FIFO_UNDERFLOW …
#define DISPC_IRQ_ACBIAS_COUNT_STAT2 …
#define DISPC_IRQ_FRAMEDONE2 …
#define DISPC_IRQ_FRAMEDONEWB …
#define DISPC_IRQ_FRAMEDONETV …
#define DISPC_IRQ_WBBUFFEROVERFLOW …
#define DISPC_IRQ_WBUNCOMPLETEERROR …
#define DISPC_IRQ_SYNC_LOST3 …
#define DISPC_IRQ_VSYNC3 …
#define DISPC_IRQ_ACBIAS_COUNT_STAT3 …
#define DISPC_IRQ_FRAMEDONE3 …

struct dispc_device;
struct drm_connector;
struct dss_device;
struct dss_lcd_mgr_config;
struct hdmi_avi_infoframe;
struct omap_drm_private;
struct omap_dss_device;
struct snd_aes_iec958;
struct snd_cea_861_aud_if;

enum omap_display_type { … };

enum omap_plane_id { … };

enum omap_channel { … };

enum omap_color_mode { … };

enum omap_dss_load_mode { … };

enum omap_dss_trans_key_type { … };

enum omap_dss_signal_level { … };

enum omap_dss_signal_edge { … };

enum omap_dss_venc_type { … };

enum omap_dss_rotation_type { … };

enum omap_overlay_caps { … };

enum omap_dss_output_id { … };

struct omap_dss_cpr_coefs { … };

struct omap_overlay_info { … };

struct omap_overlay_manager_info { … };

struct omap_dss_writeback_info { … };

struct omapdss_dsi_ops { … };

struct omap_dss_device { … };

struct dss_pdata { … };

void omapdss_device_register(struct omap_dss_device *dssdev);
void omapdss_device_unregister(struct omap_dss_device *dssdev);
struct omap_dss_device *omapdss_device_get(struct omap_dss_device *dssdev);
void omapdss_device_put(struct omap_dss_device *dssdev);
struct omap_dss_device *omapdss_find_device_by_node(struct device_node *node);
int omapdss_device_connect(struct dss_device *dss,
			   struct omap_dss_device *src,
			   struct omap_dss_device *dst);
void omapdss_device_disconnect(struct omap_dss_device *src,
			       struct omap_dss_device *dst);

int omap_dss_get_num_overlay_managers(void);

int omap_dss_get_num_overlays(void);

#define for_each_dss_output(d) …
struct omap_dss_device *omapdss_device_next_output(struct omap_dss_device *from);
int omapdss_device_init_output(struct omap_dss_device *out,
			       struct drm_bridge *local_bridge);
void omapdss_device_cleanup_output(struct omap_dss_device *out);

omap_dispc_isr_t;
int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);

int omapdss_compat_init(void);
void omapdss_compat_uninit(void);

enum dss_writeback_channel { … };

void omap_crtc_dss_start_update(struct omap_drm_private *priv,
				       enum omap_channel channel);
void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable);
int omap_crtc_dss_enable(struct omap_drm_private *priv, enum omap_channel channel);
void omap_crtc_dss_disable(struct omap_drm_private *priv, enum omap_channel channel);
void omap_crtc_dss_set_timings(struct omap_drm_private *priv,
		enum omap_channel channel,
		const struct videomode *vm);
void omap_crtc_dss_set_lcd_config(struct omap_drm_private *priv,
		enum omap_channel channel,
		const struct dss_lcd_mgr_config *config);
int omap_crtc_dss_register_framedone(
		struct omap_drm_private *priv, enum omap_channel channel,
		void (*handler)(void *), void *data);
void omap_crtc_dss_unregister_framedone(
		struct omap_drm_private *priv, enum omap_channel channel,
		void (*handler)(void *), void *data);

void dss_mgr_set_timings(struct omap_dss_device *dssdev,
		const struct videomode *vm);
void dss_mgr_set_lcd_config(struct omap_dss_device *dssdev,
		const struct dss_lcd_mgr_config *config);
int dss_mgr_enable(struct omap_dss_device *dssdev);
void dss_mgr_disable(struct omap_dss_device *dssdev);
void dss_mgr_start_update(struct omap_dss_device *dssdev);
int dss_mgr_register_framedone_handler(struct omap_dss_device *dssdev,
		void (*handler)(void *), void *data);
void dss_mgr_unregister_framedone_handler(struct omap_dss_device *dssdev,
		void (*handler)(void *), void *data);

struct dispc_device *dispc_get_dispc(struct dss_device *dss);

bool omapdss_stack_is_ready(void);
void omapdss_gather_components(struct device *dev);

int omap_dss_init(void);
void omap_dss_exit(void);

#endif /* __OMAP_DRM_DSS_H */