/* SPDX-License-Identifier: GPL-2.0-only */ /* * HDMI driver definition for TI OMAP5 processors. * * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef _HDMI5_CORE_H_ #define _HDMI5_CORE_H_ #include "hdmi.h" /* HDMI IP Core System */ /* HDMI Identification */ #define HDMI_CORE_DESIGN_ID … #define HDMI_CORE_REVISION_ID … #define HDMI_CORE_PRODUCT_ID0 … #define HDMI_CORE_PRODUCT_ID1 … #define HDMI_CORE_CONFIG0_ID … #define HDMI_CORE_CONFIG1_ID … #define HDMI_CORE_CONFIG2_ID … #define HDMI_CORE_CONFIG3_ID … /* HDMI Interrupt */ #define HDMI_CORE_IH_FC_STAT0 … #define HDMI_CORE_IH_FC_STAT1 … #define HDMI_CORE_IH_FC_STAT2 … #define HDMI_CORE_IH_AS_STAT0 … #define HDMI_CORE_IH_PHY_STAT0 … #define HDMI_CORE_IH_I2CM_STAT0 … #define HDMI_CORE_IH_CEC_STAT0 … #define HDMI_CORE_IH_VP_STAT0 … #define HDMI_CORE_IH_I2CMPHY_STAT0 … #define HDMI_CORE_IH_MUTE … /* HDMI Video Sampler */ #define HDMI_CORE_TX_INVID0 … #define HDMI_CORE_TX_INSTUFFING … #define HDMI_CORE_TX_RGYDATA0 … #define HDMI_CORE_TX_RGYDATA1 … #define HDMI_CORE_TX_RCRDATA0 … #define HDMI_CORE_TX_RCRDATA1 … #define HDMI_CORE_TX_BCBDATA0 … #define HDMI_CORE_TX_BCBDATA1 … /* HDMI Video Packetizer */ #define HDMI_CORE_VP_STATUS … #define HDMI_CORE_VP_PR_CD … #define HDMI_CORE_VP_STUFF … #define HDMI_CORE_VP_REMAP … #define HDMI_CORE_VP_CONF … #define HDMI_CORE_VP_STAT … #define HDMI_CORE_VP_INT … #define HDMI_CORE_VP_MASK … #define HDMI_CORE_VP_POL … /* Frame Composer */ #define HDMI_CORE_FC_INVIDCONF … #define HDMI_CORE_FC_INHACTIV0 … #define HDMI_CORE_FC_INHACTIV1 … #define HDMI_CORE_FC_INHBLANK0 … #define HDMI_CORE_FC_INHBLANK1 … #define HDMI_CORE_FC_INVACTIV0 … #define HDMI_CORE_FC_INVACTIV1 … #define HDMI_CORE_FC_INVBLANK … #define HDMI_CORE_FC_HSYNCINDELAY0 … #define HDMI_CORE_FC_HSYNCINDELAY1 … #define HDMI_CORE_FC_HSYNCINWIDTH0 … #define HDMI_CORE_FC_HSYNCINWIDTH1 … #define HDMI_CORE_FC_VSYNCINDELAY … #define HDMI_CORE_FC_VSYNCINWIDTH … #define HDMI_CORE_FC_INFREQ0 … #define HDMI_CORE_FC_INFREQ1 … #define HDMI_CORE_FC_INFREQ2 … #define HDMI_CORE_FC_CTRLDUR … #define HDMI_CORE_FC_EXCTRLDUR … #define HDMI_CORE_FC_EXCTRLSPAC … #define HDMI_CORE_FC_CH0PREAM … #define HDMI_CORE_FC_CH1PREAM … #define HDMI_CORE_FC_CH2PREAM … #define HDMI_CORE_FC_AVICONF3 … #define HDMI_CORE_FC_GCP … #define HDMI_CORE_FC_AVICONF0 … #define HDMI_CORE_FC_AVICONF1 … #define HDMI_CORE_FC_AVICONF2 … #define HDMI_CORE_FC_AVIVID … #define HDMI_CORE_FC_AVIETB0 … #define HDMI_CORE_FC_AVIETB1 … #define HDMI_CORE_FC_AVISBB0 … #define HDMI_CORE_FC_AVISBB1 … #define HDMI_CORE_FC_AVIELB0 … #define HDMI_CORE_FC_AVIELB1 … #define HDMI_CORE_FC_AVISRB0 … #define HDMI_CORE_FC_AVISRB1 … #define HDMI_CORE_FC_AUDICONF0 … #define HDMI_CORE_FC_AUDICONF1 … #define HDMI_CORE_FC_AUDICONF2 … #define HDMI_CORE_FC_AUDICONF3 … #define HDMI_CORE_FC_VSDIEEEID0 … #define HDMI_CORE_FC_VSDSIZE … #define HDMI_CORE_FC_VSDIEEEID1 … #define HDMI_CORE_FC_VSDIEEEID2 … #define HDMI_CORE_FC_VSDPAYLOAD(n) … #define HDMI_CORE_FC_SPDVENDORNAME(n) … #define HDMI_CORE_FC_SPDPRODUCTNAME(n) … #define HDMI_CORE_FC_SPDDEVICEINF … #define HDMI_CORE_FC_AUDSCONF … #define HDMI_CORE_FC_AUDSSTAT … #define HDMI_CORE_FC_AUDSV … #define HDMI_CORE_FC_AUDSU … #define HDMI_CORE_FC_AUDSCHNLS(n) … #define HDMI_CORE_FC_CTRLQHIGH … #define HDMI_CORE_FC_CTRLQLOW … #define HDMI_CORE_FC_ACP0 … #define HDMI_CORE_FC_ACP(n) … #define HDMI_CORE_FC_ISCR1_0 … #define HDMI_CORE_FC_ISCR1(n) … #define HDMI_CORE_FC_ISCR2(n) … #define HDMI_CORE_FC_DATAUTO0 … #define HDMI_CORE_FC_DATAUTO1 … #define HDMI_CORE_FC_DATAUTO2 … #define HDMI_CORE_FC_DATMAN … #define HDMI_CORE_FC_DATAUTO3 … #define HDMI_CORE_FC_RDRB(n) … #define HDMI_CORE_FC_STAT0 … #define HDMI_CORE_FC_INT0 … #define HDMI_CORE_FC_MASK0 … #define HDMI_CORE_FC_POL0 … #define HDMI_CORE_FC_STAT1 … #define HDMI_CORE_FC_INT1 … #define HDMI_CORE_FC_MASK1 … #define HDMI_CORE_FC_POL1 … #define HDMI_CORE_FC_STAT2 … #define HDMI_CORE_FC_INT2 … #define HDMI_CORE_FC_MASK2 … #define HDMI_CORE_FC_POL2 … #define HDMI_CORE_FC_PRCONF … #define HDMI_CORE_FC_GMD_STAT … #define HDMI_CORE_FC_GMD_EN … #define HDMI_CORE_FC_GMD_UP … #define HDMI_CORE_FC_GMD_CONF … #define HDMI_CORE_FC_GMD_HB … #define HDMI_CORE_FC_GMD_PB(n) … #define HDMI_CORE_FC_DBGFORCE … #define HDMI_CORE_FC_DBGAUD0CH0 … #define HDMI_CORE_FC_DBGAUD1CH0 … #define HDMI_CORE_FC_DBGAUD2CH0 … #define HDMI_CORE_FC_DBGAUD0CH1 … #define HDMI_CORE_FC_DBGAUD1CH1 … #define HDMI_CORE_FC_DBGAUD2CH1 … #define HDMI_CORE_FC_DBGAUD0CH2 … #define HDMI_CORE_FC_DBGAUD1CH2 … #define HDMI_CORE_FC_DBGAUD2CH2 … #define HDMI_CORE_FC_DBGAUD0CH3 … #define HDMI_CORE_FC_DBGAUD1CH3 … #define HDMI_CORE_FC_DBGAUD2CH3 … #define HDMI_CORE_FC_DBGAUD0CH4 … #define HDMI_CORE_FC_DBGAUD1CH4 … #define HDMI_CORE_FC_DBGAUD2CH4 … #define HDMI_CORE_FC_DBGAUD0CH5 … #define HDMI_CORE_FC_DBGAUD1CH5 … #define HDMI_CORE_FC_DBGAUD2CH5 … #define HDMI_CORE_FC_DBGAUD0CH6 … #define HDMI_CORE_FC_DBGAUD1CH6 … #define HDMI_CORE_FC_DBGAUD2CH6 … #define HDMI_CORE_FC_DBGAUD0CH7 … #define HDMI_CORE_FC_DBGAUD1CH7 … #define HDMI_CORE_FC_DBGAUD2CH7 … #define HDMI_CORE_FC_DBGTMDS0 … #define HDMI_CORE_FC_DBGTMDS1 … #define HDMI_CORE_FC_DBGTMDS2 … #define HDMI_CORE_PHY_MASK0 … #define HDMI_CORE_PHY_I2CM_INT_ADDR … #define HDMI_CORE_PHY_I2CM_CTLINT_ADDR … /* HDMI Audio */ #define HDMI_CORE_AUD_CONF0 … #define HDMI_CORE_AUD_CONF1 … #define HDMI_CORE_AUD_INT … #define HDMI_CORE_AUD_N1 … #define HDMI_CORE_AUD_N2 … #define HDMI_CORE_AUD_N3 … #define HDMI_CORE_AUD_CTS1 … #define HDMI_CORE_AUD_CTS2 … #define HDMI_CORE_AUD_CTS3 … #define HDMI_CORE_AUD_INCLKFS … #define HDMI_CORE_AUD_CC08 … #define HDMI_CORE_AUD_GP_CONF0 … #define HDMI_CORE_AUD_GP_CONF1 … #define HDMI_CORE_AUD_GP_CONF2 … #define HDMI_CORE_AUD_D010 … #define HDMI_CORE_AUD_GP_STAT … #define HDMI_CORE_AUD_GP_INT … #define HDMI_CORE_AUD_GP_POL … #define HDMI_CORE_AUD_GP_MASK … /* HDMI Main Controller */ #define HDMI_CORE_MC_CLKDIS … #define HDMI_CORE_MC_SWRSTZREQ … #define HDMI_CORE_MC_FLOWCTRL … #define HDMI_CORE_MC_PHYRSTZ … #define HDMI_CORE_MC_LOCKONCLOCK … /* HDMI COLOR SPACE CONVERTER */ #define HDMI_CORE_CSC_CFG … #define HDMI_CORE_CSC_SCALE … #define HDMI_CORE_CSC_COEF_A1_MSB … #define HDMI_CORE_CSC_COEF_A1_LSB … #define HDMI_CORE_CSC_COEF_A2_MSB … #define HDMI_CORE_CSC_COEF_A2_LSB … #define HDMI_CORE_CSC_COEF_A3_MSB … #define HDMI_CORE_CSC_COEF_A3_LSB … #define HDMI_CORE_CSC_COEF_A4_MSB … #define HDMI_CORE_CSC_COEF_A4_LSB … #define HDMI_CORE_CSC_COEF_B1_MSB … #define HDMI_CORE_CSC_COEF_B1_LSB … #define HDMI_CORE_CSC_COEF_B2_MSB … #define HDMI_CORE_CSC_COEF_B2_LSB … #define HDMI_CORE_CSC_COEF_B3_MSB … #define HDMI_CORE_CSC_COEF_B3_LSB … #define HDMI_CORE_CSC_COEF_B4_MSB … #define HDMI_CORE_CSC_COEF_B4_LSB … #define HDMI_CORE_CSC_COEF_C1_MSB … #define HDMI_CORE_CSC_COEF_C1_LSB … #define HDMI_CORE_CSC_COEF_C2_MSB … #define HDMI_CORE_CSC_COEF_C2_LSB … #define HDMI_CORE_CSC_COEF_C3_MSB … #define HDMI_CORE_CSC_COEF_C3_LSB … #define HDMI_CORE_CSC_COEF_C4_MSB … #define HDMI_CORE_CSC_COEF_C4_LSB … /* HDMI HDCP */ #define HDMI_CORE_HDCP_MASK … /* HDMI CEC */ #define HDMI_CORE_CEC_MASK … /* HDMI I2C Master */ #define HDMI_CORE_I2CM_SLAVE … #define HDMI_CORE_I2CM_ADDRESS … #define HDMI_CORE_I2CM_DATAO … #define HDMI_CORE_I2CM_DATAI … #define HDMI_CORE_I2CM_OPERATION … #define HDMI_CORE_I2CM_INT … #define HDMI_CORE_I2CM_CTLINT … #define HDMI_CORE_I2CM_DIV … #define HDMI_CORE_I2CM_SEGADDR … #define HDMI_CORE_I2CM_SOFTRSTZ … #define HDMI_CORE_I2CM_SEGPTR … #define HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR … #define HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR … #define HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR … #define HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR … #define HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR … #define HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR … #define HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR … #define HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR … #define HDMI_CORE_I2CM_SDA_HOLD_ADDR … enum hdmi_core_packet_mode { … }; struct hdmi_core_vid_config { … }; struct csc_table { … }; void hdmi5_core_ddc_init(struct hdmi_core_data *core); int hdmi5_core_ddc_read(void *data, u8 *buf, unsigned int block, size_t len); void hdmi5_core_ddc_uninit(struct hdmi_core_data *core); void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s); int hdmi5_core_handle_irqs(struct hdmi_core_data *core); void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, struct hdmi_config *cfg); int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core); int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, struct omap_dss_audio *audio, u32 pclk); #endif
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