/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ * Author: Archit Taneja <[email protected]> */ #ifndef __OMAP2_DISPC_REG_H #define __OMAP2_DISPC_REG_H /* DISPC common registers */ #define DISPC_REVISION … #define DISPC_SYSCONFIG … #define DISPC_SYSSTATUS … #define DISPC_IRQSTATUS … #define DISPC_IRQENABLE … #define DISPC_CONTROL … #define DISPC_CONFIG … #define DISPC_CAPABLE … #define DISPC_LINE_STATUS … #define DISPC_LINE_NUMBER … #define DISPC_GLOBAL_ALPHA … #define DISPC_CONTROL2 … #define DISPC_CONFIG2 … #define DISPC_DIVISOR … #define DISPC_GLOBAL_BUFFER … #define DISPC_CONTROL3 … #define DISPC_CONFIG3 … #define DISPC_MSTANDBY_CTRL … #define DISPC_GLOBAL_MFLAG_ATTRIBUTE … #define DISPC_GAMMA_TABLE0 … #define DISPC_GAMMA_TABLE1 … #define DISPC_GAMMA_TABLE2 … #define DISPC_GAMMA_TABLE3 … /* DISPC overlay registers */ #define DISPC_OVL_BA0(n) … #define DISPC_OVL_BA1(n) … #define DISPC_OVL_BA0_UV(n) … #define DISPC_OVL_BA1_UV(n) … #define DISPC_OVL_POSITION(n) … #define DISPC_OVL_SIZE(n) … #define DISPC_OVL_ATTRIBUTES(n) … #define DISPC_OVL_ATTRIBUTES2(n) … #define DISPC_OVL_FIFO_THRESHOLD(n) … #define DISPC_OVL_FIFO_SIZE_STATUS(n) … #define DISPC_OVL_ROW_INC(n) … #define DISPC_OVL_PIXEL_INC(n) … #define DISPC_OVL_WINDOW_SKIP(n) … #define DISPC_OVL_TABLE_BA(n) … #define DISPC_OVL_FIR(n) … #define DISPC_OVL_FIR2(n) … #define DISPC_OVL_PICTURE_SIZE(n) … #define DISPC_OVL_ACCU0(n) … #define DISPC_OVL_ACCU1(n) … #define DISPC_OVL_ACCU2_0(n) … #define DISPC_OVL_ACCU2_1(n) … #define DISPC_OVL_FIR_COEF_H(n, i) … #define DISPC_OVL_FIR_COEF_HV(n, i) … #define DISPC_OVL_FIR_COEF_H2(n, i) … #define DISPC_OVL_FIR_COEF_HV2(n, i) … #define DISPC_OVL_CONV_COEF(n, i) … #define DISPC_OVL_FIR_COEF_V(n, i) … #define DISPC_OVL_FIR_COEF_V2(n, i) … #define DISPC_OVL_PRELOAD(n) … #define DISPC_OVL_MFLAG_THRESHOLD(n) … /* DISPC up/downsampling FIR filter coefficient structure */ struct dispc_coef { … }; const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps); /* DISPC manager/channel specific registers */ static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel) { … } static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel) { … } static inline u16 DISPC_TIMING_H(enum omap_channel channel) { … } static inline u16 DISPC_TIMING_V(enum omap_channel channel) { … } static inline u16 DISPC_POL_FREQ(enum omap_channel channel) { … } static inline u16 DISPC_DIVISORo(enum omap_channel channel) { … } /* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */ static inline u16 DISPC_SIZE_MGR(enum omap_channel channel) { … } static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel) { … } static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel) { … } static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel) { … } static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel) { … } static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel) { … } static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel) { … } /* DISPC overlay register base addresses */ static inline u16 DISPC_OVL_BASE(enum omap_plane_id plane) { … } /* DISPC overlay register offsets */ static inline u16 DISPC_BA0_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_BA1_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_POS_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_SIZE_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_ATTR_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_FIR_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_FIR2_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane_id plane) { … } /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane_id plane, u16 i) { … } /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane_id plane, u16 i) { … } /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane_id plane, u16 i) { … } /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane_id plane, u16 i) { … } /* coef index i = {0, 1, 2, 3, 4,} */ static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane_id plane, u16 i) { … } /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane_id plane, u16 i) { … } /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */ static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane_id plane, u16 i) { … } static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane_id plane) { … } static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane_id plane) { … } #endif
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