/* SPDX-License-Identifier: GPL-2.0-only */ /* * HDMI driver definition for TI OMAP4 Processor. * * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef _HDMI_H #define _HDMI_H #include <linux/delay.h> #include <linux/io.h> #include <linux/platform_device.h> #include <linux/hdmi.h> #include <sound/omap-hdmi-audio.h> #include <media/cec.h> #include <drm/drm_bridge.h> #include "omapdss.h" #include "dss.h" struct dss_device; /* HDMI Wrapper */ #define HDMI_WP_REVISION … #define HDMI_WP_SYSCONFIG … #define HDMI_WP_IRQSTATUS_RAW … #define HDMI_WP_IRQSTATUS … #define HDMI_WP_IRQENABLE_SET … #define HDMI_WP_IRQENABLE_CLR … #define HDMI_WP_IRQWAKEEN … #define HDMI_WP_PWR_CTRL … #define HDMI_WP_DEBOUNCE … #define HDMI_WP_VIDEO_CFG … #define HDMI_WP_VIDEO_SIZE … #define HDMI_WP_VIDEO_TIMING_H … #define HDMI_WP_VIDEO_TIMING_V … #define HDMI_WP_CLK … #define HDMI_WP_AUDIO_CFG … #define HDMI_WP_AUDIO_CFG2 … #define HDMI_WP_AUDIO_CTRL … #define HDMI_WP_AUDIO_DATA … /* HDMI WP IRQ flags */ #define HDMI_IRQ_CORE … #define HDMI_IRQ_OCP_TIMEOUT … #define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW … #define HDMI_IRQ_AUDIO_FIFO_OVERFLOW … #define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ … #define HDMI_IRQ_VIDEO_VSYNC … #define HDMI_IRQ_VIDEO_FRAME_DONE … #define HDMI_IRQ_PHY_LINE5V_ASSERT … #define HDMI_IRQ_LINK_CONNECT … #define HDMI_IRQ_LINK_DISCONNECT … #define HDMI_IRQ_PLL_LOCK … #define HDMI_IRQ_PLL_UNLOCK … #define HDMI_IRQ_PLL_RECAL … /* HDMI PLL */ #define PLLCTRL_PLL_CONTROL … #define PLLCTRL_PLL_STATUS … #define PLLCTRL_PLL_GO … #define PLLCTRL_CFG1 … #define PLLCTRL_CFG2 … #define PLLCTRL_CFG3 … #define PLLCTRL_SSC_CFG1 … #define PLLCTRL_SSC_CFG2 … #define PLLCTRL_CFG4 … /* HDMI PHY */ #define HDMI_TXPHY_TX_CTRL … #define HDMI_TXPHY_DIGITAL_CTRL … #define HDMI_TXPHY_POWER_CTRL … #define HDMI_TXPHY_PAD_CFG_CTRL … #define HDMI_TXPHY_BIST_CONTROL … enum hdmi_pll_pwr { … }; enum hdmi_phy_pwr { … }; enum hdmi_core_hdmi_dvi { … }; enum hdmi_packing_mode { … }; enum hdmi_stereo_channels { … }; enum hdmi_audio_type { … }; enum hdmi_audio_justify { … }; enum hdmi_audio_sample_order { … }; enum hdmi_audio_samples_perword { … }; enum hdmi_audio_sample_size_omap { … }; enum hdmi_audio_transf_mode { … }; enum hdmi_audio_blk_strt_end_sig { … }; enum hdmi_core_audio_layout { … }; enum hdmi_core_cts_mode { … }; enum hdmi_audio_mclk_mode { … }; struct hdmi_video_format { … }; struct hdmi_config { … }; struct hdmi_audio_format { … }; struct hdmi_audio_dma { … }; struct hdmi_core_audio_i2s_config { … }; struct hdmi_core_audio_config { … }; struct hdmi_wp_data { … }; struct hdmi_pll_data { … }; struct hdmi_phy_features { … }; struct hdmi_phy_data { … }; struct hdmi_core_data { … }; static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx, u32 val) { … } static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx) { … } #define REG_FLD_MOD(base, idx, val, start, end) … #define REG_GET(base, idx, start, end) … static inline int hdmi_wait_for_bit_change(void __iomem *base_addr, const u32 idx, int b2, int b1, u32 val) { … } /* HDMI wrapper funcs */ int hdmi_wp_video_start(struct hdmi_wp_data *wp); void hdmi_wp_video_stop(struct hdmi_wp_data *wp); void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s); u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp); void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus); void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask); void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask); int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val); int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val); void hdmi_wp_video_config_format(struct hdmi_wp_data *wp, const struct hdmi_video_format *video_fmt); void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp, const struct videomode *vm); void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, const struct videomode *vm); void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, struct videomode *vm, const struct hdmi_config *param); int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp, unsigned int version); phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp); /* HDMI PLL funcs */ void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s); int hdmi_pll_init(struct dss_device *dss, struct platform_device *pdev, struct hdmi_pll_data *pll, struct hdmi_wp_data *wp); void hdmi_pll_uninit(struct hdmi_pll_data *hpll); /* HDMI PHY funcs */ int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk, unsigned long lfbitclk); void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s); int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy, unsigned int version); int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes); /* HDMI common funcs */ int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep, struct hdmi_phy_data *phy); /* Audio funcs */ int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts); int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable); int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable); void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp, struct hdmi_audio_format *aud_fmt); void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp, struct hdmi_audio_dma *aud_dma); static inline bool hdmi_mode_has_audio(struct hdmi_config *cfg) { … } /* HDMI DRV data */ struct omap_hdmi { … }; #define drm_bridge_to_hdmi(b) … #endif
Codebase Browser
linux