linux/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Hisilicon Hi6220 SoC ADE(Advanced Display Engine)'s crtc&plane driver
 *
 * Copyright (c) 2016 Linaro Limited.
 * Copyright (c) 2014-2016 HiSilicon Limited.
 *
 * Author:
 *	Xinliang Liu <[email protected]>
 *	Xinliang Liu <[email protected]>
 *	Xinwei Kong <[email protected]>
 */

#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/mfd/syscon.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>

#include <video/display_timing.h>

#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_drv.h>
#include <drm/drm_fb_dma_helper.h>
#include <drm/drm_fourcc.h>
#include <drm/drm_framebuffer.h>
#include <drm/drm_gem_dma_helper.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_vblank.h>
#include <drm/drm_gem_framebuffer_helper.h>

#include "kirin_drm_drv.h"
#include "kirin_ade_reg.h"

#define OUT_OVLY …
#define ADE_DEBUG …


struct ade_hw_ctx { … };

static const struct kirin_format ade_formats[] = …;

static const u32 channel_formats[] = …;

/* convert from fourcc format to ade format */
static u32 ade_get_format(u32 pixel_format)
{ … }

static void ade_update_reload_bit(void __iomem *base, u32 bit_num, u32 val)
{ … }

static u32 ade_read_reload_bit(void __iomem *base, u32 bit_num)
{ … }

static void ade_init(struct ade_hw_ctx *ctx)
{ … }

static bool ade_crtc_mode_fixup(struct drm_crtc *crtc,
				const struct drm_display_mode *mode,
				struct drm_display_mode *adjusted_mode)
{ … }


static void ade_set_pix_clk(struct ade_hw_ctx *ctx,
			    struct drm_display_mode *mode,
			    struct drm_display_mode *adj_mode)
{ … }

static void ade_ldi_set_mode(struct ade_hw_ctx *ctx,
			     struct drm_display_mode *mode,
			     struct drm_display_mode *adj_mode)
{ … }

static int ade_power_up(struct ade_hw_ctx *ctx)
{ … }

static void ade_power_down(struct ade_hw_ctx *ctx)
{ … }

static void ade_set_medianoc_qos(struct ade_hw_ctx *ctx)
{ … }

static int ade_crtc_enable_vblank(struct drm_crtc *crtc)
{ … }

static void ade_crtc_disable_vblank(struct drm_crtc *crtc)
{ … }

static irqreturn_t ade_irq_handler(int irq, void *data)
{ … }

static void ade_display_enable(struct ade_hw_ctx *ctx)
{ … }

#if ADE_DEBUG
static void ade_rdma_dump_regs(void __iomem *base, u32 ch)
{ … }

static void ade_clip_dump_regs(void __iomem *base, u32 ch)
{ … }

static void ade_compositor_routing_dump_regs(void __iomem *base, u32 ch)
{ … }

static void ade_dump_overlay_compositor_regs(void __iomem *base, u32 comp)
{ … }

static void ade_dump_regs(void __iomem *base)
{ … }
#else
static void ade_dump_regs(void __iomem *base) { }
#endif

static void ade_crtc_atomic_enable(struct drm_crtc *crtc,
				   struct drm_atomic_state *state)
{ … }

static void ade_crtc_atomic_disable(struct drm_crtc *crtc,
				    struct drm_atomic_state *state)
{ … }

static void ade_crtc_mode_set_nofb(struct drm_crtc *crtc)
{ … }

static void ade_crtc_atomic_begin(struct drm_crtc *crtc,
				  struct drm_atomic_state *state)
{ … }

static void ade_crtc_atomic_flush(struct drm_crtc *crtc,
				  struct drm_atomic_state *state)

{ … }

static const struct drm_crtc_helper_funcs ade_crtc_helper_funcs = …;

static const struct drm_crtc_funcs ade_crtc_funcs = …;

static void ade_rdma_set(void __iomem *base, struct drm_framebuffer *fb,
			 u32 ch, u32 y, u32 in_h, u32 fmt)
{ … }

static void ade_rdma_disable(void __iomem *base, u32 ch)
{ … }

static void ade_clip_set(void __iomem *base, u32 ch, u32 fb_w, u32 x,
			 u32 in_w, u32 in_h)
{ … }

static void ade_clip_disable(void __iomem *base, u32 ch)
{ … }

static bool has_Alpha_channel(int format)
{ … }

static void ade_get_blending_params(u32 fmt, u8 glb_alpha, u8 *alp_mode,
				    u8 *alp_sel, u8 *under_alp_sel)
{ … }

static void ade_compositor_routing_set(void __iomem *base, u8 ch,
				       u32 x0, u32 y0,
				       u32 in_w, u32 in_h, u32 fmt)
{ … }

static void ade_compositor_routing_disable(void __iomem *base, u32 ch)
{ … }

/*
 * Typicaly, a channel looks like: DMA-->clip-->scale-->ctrans-->compositor
 */
static void ade_update_channel(struct kirin_plane *kplane,
			       struct drm_framebuffer *fb, int crtc_x,
			       int crtc_y, unsigned int crtc_w,
			       unsigned int crtc_h, u32 src_x,
			       u32 src_y, u32 src_w, u32 src_h)
{ … }

static void ade_disable_channel(struct kirin_plane *kplane)
{ … }

static int ade_plane_atomic_check(struct drm_plane *plane,
				  struct drm_atomic_state *state)
{ … }

static void ade_plane_atomic_update(struct drm_plane *plane,
				    struct drm_atomic_state *state)
{ … }

static void ade_plane_atomic_disable(struct drm_plane *plane,
				     struct drm_atomic_state *state)
{ … }

static const struct drm_plane_helper_funcs ade_plane_helper_funcs = …;

static struct drm_plane_funcs ade_plane_funcs = …;

static void *ade_hw_ctx_alloc(struct platform_device *pdev,
			      struct drm_crtc *crtc)
{ … }

static void ade_hw_ctx_cleanup(void *hw_ctx)
{ … }

static const struct drm_mode_config_funcs ade_mode_config_funcs = …;

DEFINE_DRM_GEM_DMA_FOPS(ade_fops);

static const struct drm_driver ade_driver = …;

struct kirin_drm_data ade_driver_data = …;