/* Copyright 2008 - 2016 Freescale Semiconductor, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * ALTERNATIVELY, this software may be distributed under the terms of the * GNU General Public License ("GPL") as published by the Free Software * Foundation, either version 2 of that License or (at your option) any * later version. * * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "qman_priv.h" u16 qman_ip_rev; EXPORT_SYMBOL(…); u16 qm_channel_pool1 = …; EXPORT_SYMBOL(…); u16 qm_channel_caam = …; EXPORT_SYMBOL(…); /* Register offsets */ #define REG_QCSP_LIO_CFG(n) … #define REG_QCSP_IO_CFG(n) … #define REG_QCSP_DD_CFG(n) … #define REG_DD_CFG … #define REG_DCP_CFG(n) … #define REG_DCP_DD_CFG(n) … #define REG_DCP_DLM_AVG(n) … #define REG_PFDR_FPC … #define REG_PFDR_FP_HEAD … #define REG_PFDR_FP_TAIL … #define REG_PFDR_FP_LWIT … #define REG_PFDR_CFG … #define REG_SFDR_CFG … #define REG_SFDR_IN_USE … #define REG_WQ_CS_CFG(n) … #define REG_WQ_DEF_ENC_WQID … #define REG_WQ_SC_DD_CFG(n) … #define REG_WQ_PC_DD_CFG(n) … #define REG_WQ_DC0_DD_CFG(n) … #define REG_WQ_DC1_DD_CFG(n) … #define REG_WQ_DCn_DD_CFG(n) … #define REG_CM_CFG … #define REG_ECSR … #define REG_ECIR … #define REG_EADR … #define REG_ECIR2 … #define REG_EDATA(n) … #define REG_SBEC(n) … #define REG_MCR … #define REG_MCP(n) … #define REG_MISC_CFG … #define REG_HID_CFG … #define REG_IDLE_STAT … #define REG_IP_REV_1 … #define REG_IP_REV_2 … #define REG_FQD_BARE … #define REG_PFDR_BARE … #define REG_offset_BAR … #define REG_offset_AR … #define REG_QCSP_BARE … #define REG_QCSP_BAR … #define REG_CI_SCHED_CFG … #define REG_SRCIDR … #define REG_LIODNR … #define REG_CI_RLM_AVG … #define REG_ERR_ISR … #define REG_ERR_IER … #define REG_REV3_QCSP_LIO_CFG(n) … #define REG_REV3_QCSP_IO_CFG(n) … #define REG_REV3_QCSP_DD_CFG(n) … /* Assists for QMAN_MCR */ #define MCR_INIT_PFDR … #define MCR_get_rslt(v) … #define MCR_rslt_idle(r) … #define MCR_rslt_ok(r) … #define MCR_rslt_eaccess(r) … #define MCR_rslt_inval(r) … /* * Corenet initiator settings. Stash request queues are 4-deep to match cores * ability to snarf. Stash priority is 3, other priorities are 2. */ #define QM_CI_SCHED_CFG_SRCCIV … #define QM_CI_SCHED_CFG_SRQ_W … #define QM_CI_SCHED_CFG_RW_W … #define QM_CI_SCHED_CFG_BMAN_W … /* write SRCCIV enable */ #define QM_CI_SCHED_CFG_SRCCIV_EN … /* Follows WQ_CS_CFG0-5 */ enum qm_wq_class { … }; /* Follows FQD_[BARE|BAR|AR] and PFDR_[BARE|BAR|AR] */ enum qm_memory { … }; /* Used by all error interrupt registers except 'inhibit' */ #define QM_EIRQ_CIDE … #define QM_EIRQ_CTDE … #define QM_EIRQ_CITT … #define QM_EIRQ_PLWI … #define QM_EIRQ_MBEI … #define QM_EIRQ_SBEI … #define QM_EIRQ_PEBI … #define QM_EIRQ_IFSI … #define QM_EIRQ_ICVI … #define QM_EIRQ_IDDI … #define QM_EIRQ_IDFI … #define QM_EIRQ_IDSI … #define QM_EIRQ_IDQI … #define QM_EIRQ_IECE … #define QM_EIRQ_IEOI … #define QM_EIRQ_IESI … #define QM_EIRQ_IECI … #define QM_EIRQ_IEQI … /* QMAN_ECIR valid error bit */ #define PORTAL_ECSR_ERR … #define FQID_ECSR_ERR … struct qm_ecir { … }; static bool qm_ecir_is_dcp(const struct qm_ecir *p) { … } static int qm_ecir_get_pnum(const struct qm_ecir *p) { … } static int qm_ecir_get_fqid(const struct qm_ecir *p) { … } struct qm_ecir2 { … }; static bool qm_ecir2_is_dcp(const struct qm_ecir2 *p) { … } static int qm_ecir2_get_pnum(const struct qm_ecir2 *p) { … } struct qm_eadr { … }; static int qm_eadr_get_memid(const struct qm_eadr *p) { … } static int qm_eadr_get_eadr(const struct qm_eadr *p) { … } static int qm_eadr_v3_get_memid(const struct qm_eadr *p) { … } static int qm_eadr_v3_get_eadr(const struct qm_eadr *p) { … } struct qman_hwerr_txt { … }; static const struct qman_hwerr_txt qman_hwerr_txts[] = …; struct qman_error_info_mdata { … }; static const struct qman_error_info_mdata error_mdata[] = …; #define QMAN_ERRS_TO_DISABLE … /* * TODO: unimplemented registers * * Keeping a list here of QMan registers I have not yet covered; * QCSP_DD_IHRSR, QCSP_DD_IHRFR, QCSP_DD_HASR, * DCP_DD_IHRSR, DCP_DD_IHRFR, DCP_DD_HASR, CM_CFG, * QMAN_EECC, QMAN_SBET, QMAN_EINJ, QMAN_SBEC0-12 */ /* Pointer to the start of the QMan's CCSR space */ static u32 __iomem *qm_ccsr_start; /* A SDQCR mask comprising all the available/visible pool channels */ static u32 qm_pools_sdqcr; static int __qman_probed; static int __qman_requires_cleanup; static inline u32 qm_ccsr_in(u32 offset) { … } static inline void qm_ccsr_out(u32 offset, u32 val) { … } u32 qm_get_pools_sdqcr(void) { … } enum qm_dc_portal { … }; static void qm_set_dc(enum qm_dc_portal portal, int ed, u8 sernd) { … } static void qm_set_wq_scheduling(enum qm_wq_class wq_class, u8 cs_elev, u8 csw2, u8 csw3, u8 csw4, u8 csw5, u8 csw6, u8 csw7) { … } static void qm_set_hid(void) { … } static void qm_set_corenet_initiator(void) { … } static void qm_get_version(u16 *id, u8 *major, u8 *minor) { … } #define PFDR_AR_EN … static int qm_set_memory(enum qm_memory memory, u64 ba, u32 size) { … } static void qm_set_pfdr_threshold(u32 th, u8 k) { … } static void qm_set_sfdr_threshold(u16 th) { … } static int qm_init_pfdr(struct device *dev, u32 pfdr_start, u32 num) { … } /* * QMan needs two global memory areas initialized at boot time: * 1) FQD: Frame Queue Descriptors used to manage frame queues * 2) PFDR: Packed Frame Queue Descriptor Records used to store frames * Both areas are reserved using the device tree reserved memory framework * and the addresses and sizes are initialized when the QMan device is probed */ static dma_addr_t fqd_a, pfdr_a; static size_t fqd_sz, pfdr_sz; #ifdef CONFIG_PPC /* * Support for PPC Device Tree backward compatibility when compatible * string is set to fsl-qman-fqd and fsl-qman-pfdr */ static int zero_priv_mem(phys_addr_t addr, size_t sz) { /* map as cacheable, non-guarded */ void __iomem *tmpp = ioremap_cache(addr, sz); if (!tmpp) return -ENOMEM; memset_io(tmpp, 0, sz); flush_dcache_range((unsigned long)tmpp, (unsigned long)tmpp + sz); iounmap(tmpp); return 0; } #endif unsigned int qm_get_fqid_maxcnt(void) { … } static void log_edata_bits(struct device *dev, u32 bit_count) { … } static void log_additional_error_info(struct device *dev, u32 isr_val, u32 ecsr_val) { … } static irqreturn_t qman_isr(int irq, void *ptr) { … } static int qman_init_ccsr(struct device *dev) { … } #define LIO_CFG_LIODN_MASK … void __qman_liodn_fixup(u16 channel) { … } #define IO_CFG_SDEST_MASK … void qman_set_sdest(u16 channel, unsigned int cpu_idx) { … } static int qman_resource_init(struct device *dev) { … } int qman_is_probed(void) { … } EXPORT_SYMBOL_GPL(…); int qman_requires_cleanup(void) { … } void qman_done_cleanup(void) { … } static int fsl_qman_probe(struct platform_device *pdev) { … } static const struct of_device_id fsl_qman_ids[] = …; static struct platform_driver fsl_qman_driver = …; builtin_platform_driver(…) …;
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