/* Copyright 2008 - 2016 Freescale Semiconductor, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * ALTERNATIVELY, this software may be distributed under the terms of the * GNU General Public License ("GPL") as published by the Free Software * Foundation, either version 2 of that License or (at your option) any * later version. * * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "bman_priv.h" #define IRQNAME … #define MAX_IRQNAME … /* Portal register assists */ #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) /* Cache-inhibited register offsets */ #define BM_REG_RCR_PI_CINH … #define BM_REG_RCR_CI_CINH … #define BM_REG_RCR_ITR … #define BM_REG_CFG … #define BM_REG_SCN … #define BM_REG_ISR … #define BM_REG_IER … #define BM_REG_ISDR … #define BM_REG_IIR … /* Cache-enabled register offsets */ #define BM_CL_CR … #define BM_CL_RR0 … #define BM_CL_RR1 … #define BM_CL_RCR … #define BM_CL_RCR_PI_CENA … #define BM_CL_RCR_CI_CENA … #else /* Cache-inhibited register offsets */ #define BM_REG_RCR_PI_CINH … #define BM_REG_RCR_CI_CINH … #define BM_REG_RCR_ITR … #define BM_REG_CFG … #define BM_REG_SCN(n) … #define BM_REG_ISR … #define BM_REG_IER … #define BM_REG_ISDR … #define BM_REG_IIR … /* Cache-enabled register offsets */ #define BM_CL_CR … #define BM_CL_RR0 … #define BM_CL_RR1 … #define BM_CL_RCR … #define BM_CL_RCR_PI_CENA … #define BM_CL_RCR_CI_CENA … #endif /* * Portal modes. * Enum types; * pmode == production mode * cmode == consumption mode, * Enum values use 3 letter codes. First letter matches the portal mode, * remaining two letters indicate; * ci == cache-inhibited portal register * ce == cache-enabled portal register * vb == in-band valid-bit (cache-enabled) */ enum bm_rcr_pmode { … }; enum bm_rcr_cmode { … }; /* --- Portal structures --- */ #define BM_RCR_SIZE … /* Release Command */ struct bm_rcr_entry { … }; #define BM_RCR_VERB_VBIT … #define BM_RCR_VERB_CMD_MASK … #define BM_RCR_VERB_CMD_BPID_SINGLE … #define BM_RCR_VERB_CMD_BPID_MULTI … #define BM_RCR_VERB_BUFCOUNT_MASK … struct bm_rcr { … }; /* MC (Management Command) command */ struct bm_mc_command { … }; #define BM_MCC_VERB_VBIT … #define BM_MCC_VERB_CMD_MASK … #define BM_MCC_VERB_CMD_ACQUIRE … #define BM_MCC_VERB_CMD_QUERY … #define BM_MCC_VERB_ACQUIRE_BUFCOUNT … /* MC result, Acquire and Query Response */ bm_mc_result; #define BM_MCR_VERB_VBIT … #define BM_MCR_VERB_CMD_MASK … #define BM_MCR_VERB_CMD_ACQUIRE … #define BM_MCR_VERB_CMD_QUERY … #define BM_MCR_VERB_CMD_ERR_INVALID … #define BM_MCR_VERB_CMD_ERR_ECC … #define BM_MCR_VERB_ACQUIRE_BUFCOUNT … #define BM_MCR_TIMEOUT … struct bm_mc { … }; struct bm_addr { … }; struct bm_portal { … } ____cacheline_aligned; /* Cache-inhibited register access. */ static inline u32 bm_in(struct bm_portal *p, u32 offset) { … } static inline void bm_out(struct bm_portal *p, u32 offset, u32 val) { … } /* Cache Enabled Portal Access */ static inline void bm_cl_invalidate(struct bm_portal *p, u32 offset) { … } static inline void bm_cl_touch_ro(struct bm_portal *p, u32 offset) { … } static inline u32 bm_ce_in(struct bm_portal *p, u32 offset) { … } struct bman_portal { … }; static cpumask_t affine_mask; static DEFINE_SPINLOCK(affine_mask_lock); static DEFINE_PER_CPU(struct bman_portal, bman_affine_portal); static inline struct bman_portal *get_affine_portal(void) { … } static inline void put_affine_portal(void) { … } /* * This object type refers to a pool, it isn't *the* pool. There may be * more than one such object per BMan buffer pool, eg. if different users of the * pool are operating via different portals. */ struct bman_pool { … }; static u32 poll_portal_slow(struct bman_portal *p, u32 is); static irqreturn_t portal_isr(int irq, void *ptr) { … } /* --- RCR API --- */ #define RCR_SHIFT … #define RCR_CARRY … /* Bit-wise logic to wrap a ring pointer by clearing the "carry bit" */ static struct bm_rcr_entry *rcr_carryclear(struct bm_rcr_entry *p) { … } #ifdef CONFIG_FSL_DPAA_CHECKING /* Bit-wise logic to convert a ring pointer to a ring index */ static int rcr_ptr2idx(struct bm_rcr_entry *e) { … } #endif /* Increment the 'cursor' ring pointer, taking 'vbit' into account */ static inline void rcr_inc(struct bm_rcr *rcr) { … } static int bm_rcr_get_avail(struct bm_portal *portal) { … } static int bm_rcr_get_fill(struct bm_portal *portal) { … } static void bm_rcr_set_ithresh(struct bm_portal *portal, u8 ithresh) { … } static void bm_rcr_cce_prefetch(struct bm_portal *portal) { … } static u8 bm_rcr_cce_update(struct bm_portal *portal) { … } static inline struct bm_rcr_entry *bm_rcr_start(struct bm_portal *portal) { … } static inline void bm_rcr_pvb_commit(struct bm_portal *portal, u8 myverb) { … } static int bm_rcr_init(struct bm_portal *portal, enum bm_rcr_pmode pmode, enum bm_rcr_cmode cmode) { … } static void bm_rcr_finish(struct bm_portal *portal) { … } /* --- Management command API --- */ static int bm_mc_init(struct bm_portal *portal) { … } static void bm_mc_finish(struct bm_portal *portal) { … } static inline struct bm_mc_command *bm_mc_start(struct bm_portal *portal) { … } static inline void bm_mc_commit(struct bm_portal *portal, u8 myverb) { … } static inline union bm_mc_result *bm_mc_result(struct bm_portal *portal) { … } static inline int bm_mc_result_timeout(struct bm_portal *portal, union bm_mc_result **mcr) { … } /* Disable all BSCN interrupts for the portal */ static void bm_isr_bscn_disable(struct bm_portal *portal) { … } static int bman_create_portal(struct bman_portal *portal, const struct bm_portal_config *c) { … } struct bman_portal *bman_create_affine_portal(const struct bm_portal_config *c) { … } static u32 poll_portal_slow(struct bman_portal *p, u32 is) { … } int bman_p_irqsource_add(struct bman_portal *p, u32 bits) { … } int bm_shutdown_pool(u32 bpid) { … } struct gen_pool *bm_bpalloc; static int bm_alloc_bpid_range(u32 *result, u32 count) { … } static int bm_release_bpid(u32 bpid) { … } struct bman_pool *bman_new_pool(void) { … } EXPORT_SYMBOL(…); void bman_free_pool(struct bman_pool *pool) { … } EXPORT_SYMBOL(…); int bman_get_bpid(const struct bman_pool *pool) { … } EXPORT_SYMBOL(…); static void update_rcr_ci(struct bman_portal *p, int avail) { … } int bman_release(struct bman_pool *pool, const struct bm_buffer *bufs, u8 num) { … } EXPORT_SYMBOL(…); int bman_acquire(struct bman_pool *pool, struct bm_buffer *bufs, u8 num) { … } EXPORT_SYMBOL(…); const struct bm_portal_config * bman_get_bm_portal_config(const struct bman_portal *portal) { … }
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