# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek DWMAC glue layer controller
maintainers:
- Biao Huang <[email protected]>
description:
This file documents platform glue layer for stmmac.
# We need a select here so we don't match all nodes with 'snps,dwmac'
select:
properties:
compatible:
contains:
enum:
- mediatek,mt2712-gmac
- mediatek,mt8188-gmac
- mediatek,mt8195-gmac
required:
- compatible
allOf:
- $ref: snps,dwmac.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- mediatek,mt2712-gmac
- const: snps,dwmac-4.20a
- items:
- enum:
- mediatek,mt8195-gmac
- const: snps,dwmac-5.10a
- items:
- enum:
- mediatek,mt8188-gmac
- const: mediatek,mt8195-gmac
- const: snps,dwmac-5.10a
clocks:
minItems: 5
items:
- description: AXI clock
- description: APB clock
- description: MAC Main clock
- description: PTP clock
- description: RMII reference clock provided by MAC
- description: MAC clock gate
clock-names:
minItems: 5
items:
- const: axi
- const: apb
- const: mac_main
- const: ptp_ref
- const: rmii_internal
- const: mac_cg
power-domains:
maxItems: 1
mediatek,pericfg:
$ref: /schemas/types.yaml#/definitions/phandle
description:
The phandle to the syscon node that control ethernet
interface and timing delay.
mediatek,tx-delay-ps:
description:
The internal TX clock delay (provided by this driver) in nanoseconds.
For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
or will round down. Range 0~31*170.
For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
or will round down. Range 0~31*550.
For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,
or will round down. Range 0~31*290.
mediatek,rx-delay-ps:
description:
The internal RX clock delay (provided by this driver) in nanoseconds.
For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
or will round down. Range 0~31*170.
For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
or will round down. Range 0~31*550.
For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple
of 290, or will round down. Range 0~31*290.
mediatek,rmii-rxc:
type: boolean
description:
If present, indicates that the RMII reference clock, which is from external
PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin.
mediatek,rmii-clk-from-mac:
type: boolean
description:
If present, indicates that MAC provides the RMII reference clock, which
outputs to TXC pin only.
mediatek,txc-inverse:
type: boolean
description:
If present, indicates that
1. tx clock will be inversed in MII/RGMII case,
2. tx clock inside MAC will be inversed relative to reference clock
which is from external PHYs in RMII case, and it rarely happen.
3. the reference clock, which outputs to TXC pin will be inversed in RMII case
when the reference clock is from MAC.
mediatek,rxc-inverse:
type: boolean
description:
If present, indicates that
1. rx clock will be inversed in MII/RGMII case.
2. reference clock will be inversed when arrived at MAC in RMII case, when
the reference clock is from external PHYs.
3. the inside clock, which be sent to MAC, will be inversed in RMII case when
the reference clock is from MAC.
mediatek,mac-wol:
type: boolean
description:
If present, indicates that MAC supports WOL(Wake-On-LAN), and MAC WOL will be enabled.
Otherwise, PHY WOL is preferred.
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
- clock-names
- phy-mode
- mediatek,pericfg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/mt2712-clk.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt2712-power.h>
eth: ethernet@1101c000 {
compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
reg = <0x1101c000 0x1300>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "macirq";
phy-mode = "rgmii-rxid";
mac-address = [00 55 7b b5 7d f7];
clock-names = "axi",
"apb",
"mac_main",
"ptp_ref",
"rmii_internal";
clocks = <&pericfg CLK_PERI_GMAC>,
<&pericfg CLK_PERI_GMAC_PCLK>,
<&topckgen CLK_TOP_ETHER_125M_SEL>,
<&topckgen CLK_TOP_ETHER_50M_SEL>,
<&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
<&topckgen CLK_TOP_ETHER_50M_SEL>,
<&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
<&topckgen CLK_TOP_APLL1_D3>,
<&topckgen CLK_TOP_ETHERPLL_50M>;
power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
mediatek,pericfg = <&pericfg>;
mediatek,tx-delay-ps = <1530>;
snps,txpbl = <1>;
snps,rxpbl = <1>;
snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
snps,reset-delays-us = <0 10000 10000>;
};
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