# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung MIPI DSIM bridge controller
maintainers:
- Inki Dae <[email protected]>
- Jagan Teki <[email protected]>
- Marek Szyprowski <[email protected]>
description: |
Samsung MIPI DSIM bridge controller can be found it on Exynos
and i.MX8M Mini/Nano/Plus SoC's.
properties:
compatible:
oneOf:
- enum:
- samsung,exynos3250-mipi-dsi
- samsung,exynos4210-mipi-dsi
- samsung,exynos5410-mipi-dsi
- samsung,exynos5422-mipi-dsi
- samsung,exynos5433-mipi-dsi
- fsl,imx8mm-mipi-dsim
- fsl,imx8mp-mipi-dsim
- items:
- const: fsl,imx8mn-mipi-dsim
- const: fsl,imx8mm-mipi-dsim
reg:
maxItems: 1
interrupts:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
clocks:
minItems: 2
maxItems: 5
clock-names:
minItems: 2
maxItems: 5
samsung,phy-type:
$ref: /schemas/types.yaml#/definitions/uint32
description: phandle to the samsung phy-type
power-domains:
maxItems: 1
samsung,power-domain:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the associated samsung power domain
vddcore-supply:
description: MIPI DSIM Core voltage supply (e.g. 1.1V)
vddio-supply:
description: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
samsung,burst-clock-frequency:
$ref: /schemas/types.yaml#/definitions/uint32
description:
DSIM high speed burst mode frequency. If absent,
the pixel clock from the attached device or bridge
will be used instead.
samsung,esc-clock-frequency:
$ref: /schemas/types.yaml#/definitions/uint32
description:
DSIM escape mode frequency.
samsung,pll-clock-frequency:
$ref: /schemas/types.yaml#/definitions/uint32
description:
DSIM oscillator clock frequency. If absent, the clock frequency
of sclk_mipi will be used instead.
phys:
maxItems: 1
phy-names:
const: dsim
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
Input port node to receive pixel data from the
display controller. Exactly one endpoint must be
specified.
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
DSI output port node to the panel or the next bridge
in the chain.
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 4
uniqueItems: true
items:
enum: [ 1, 2, 3, 4 ]
lane-polarities:
minItems: 1
maxItems: 5
description:
The Samsung MIPI DSI IP requires that all the data lanes have
the same polarity.
dependencies:
lane-polarities: [data-lanes]
required:
- clock-names
- clocks
- compatible
- interrupts
- reg
- samsung,esc-clock-frequency
allOf:
- $ref: ../dsi-controller.yaml#
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-mipi-dsi
then:
properties:
clocks:
minItems: 5
clock-names:
items:
- const: bus_clk
- const: phyclk_mipidphy0_bitclkdiv8
- const: phyclk_mipidphy0_rxclkesc0
- const: sclk_rgb_vclk_to_dsim0
- const: sclk_mipi
ports:
required:
- port@0
required:
- ports
- vddcore-supply
- vddio-supply
- if:
properties:
compatible:
contains:
const: samsung,exynos5410-mipi-dsi
then:
properties:
clocks:
minItems: 2
clock-names:
items:
- const: bus_clk
- const: pll_clk
required:
- vddcore-supply
- vddio-supply
- if:
properties:
compatible:
contains:
const: samsung,exynos4210-mipi-dsi
then:
properties:
clocks:
minItems: 2
clock-names:
items:
- const: bus_clk
- const: sclk_mipi
required:
- vddcore-supply
- vddio-supply
- if:
properties:
compatible:
contains:
const: samsung,exynos3250-mipi-dsi
then:
properties:
clocks:
minItems: 2
clock-names:
items:
- const: bus_clk
- const: pll_clk
required:
- vddcore-supply
- vddio-supply
- samsung,phy-type
additionalProperties:
type: object
examples:
- |
#include <dt-bindings/clock/exynos5433.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
dsi@13900000 {
compatible = "samsung,exynos5433-mipi-dsi";
reg = <0x13900000 0xC0>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
phys = <&mipi_phy 1>;
phy-names = "dsim";
clocks = <&cmu_disp CLK_PCLK_DSIM0>,
<&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
<&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
<&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
<&cmu_disp CLK_SCLK_DSIM0>;
clock-names = "bus_clk",
"phyclk_mipidphy0_bitclkdiv8",
"phyclk_mipidphy0_rxclkesc0",
"sclk_rgb_vclk_to_dsim0",
"sclk_mipi";
power-domains = <&pd_disp>;
vddcore-supply = <&ldo6_reg>;
vddio-supply = <&ldo7_reg>;
samsung,burst-clock-frequency = <512000000>;
samsung,esc-clock-frequency = <16000000>;
samsung,pll-clock-frequency = <24000000>;
pinctrl-names = "default";
pinctrl-0 = <&te_irq>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_to_mic: endpoint {
remote-endpoint = <&mic_to_dsi>;
};
};
};
};
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