/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "umc_v8_10.h" #include "amdgpu_ras.h" #include "amdgpu_umc.h" #include "amdgpu.h" #include "umc/umc_8_10_0_offset.h" #include "umc/umc_8_10_0_sh_mask.h" #define UMC_8_NODE_DIST … #define UMC_8_INST_DIST … struct channelnum_map_colbit { … }; const struct channelnum_map_colbit umc_v8_10_channelnum_map_colbit_table[] = …; const uint32_t umc_v8_10_channel_idx_tbl_ext0[] [UMC_V8_10_UMC_INSTANCE_NUM] [UMC_V8_10_CHANNEL_INSTANCE_NUM] = …; const uint32_t umc_v8_10_channel_idx_tbl[] [UMC_V8_10_UMC_INSTANCE_NUM] [UMC_V8_10_CHANNEL_INSTANCE_NUM] = …; static inline uint32_t get_umc_v8_10_reg_offset(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst) { … } static int umc_v8_10_clear_error_count_per_channel(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) { … } static void umc_v8_10_clear_error_count(struct amdgpu_device *adev) { … } static void umc_v8_10_query_correctable_error_count(struct amdgpu_device *adev, uint32_t umc_reg_offset, unsigned long *error_count) { … } static void umc_v8_10_query_uncorrectable_error_count(struct amdgpu_device *adev, uint32_t umc_reg_offset, unsigned long *error_count) { … } static int umc_v8_10_query_ecc_error_count(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) { … } static void umc_v8_10_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status) { … } static uint32_t umc_v8_10_get_col_bit(uint32_t channel_num) { … } /* * Mapping normal address to soc physical address in swizzle mode. */ static int umc_v8_10_swizzle_mode_na_to_pa(struct amdgpu_device *adev, uint32_t channel_idx, uint64_t na, uint64_t *soc_pa) { … } static void umc_v8_10_convert_error_address(struct amdgpu_device *adev, struct ras_err_data *err_data, uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst, uint32_t node_inst, uint64_t mc_umc_status) { … } static int umc_v8_10_query_error_address(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) { … } static void umc_v8_10_query_ras_error_address(struct amdgpu_device *adev, void *ras_error_status) { … } static int umc_v8_10_err_cnt_init_per_channel(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) { … } static void umc_v8_10_err_cnt_init(struct amdgpu_device *adev) { … } static bool umc_v8_10_query_ras_poison_mode(struct amdgpu_device *adev) { … } static void umc_v8_10_ecc_info_query_correctable_error_count(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, unsigned long *error_count) { … } static void umc_v8_10_ecc_info_query_uncorrectable_error_count(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, unsigned long *error_count) { … } static int umc_v8_10_ecc_info_query_ecc_error_count(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) { … } static void umc_v8_10_ecc_info_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status) { … } static int umc_v8_10_ecc_info_query_error_address(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) { … } static void umc_v8_10_ecc_info_query_ras_error_address(struct amdgpu_device *adev, void *ras_error_status) { … } const struct amdgpu_ras_block_hw_ops umc_v8_10_ras_hw_ops = …; struct amdgpu_umc_ras umc_v8_10_ras = …;
Codebase Browser
linux