#include "amdgpu.h"
#include "mmhub_v1_8.h"
#include "mmhub/mmhub_1_8_0_offset.h"
#include "mmhub/mmhub_1_8_0_sh_mask.h"
#include "vega10_enum.h"
#include "soc15_common.h"
#include "soc15.h"
#include "amdgpu_ras.h"
#define regVM_L2_CNTL3_DEFAULT …
#define regVM_L2_CNTL4_DEFAULT …
#define mmSMNAID_AID0_MCA_SMU …
static u64 mmhub_v1_8_get_fb_location(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_8_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
uint64_t page_table_base)
{ … }
static void mmhub_v1_8_init_gart_aperture_regs(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_8_init_system_aperture_regs(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_8_init_tlb_regs(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_8_init_cache_regs(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_8_enable_system_domain(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_8_disable_identity_aperture(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_8_program_invalidation(struct amdgpu_device *adev)
{ … }
static int mmhub_v1_8_gart_enable(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_8_gart_disable(struct amdgpu_device *adev)
{ … }
static void mmhub_v1_8_set_fault_enable_default(struct amdgpu_device *adev, bool value)
{ … }
static void mmhub_v1_8_init(struct amdgpu_device *adev)
{ … }
static int mmhub_v1_8_set_clockgating(struct amdgpu_device *adev,
enum amd_clockgating_state state)
{ … }
static void mmhub_v1_8_get_clockgating(struct amdgpu_device *adev, u64 *flags)
{ … }
static bool mmhub_v1_8_query_utcl2_poison_status(struct amdgpu_device *adev,
int hub_inst)
{ … }
const struct amdgpu_mmhub_funcs mmhub_v1_8_funcs = …;
static const struct amdgpu_ras_err_status_reg_entry mmhub_v1_8_ce_reg_list[] = …;
static const struct amdgpu_ras_err_status_reg_entry mmhub_v1_8_ue_reg_list[] = …;
static const struct amdgpu_ras_memory_id_entry mmhub_v1_8_ras_memory_list[] = …;
static void mmhub_v1_8_inst_query_ras_error_count(struct amdgpu_device *adev,
uint32_t mmhub_inst,
void *ras_err_status)
{ … }
static void mmhub_v1_8_query_ras_error_count(struct amdgpu_device *adev,
void *ras_err_status)
{ … }
static void mmhub_v1_8_inst_reset_ras_error_count(struct amdgpu_device *adev,
uint32_t mmhub_inst)
{ … }
static void mmhub_v1_8_reset_ras_error_count(struct amdgpu_device *adev)
{ … }
static const struct amdgpu_ras_block_hw_ops mmhub_v1_8_ras_hw_ops = …;
static int mmhub_v1_8_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,
enum aca_smu_type type, void *data)
{ … }
static int mmhub_v1_8_err_codes[] = …;
static bool mmhub_v1_8_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
enum aca_smu_type type, void *data)
{ … }
static const struct aca_bank_ops mmhub_v1_8_aca_bank_ops = …;
static const struct aca_info mmhub_v1_8_aca_info = …;
static int mmhub_v1_8_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
{ … }
struct amdgpu_mmhub_ras mmhub_v1_8_ras = …;