/* * Copyright 2020 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/pci.h> #include "amdgpu.h" #include "amdgpu_ih.h" #include "soc15.h" #include "oss/osssys_4_2_0_offset.h" #include "oss/osssys_4_2_0_sh_mask.h" #include "soc15_common.h" #include "vega20_ih.h" #define MAX_REARM_RETRY … #define mmIH_CHICKEN_ALDEBARAN … #define mmIH_CHICKEN_ALDEBARAN_BASE_IDX … #define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN … #define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN_BASE_IDX … #define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE__SHIFT … #define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE_MASK … static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev); /** * vega20_ih_init_register_offset - Initialize register offset for ih rings * * @adev: amdgpu_device pointer * * Initialize register offset ih rings (VEGA20). */ static void vega20_ih_init_register_offset(struct amdgpu_device *adev) { … } /** * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer * * @adev: amdgpu_device pointer * @ih: amdgpu_ih_ring pointer * @enable: true - enable the interrupts, false - disable the interrupts * * Toggle the interrupt ring buffer (VEGA20) */ static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, bool enable) { … } /** * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers * * @adev: amdgpu_device pointer * @enable: enable or disable interrupt ring buffers * * Toggle all the available interrupt ring buffers (VEGA20). */ static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) { … } static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) { … } static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) { … } /** * vega20_ih_enable_ring - enable an ih ring buffer * * @adev: amdgpu_device pointer * @ih: amdgpu_ih_ring pointer * * Enable an ih ring buffer (VEGA20) */ static int vega20_ih_enable_ring(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) { … } static uint32_t vega20_setup_retry_doorbell(u32 doorbell_index) { … } /** * vega20_ih_irq_init - init and enable the interrupt ring * * @adev: amdgpu_device pointer * * Allocate a ring buffer for the interrupt controller, * enable the RLC, disable interrupts, enable the IH * ring buffer and enable it (VI). * Called at device load and reume. * Returns 0 for success, errors for failure. */ static int vega20_ih_irq_init(struct amdgpu_device *adev) { … } /** * vega20_ih_irq_disable - disable interrupts * * @adev: amdgpu_device pointer * * Disable interrupts on the hw (VEGA20). */ static void vega20_ih_irq_disable(struct amdgpu_device *adev) { … } /** * vega20_ih_get_wptr - get the IH ring buffer wptr * * @adev: amdgpu_device pointer * @ih: amdgpu_ih_ring pointer * * Get the IH ring buffer wptr from either the register * or the writeback memory buffer (VEGA20). Also check for * ring buffer overflow and deal with it. * Returns the value of the wptr. */ static u32 vega20_ih_get_wptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) { … } /** * vega20_ih_irq_rearm - rearm IRQ if lost * * @adev: amdgpu_device pointer * @ih: amdgpu_ih_ring pointer * */ static void vega20_ih_irq_rearm(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) { … } /** * vega20_ih_set_rptr - set the IH ring buffer rptr * * @adev: amdgpu_device pointer * @ih: amdgpu_ih_ring pointer * * Set the IH ring buffer rptr. */ static void vega20_ih_set_rptr(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) { … } /** * vega20_ih_self_irq - dispatch work for ring 1 and 2 * * @adev: amdgpu_device pointer * @source: irq source * @entry: IV with WPTR update * * Update the WPTR from the IV and schedule work to handle the entries. */ static int vega20_ih_self_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { … } static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = …; static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev) { … } static int vega20_ih_early_init(void *handle) { … } static int vega20_ih_sw_init(void *handle) { … } static int vega20_ih_sw_fini(void *handle) { … } static int vega20_ih_hw_init(void *handle) { … } static int vega20_ih_hw_fini(void *handle) { … } static int vega20_ih_suspend(void *handle) { … } static int vega20_ih_resume(void *handle) { … } static bool vega20_ih_is_idle(void *handle) { … } static int vega20_ih_wait_for_idle(void *handle) { … } static int vega20_ih_soft_reset(void *handle) { … } static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev, bool enable) { … } static int vega20_ih_set_clockgating_state(void *handle, enum amd_clockgating_state state) { … } static int vega20_ih_set_powergating_state(void *handle, enum amd_powergating_state state) { … } const struct amd_ip_funcs vega20_ih_ip_funcs = …; static const struct amdgpu_ih_funcs vega20_ih_funcs = …; static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev) { … } const struct amdgpu_ip_block_version vega20_ih_ip_block = …;
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