linux/drivers/gpu/drm/amd/amdgpu/cz_ih.c

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include <linux/pci.h>

#include "amdgpu.h"
#include "amdgpu_ih.h"
#include "vid.h"

#include "oss/oss_3_0_1_d.h"
#include "oss/oss_3_0_1_sh_mask.h"

#include "bif/bif_5_1_d.h"
#include "bif/bif_5_1_sh_mask.h"

/*
 * Interrupts
 * Starting with r6xx, interrupts are handled via a ring buffer.
 * Ring buffers are areas of GPU accessible memory that the GPU
 * writes interrupt vectors into and the host reads vectors out of.
 * There is a rptr (read pointer) that determines where the
 * host is currently reading, and a wptr (write pointer)
 * which determines where the GPU has written.  When the
 * pointers are equal, the ring is idle.  When the GPU
 * writes vectors to the ring buffer, it increments the
 * wptr.  When there is an interrupt, the host then starts
 * fetching commands and processing them until the pointers are
 * equal again at which point it updates the rptr.
 */

static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev);

/**
 * cz_ih_enable_interrupts - Enable the interrupt ring buffer
 *
 * @adev: amdgpu_device pointer
 *
 * Enable the interrupt ring buffer (VI).
 */
static void cz_ih_enable_interrupts(struct amdgpu_device *adev)
{ … }

/**
 * cz_ih_disable_interrupts - Disable the interrupt ring buffer
 *
 * @adev: amdgpu_device pointer
 *
 * Disable the interrupt ring buffer (VI).
 */
static void cz_ih_disable_interrupts(struct amdgpu_device *adev)
{ … }

/**
 * cz_ih_irq_init - init and enable the interrupt ring
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate a ring buffer for the interrupt controller,
 * enable the RLC, disable interrupts, enable the IH
 * ring buffer and enable it (VI).
 * Called at device load and reume.
 * Returns 0 for success, errors for failure.
 */
static int cz_ih_irq_init(struct amdgpu_device *adev)
{ … }

/**
 * cz_ih_irq_disable - disable interrupts
 *
 * @adev: amdgpu_device pointer
 *
 * Disable interrupts on the hw (VI).
 */
static void cz_ih_irq_disable(struct amdgpu_device *adev)
{ … }

/**
 * cz_ih_get_wptr - get the IH ring buffer wptr
 *
 * @adev: amdgpu_device pointer
 * @ih: IH ring buffer to fetch wptr
 *
 * Get the IH ring buffer wptr from either the register
 * or the writeback memory buffer (VI).  Also check for
 * ring buffer overflow and deal with it.
 * Used by cz_irq_process(VI).
 * Returns the value of the wptr.
 */
static u32 cz_ih_get_wptr(struct amdgpu_device *adev,
			  struct amdgpu_ih_ring *ih)
{ … }

/**
 * cz_ih_decode_iv - decode an interrupt vector
 *
 * @adev: amdgpu_device pointer
 * @ih: IH ring buffer to decode
 * @entry: IV entry to place decoded information into
 *
 * Decodes the interrupt vector at the current rptr
 * position and also advance the position.
 */
static void cz_ih_decode_iv(struct amdgpu_device *adev,
			    struct amdgpu_ih_ring *ih,
			    struct amdgpu_iv_entry *entry)
{ … }

/**
 * cz_ih_set_rptr - set the IH ring buffer rptr
 *
 * @adev: amdgpu_device pointer
 * @ih: IH ring buffer to set rptr
 *
 * Set the IH ring buffer rptr.
 */
static void cz_ih_set_rptr(struct amdgpu_device *adev,
			   struct amdgpu_ih_ring *ih)
{ … }

static int cz_ih_early_init(void *handle)
{ … }

static int cz_ih_sw_init(void *handle)
{ … }

static int cz_ih_sw_fini(void *handle)
{ … }

static int cz_ih_hw_init(void *handle)
{ … }

static int cz_ih_hw_fini(void *handle)
{ … }

static int cz_ih_suspend(void *handle)
{ … }

static int cz_ih_resume(void *handle)
{ … }

static bool cz_ih_is_idle(void *handle)
{ … }

static int cz_ih_wait_for_idle(void *handle)
{ … }

static int cz_ih_soft_reset(void *handle)
{ … }

static int cz_ih_set_clockgating_state(void *handle,
					  enum amd_clockgating_state state)
{ … }

static int cz_ih_set_powergating_state(void *handle,
					  enum amd_powergating_state state)
{ … }

static const struct amd_ip_funcs cz_ih_ip_funcs = …;

static const struct amdgpu_ih_funcs cz_ih_funcs = …;

static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev)
{ … }

const struct amdgpu_ip_block_version cz_ih_ip_block = …;