// SPDX-License-Identifier: GPL-2.0-only #define pr_fmt(fmt) … #include <linux/clk.h> #include <linux/clockchips.h> #include <linux/cpu.h> #include <linux/cpuhotplug.h> #include <linux/cpumask.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/jiffies.h> #include <linux/printk.h> #include <linux/sched_clock.h> #include "timer-of.h" #define RTTM_DATA … #define RTTM_CNT … #define RTTM_CTRL … #define RTTM_INT … #define RTTM_CTRL_ENABLE … #define RTTM_INT_PENDING … #define RTTM_INT_ENABLE … /* * The Otto platform provides multiple 28 bit timers/counters with the following * operating logic. If enabled the timer counts up. Per timer one can set a * maximum counter value as an end marker. If end marker is reached the timer * fires an interrupt. If the timer "overflows" by reaching the end marker or * by adding 1 to 0x0fffffff the counter is reset to 0. When this happens and * the timer is in operating mode COUNTER it stops. In mode TIMER it will * continue to count up. */ #define RTTM_CTRL_COUNTER … #define RTTM_CTRL_TIMER … #define RTTM_BIT_COUNT … #define RTTM_MIN_DELTA … #define RTTM_MAX_DELTA … /* * Timers are derived from the LXB clock frequency. Usually this is a fixed * multiple of the 25 MHz oscillator. The 930X SOC is an exception from that. * Its LXB clock has only dividers and uses the switch PLL of 2.45 GHz as its * base. The only meaningful frequencies we can achieve from that are 175.000 * MHz and 153.125 MHz. The greatest common divisor of all explained possible * speeds is 3125000. Pin the timers to this 3.125 MHz reference frequency. */ #define RTTM_TICKS_PER_SEC … struct rttm_cs { … }; /* Simple internal register functions */ static inline void rttm_set_counter(void __iomem *base, unsigned int counter) { … } static inline unsigned int rttm_get_counter(void __iomem *base) { … } static inline void rttm_set_period(void __iomem *base, unsigned int period) { … } static inline void rttm_disable_timer(void __iomem *base) { … } static inline void rttm_enable_timer(void __iomem *base, u32 mode, u32 divisor) { … } static inline void rttm_ack_irq(void __iomem *base) { … } static inline void rttm_enable_irq(void __iomem *base) { … } static inline void rttm_disable_irq(void __iomem *base) { … } /* Aggregated control functions for kernel clock framework */ #define RTTM_DEBUG(base) … static irqreturn_t rttm_timer_interrupt(int irq, void *dev_id) { … } static void rttm_stop_timer(void __iomem *base) { … } static void rttm_start_timer(struct timer_of *to, u32 mode) { … } static int rttm_next_event(unsigned long delta, struct clock_event_device *clkevt) { … } static int rttm_state_oneshot(struct clock_event_device *clkevt) { … } static int rttm_state_periodic(struct clock_event_device *clkevt) { … } static int rttm_state_shutdown(struct clock_event_device *clkevt) { … } static void rttm_setup_timer(void __iomem *base) { … } static u64 rttm_read_clocksource(struct clocksource *cs) { … } /* Module initialization part. */ static DEFINE_PER_CPU(struct timer_of, rttm_to) = …; static int rttm_enable_clocksource(struct clocksource *cs) { … } struct rttm_cs rttm_cs = …; static u64 notrace rttm_read_clock(void) { … } static int rttm_cpu_starting(unsigned int cpu) { … } static int __init rttm_probe(struct device_node *np) { … } TIMER_OF_DECLARE(otto_timer, "realtek,otto-timer", rttm_probe);
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