// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2024 Josua Mayer <[email protected]>
*
* DTS for SolidRun CN9130 Clearfog Base.
*
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "cn9130.dtsi"
#include "cn9130-sr-som.dtsi"
/*
* Instantiate the external CP115
*/
#define CP11X_NAME cp1
#define CP11X_BASE f4000000
#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f4600000
#define CP11X_PCIE1_BASE f4620000
#define CP11X_PCIE2_BASE f4640000
#include "armada-cp115.dtsi"
#undef CP11X_NAME
#undef CP11X_BASE
#undef CP11X_PCIEx_MEM_BASE
#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
/ {
model = "SolidRun CN9131 SolidWAN";
compatible = "solidrun,cn9131-solidwan",
"solidrun,cn9130-sr-som", "marvell,cn9130";
aliases {
ethernet0 = &cp1_eth1;
ethernet1 = &cp1_eth2;
ethernet2 = &cp0_eth1;
ethernet3 = &cp0_eth2;
ethernet4 = &cp0_eth0;
ethernet5 = &cp1_eth0;
gpio0 = &ap_gpio;
gpio1 = &cp0_gpio1;
gpio2 = &cp0_gpio2;
gpio3 = &cp1_gpio1;
gpio4 = &cp1_gpio2;
gpio5 = &expander0;
i2c0 = &cp0_i2c0;
i2c1 = &cp0_i2c1;
i2c2 = &cp1_i2c1;
mmc0 = &ap_sdhci0;
mmc1 = &cp0_sdhci0;
rtc0 = &cp0_rtc;
rtc1 = &carrier_rtc;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&cp0_led_pins &cp1_led_pins>;
/* for sfp-1 (J42) */
led-sfp1-activity {
label = "sfp1:green";
gpios = <&cp0_gpio1 7 GPIO_ACTIVE_HIGH>;
};
/* for sfp-1 (J42) */
led-sfp1-link {
label = "sfp1:yellow";
gpios = <&cp0_gpio1 4 GPIO_ACTIVE_HIGH>;
};
/* (J28) */
led-sfp0-activity {
label = "sfp0:green";
gpios = <&cp1_gpio2 22 GPIO_ACTIVE_HIGH>;
};
/* (J28) */
led-sfp0-link {
label = "sfp0:yellow";
gpios = <&cp1_gpio2 23 GPIO_ACTIVE_HIGH>;
};
};
/* Type-A port on J53 */
reg_usb_a_vbus0: regulator-usb-a-vbus0 {
compatible = "regulator-fixed";
pinctrl-0 = <&cp0_reg_usb_a_vbus0_pins>;
pinctrl-names = "default";
regulator-name = "vbus0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpios = <&cp0_gpio1 27 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_usb_a_vbus1: regulator-usb-a-vbus1 {
compatible = "regulator-fixed";
pinctrl-0 = <&cp0_reg_usb_a_vbus1_pins>;
pinctrl-names = "default";
regulator-name = "vbus1";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpios = <&cp0_gpio1 28 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
sfp0: sfp-0 {
compatible = "sff,sfp";
pinctrl-0 = <&cp0_sfp0_pins>;
pinctrl-names = "default";
i2c-bus = <&cp0_i2c1>;
los-gpios = <&cp0_gpio2 2 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&cp0_gpio2 1 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&cp0_gpio1 31 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <2000>;
};
sfp1: sfp-1 {
compatible = "sff,sfp";
pinctrl-0 = <&cp1_sfp1_pins>;
pinctrl-names = "default";
i2c-bus = <&cp1_i2c1>;
los-gpios = <&cp1_gpio2 2 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&cp1_gpio2 18 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&cp1_gpio2 1 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&cp1_gpio2 17 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <2000>;
};
};
&cp0_ethernet {
status = "okay";
};
/* SRDS #2 - SFP+ 10GE */
&cp0_eth0 {
managed = "in-band-status";
phy-mode = "10gbase-r";
phys = <&cp0_comphy2 0>;
sfp = <&sfp0>;
status = "okay";
};
/* SRDS #3 - SGMII 1GE */
&cp0_eth1 {
managed = "in-band-status";
phy-mode = "sgmii";
/* Without mdio phy access rely on sgmii auto-negotiation. */
phys = <&cp0_comphy3 1>;
status = "okay";
};
/* SRDS #1 - SGMII */
&cp0_eth2 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
managed = "in-band-status";
phy-mode = "sgmii";
phy = <&cp0_phy1>;
phys = <&cp0_comphy1 2>;
};
&cp0_gpio1 {
pcie0-0-w-disable-hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_LOW>;
output-low;
line-name = "pcie0.0-w-disable";
};
/* J34 */
m2-full-card-power-off-hog {
gpio-hog;
gpios = <8 GPIO_ACTIVE_LOW>;
output-low;
line-name = "m2-full-card-power-off";
};
};
&cp0_i2c0 {
/* assembly option */
fan-controller@18 {
compatible = "ti,amc6821";
reg = <0x18>;
};
expander0: gpio@41 {
compatible = "nxp,pca9536";
reg = <0x41>;
usb-a-vbus0-ilimit-hog {
gpio-hog;
gpios = <0 GPIO_ACTIVE_LOW>;
input;
line-name = "vbus0-ilimit";
};
/* duplicate connection, controlled by soc gpio */
usb-vbus0-enable-hog {
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
input;
line-name = "vbus0-enable";
};
usb-a-vbus1-ilimit-hog {
gpio-hog;
gpios = <2 GPIO_ACTIVE_LOW>;
input;
line-name = "vbus1-ilimit";
};
/* duplicate connection, controlled by soc gpio */
usb-vbus1-enable-hog {
gpio-hog;
gpios = <3 GPIO_ACTIVE_HIGH>;
input;
line-name = "vbus1-enable";
};
};
carrier_eeprom: eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <8>;
};
/* usb-hub@60 */
/* assembly option */
carrier_rtc: rtc@68 {
compatible = "st,m41t83";
reg = <0x68>;
pinctrl-0 = <&cp1_rtc_pins>;
pinctrl-names = "default";
interrupt-parent = <&cp1_gpio1>;
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&cp1_gpio1 13 GPIO_ACTIVE_LOW>;
};
};
&cp0_i2c1 {
/*
* Routed to SFP.
* Limit to 100kHz for compatibility with SFP modules,
* featuring AT24C01A/02/04 at addresses 0x50/0x51.
*/
clock-frequency = <100000>;
pinctrl-0 = <&cp0_i2c1_pins>;
pinctrl-names = "default";
status = "okay";
};
&cp0_mdio {
/*
* SoM + Carrier each have a PHY at address 0.
* Remove the SoM phy node, and skip adding the carrier node.
* SGMII Auto-Negotation is enabled by bootloader for
* autonomous operation without mdio control.
*/
/delete-node/ ethernet-phy@0;
/* U17016 */
cp0_phy1: ethernet-phy@1 {
reg = <1>;
/*
* Configure LEDs default behaviour:
* - LED[0]: link is 1000Mbps: On (yellow)
* - LED[1]: link/activity: On/blink (green)
* - LED[2]: high impedance (floating)
*/
marvell,reg-init = <3 16 0xf000 0x0a17>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_LAN;
default-state = "keep";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
default-state = "keep";
};
};
};
};
/* SRDS #0 - miniPCIe */
&cp0_pcie0 {
num-lanes = <1>;
phys = <&cp0_comphy0 0>;
status = "okay";
};
/* SRDS #5 - M.2 B-Key (J34) */
&cp0_pcie2 {
num-lanes = <1>;
phys = <&cp0_comphy5 2>;
status = "okay";
};
&cp0_pinctrl {
pinctrl-0 = <&cp0_m2_0_shutdown_pins &cp0_mpcie_rfkill_pins>;
pinctrl-names = "default";
cp0_i2c1_pins: cp0-i2c1-pins {
marvell,pins = "mpp35", "mpp36";
marvell,function = "i2c1";
};
cp0_led_pins: cp0-led-pins {
marvell,pins = "mpp4", "mpp7";
marvell,function = "gpio";
};
cp0_m2_0_shutdown_pins: cp0-m2-0-shutdown-pins {
marvell,pins = "mpp8";
marvell,function = "gpio";
};
cp0_mmc0_pins: cp0-mmc0-pins {
marvell,pins = "mpp43", "mpp56", "mpp57", "mpp58",
"mpp59", "mpp60", "mpp61";
marvell,function = "sdio";
};
cp0_mpcie_rfkill_pins: cp0-mpcie-rfkill-pins {
marvell,pins = "mpp6";
marvell,function = "gpio";
};
cp0_reg_usb_a_vbus0_pins: cp0-reg-usb-a-vbus0-pins {
marvell,pins = "mpp27";
marvell,function = "gpio";
};
cp0_reg_usb_a_vbus1_pins: cp0-reg-usb-a-vbus1-pins {
marvell,pins = "mpp28";
marvell,function = "gpio";
};
cp0_sfp0_pins: cp0-sfp0-pins {
marvell,pins = "mpp31", "mpp32", "mpp33", "mpp34";
marvell,function = "gpio";
};
cp0_spi1_cs1_pins: cp0-spi1-cs1-pins {
marvell,pins = "mpp12";
marvell,function = "spi1";
};
};
/* microSD */
&cp0_sdhci0 {
pinctrl-0 = <&cp0_mmc0_pins>;
pinctrl-names = "default";
bus-width = <4>;
no-1-8-v;
status = "okay";
};
&cp0_spi1 {
/* add pin for chip-select 1 */
pinctrl-0 = <&cp0_spi1_pins &cp0_spi1_cs1_pins>;
flash@1 {
compatible = "jedec,spi-nor";
reg = <1>;
/* read command supports max. 50MHz */
spi-max-frequency = <50000000>;
};
};
/* USB-2.0 Host to USB-Hub */
&cp0_usb3_0 {
phys = <&cp0_utmi0>;
phy-names = "utmi";
dr_mode = "host";
status = "okay";
};
/* SRDS #4 - USB-3.0 Host to USB-Hub */
&cp0_usb3_1 {
phys = <&cp0_comphy4 1>, <&cp0_utmi1>;
phy-names = "comphy", "utmi";
dr_mode = "host";
status = "okay";
};
&cp0_utmi {
status = "okay";
};
&cp0_utmi1 {
status = "disabled";
};
&cp1_ethernet {
status = "okay";
};
/* SRDS #4 - SFP+ 10GE */
&cp1_eth0 {
managed = "in-band-status";
phy-mode = "10gbase-r";
phys = <&cp1_comphy4 0>;
sfp = <&sfp1>;
status = "okay";
};
/* SRDS #3 - SGMII 1GE */
&cp1_eth1 {
managed = "in-band-status";
phy-mode = "sgmii";
phy = <&cp1_phy0>;
phys = <&cp0_comphy3 1>;
status = "okay";
};
/* SRDS #5 - SGMII 1GE */
&cp1_eth2 {
managed = "in-band-status";
phy-mode = "sgmii";
phy = <&cp1_phy1>;
phys = <&cp0_comphy5 2>;
status = "okay";
};
&cp1_gpio1 {
status = "okay";
/* J30 */
m2-full-card-power-off-hog-0 {
gpio-hog;
gpios = <29 GPIO_ACTIVE_LOW>;
output-low;
line-name = "m2-full-card-power-off";
};
/* J44 */
m2-full-card-power-off-hog-1 {
gpio-hog;
gpios = <30 GPIO_ACTIVE_LOW>;
output-low;
line-name = "m2-full-card-power-off";
};
};
&cp1_gpio2 {
status = "okay";
};
&cp1_i2c1 {
/*
* Routed to SFP.
* Limit to 100kHz for compatibility with SFP modules,
* featuring AT24C01A/02/04 at addresses 0x50/0x51.
*/
clock-frequency = <100000>;
pinctrl-0 = <&cp1_i2c1_pins>;
pinctrl-names = "default";
status = "okay";
};
&cp1_mdio {
pinctrl-0 = <&cp1_mdio_pins>;
pinctrl-names = "default";
status = "okay";
cp1_phy0: ethernet-phy@0 {
reg = <0>;
/*
* Configure LEDs default behaviour:
* - LED[0]: link is 1000Mbps: On (yellow)
* - LED[1]: link/activity: On/blink (green)
* - LED[2]: high impedance (floating)
*/
marvell,reg-init = <3 16 0xf000 0x0a17>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_LAN;
default-state = "keep";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
default-state = "keep";
};
};
};
cp1_phy1: ethernet-phy@1 {
reg = <1>;
/*
* Configure LEDs default behaviour:
* - LED[0]: link is 1000Mbps: On (yellow)
* - LED[1]: link/activity: On/blink (green)
* - LED[2]: high impedance (floating)
*/
marvell,reg-init = <3 16 0xf000 0x0a17>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_LAN;
default-state = "keep";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
default-state = "keep";
};
};
};
};
/* SRDS #0 - M.2 (J30) */
&cp1_pcie0 {
num-lanes = <1>;
phys = <&cp1_comphy0 0>;
status = "okay";
};
&cp1_rtc {
status = "disabled";
};
/* SRDS #1 - SATA on M.2 (J44) */
&cp1_sata0 {
phys = <&cp1_comphy1 0>;
status = "okay";
/* only port 0 is available */
/delete-node/ sata-port@1;
};
&cp1_syscon0 {
cp1_pinctrl: pinctrl {
compatible = "marvell,cp115-standalone-pinctrl";
pinctrl-0 = <&cp1_m2_1_shutdown_pins &cp1_m2_2_shutdown_pins>;
pinctrl-names = "default";
cp1_i2c1_pins: cp0-i2c1-pins {
marvell,pins = "mpp35", "mpp36";
marvell,function = "i2c1";
};
cp1_led_pins: cp1-led-pins {
marvell,pins = "mpp54", "mpp55";
marvell,function = "gpio";
};
cp1_m2_1_shutdown_pins: cp1-m2-1-shutdown-pins {
marvell,pins = "mpp29";
marvell,function = "gpio";
};
cp1_m2_2_shutdown_pins: cp1-m2-2-shutdown-pins {
marvell,pins = "mpp30";
marvell,function = "gpio";
};
cp1_mdio_pins: cp1-mdio-pins {
marvell,pins = "mpp37", "mpp38";
marvell,function = "ge";
};
cp1_rtc_pins: cp1-rtc-pins {
marvell,pins = "mpp12", "mpp13";
marvell,function = "gpio";
};
cp1_sfp1_pins: cp1-sfp1-pins {
marvell,pins = "mpp33", "mpp34", "mpp49", "mpp50";
marvell,function = "gpio";
};
};
};
/*
* SRDS #2 - USB-3.0 Host to M.2 (J44)
* USB-2.0 Host to M.2 (J30)
*/
&cp1_usb3_0 {
phys = <&cp1_comphy2 0>, <&cp1_utmi0>;
phy-names = "comphy", "utmi";
dr_mode = "host";
status = "okay";
};
/* USB-2.0 Host to M.2 (J44) */
&cp1_usb3_1 {
phys = <&cp1_utmi1>;
phy-names = "utmi";
dr_mode = "host";
status = "okay";
};
&cp1_utmi {
status = "okay";
};
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