/* * Copyright 2013 Intel Corporation * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #ifndef _I915_PCIIDS_H #define _I915_PCIIDS_H /* * A pci_device_id struct { * __u32 vendor, device; * __u32 subvendor, subdevice; * __u32 class, class_mask; * kernel_ulong_t driver_data; * }; * Don't use C99 here because "class" is reserved and we want to * give userspace flexibility. */ #define INTEL_VGA_DEVICE(id, info) … #define INTEL_QUANTA_VGA_DEVICE(info) … #define INTEL_I810_IDS(MACRO__, ...) … #define INTEL_I815_IDS(MACRO__, ...) … #define INTEL_I830_IDS(MACRO__, ...) … #define INTEL_I845G_IDS(MACRO__, ...) … #define INTEL_I85X_IDS(MACRO__, ...) … #define INTEL_I865G_IDS(MACRO__, ...) … #define INTEL_I915G_IDS(MACRO__, ...) … #define INTEL_I915GM_IDS(MACRO__, ...) … #define INTEL_I945G_IDS(MACRO__, ...) … #define INTEL_I945GM_IDS(MACRO__, ...) … #define INTEL_I965G_IDS(MACRO__, ...) … #define INTEL_G33_IDS(MACRO__, ...) … #define INTEL_I965GM_IDS(MACRO__, ...) … #define INTEL_GM45_IDS(MACRO__, ...) … #define INTEL_G45_IDS(MACRO__, ...) … #define INTEL_PNV_G_IDS(MACRO__, ...) … #define INTEL_PNV_M_IDS(MACRO__, ...) … #define INTEL_PNV_IDS(MACRO__, ...) … #define INTEL_ILK_D_IDS(MACRO__, ...) … #define INTEL_ILK_M_IDS(MACRO__, ...) … #define INTEL_ILK_IDS(MACRO__, ...) … #define INTEL_SNB_D_GT1_IDS(MACRO__, ...) … #define INTEL_SNB_D_GT2_IDS(MACRO__, ...) … #define INTEL_SNB_D_IDS(MACRO__, ...) … #define INTEL_SNB_M_GT1_IDS(MACRO__, ...) … #define INTEL_SNB_M_GT2_IDS(MACRO__, ...) … #define INTEL_SNB_M_IDS(MACRO__, ...) … #define INTEL_SNB_IDS(MACRO__, ...) … #define INTEL_IVB_M_GT1_IDS(MACRO__, ...) … #define INTEL_IVB_M_GT2_IDS(MACRO__, ...) … #define INTEL_IVB_M_IDS(MACRO__, ...) … #define INTEL_IVB_D_GT1_IDS(MACRO__, ...) … #define INTEL_IVB_D_GT2_IDS(MACRO__, ...) … #define INTEL_IVB_D_IDS(MACRO__, ...) … #define INTEL_IVB_IDS(MACRO__, ...) … #define INTEL_IVB_Q_IDS(MACRO__, ...) … #define INTEL_HSW_ULT_GT1_IDS(MACRO__, ...) … #define INTEL_HSW_ULX_GT1_IDS(MACRO__, ...) … #define INTEL_HSW_GT1_IDS(MACRO__, ...) … #define INTEL_HSW_ULT_GT2_IDS(MACRO__, ...) … \ #define INTEL_HSW_ULX_GT2_IDS(MACRO__, ...) … \ #define INTEL_HSW_GT2_IDS(MACRO__, ...) … #define INTEL_HSW_ULT_GT3_IDS(MACRO__, ...) … #define INTEL_HSW_GT3_IDS(MACRO__, ...) … #define INTEL_HSW_IDS(MACRO__, ...) … #define INTEL_VLV_IDS(MACRO__, ...) … #define INTEL_BDW_ULT_GT1_IDS(MACRO__, ...) … #define INTEL_BDW_ULX_GT1_IDS(MACRO__, ...) … #define INTEL_BDW_GT1_IDS(MACRO__, ...) … #define INTEL_BDW_ULT_GT2_IDS(MACRO__, ...) … #define INTEL_BDW_ULX_GT2_IDS(MACRO__, ...) … #define INTEL_BDW_GT2_IDS(MACRO__, ...) … #define INTEL_BDW_ULT_GT3_IDS(MACRO__, ...) … \ #define INTEL_BDW_ULX_GT3_IDS(MACRO__, ...) … #define INTEL_BDW_GT3_IDS(MACRO__, ...) … #define INTEL_BDW_ULT_RSVD_IDS(MACRO__, ...) … #define INTEL_BDW_ULX_RSVD_IDS(MACRO__, ...) … #define INTEL_BDW_RSVD_IDS(MACRO__, ...) … #define INTEL_BDW_IDS(MACRO__, ...) … #define INTEL_CHV_IDS(MACRO__, ...) … #define INTEL_SKL_ULT_GT1_IDS(MACRO__, ...) … #define INTEL_SKL_ULX_GT1_IDS(MACRO__, ...) … #define INTEL_SKL_GT1_IDS(MACRO__, ...) … #define INTEL_SKL_ULT_GT2_IDS(MACRO__, ...) … #define INTEL_SKL_ULX_GT2_IDS(MACRO__, ...) … #define INTEL_SKL_GT2_IDS(MACRO__, ...) … #define INTEL_SKL_ULT_GT3_IDS(MACRO__, ...) … #define INTEL_SKL_GT3_IDS(MACRO__, ...) … #define INTEL_SKL_GT4_IDS(MACRO__, ...) … #define INTEL_SKL_IDS(MACRO__, ...) … #define INTEL_BXT_IDS(MACRO__, ...) … #define INTEL_GLK_IDS(MACRO__, ...) … #define INTEL_KBL_ULT_GT1_IDS(MACRO__, ...) … #define INTEL_KBL_ULX_GT1_IDS(MACRO__, ...) … #define INTEL_KBL_GT1_IDS(MACRO__, ...) … #define INTEL_KBL_ULT_GT2_IDS(MACRO__, ...) … #define INTEL_KBL_ULX_GT2_IDS(MACRO__, ...) … #define INTEL_KBL_GT2_IDS(MACRO__, ...) … #define INTEL_KBL_ULT_GT3_IDS(MACRO__, ...) … #define INTEL_KBL_GT3_IDS(MACRO__, ...) … #define INTEL_KBL_GT4_IDS(MACRO__, ...) … /* AML/KBL Y GT2 */ #define INTEL_AML_KBL_GT2_IDS(MACRO__, ...) … /* AML/CFL Y GT2 */ #define INTEL_AML_CFL_GT2_IDS(MACRO__, ...) … /* CML GT1 */ #define INTEL_CML_GT1_IDS(MACRO__, ...) … #define INTEL_CML_U_GT1_IDS(MACRO__, ...) … /* CML GT2 */ #define INTEL_CML_GT2_IDS(MACRO__, ...) … #define INTEL_CML_U_GT2_IDS(MACRO__, ...) … #define INTEL_CML_IDS(MACRO__, ...) … #define INTEL_KBL_IDS(MACRO__, ...) … /* CFL S */ #define INTEL_CFL_S_GT1_IDS(MACRO__, ...) … #define INTEL_CFL_S_GT2_IDS(MACRO__, ...) … /* CFL H */ #define INTEL_CFL_H_GT1_IDS(MACRO__, ...) … #define INTEL_CFL_H_GT2_IDS(MACRO__, ...) … /* CFL U GT2 */ #define INTEL_CFL_U_GT2_IDS(MACRO__, ...) … /* CFL U GT3 */ #define INTEL_CFL_U_GT3_IDS(MACRO__, ...) … #define INTEL_CFL_IDS(MACRO__, ...) … /* WHL/CFL U GT1 */ #define INTEL_WHL_U_GT1_IDS(MACRO__, ...) … /* WHL/CFL U GT2 */ #define INTEL_WHL_U_GT2_IDS(MACRO__, ...) … /* WHL/CFL U GT3 */ #define INTEL_WHL_U_GT3_IDS(MACRO__, ...) … #define INTEL_WHL_IDS(MACRO__, ...) … /* CNL */ #define INTEL_CNL_PORT_F_IDS(MACRO__, ...) … #define INTEL_CNL_IDS(MACRO__, ...) … /* ICL */ #define INTEL_ICL_PORT_F_IDS(MACRO__, ...) … #define INTEL_ICL_IDS(MACRO__, ...) … /* EHL */ #define INTEL_EHL_IDS(MACRO__, ...) … /* JSL */ #define INTEL_JSL_IDS(MACRO__, ...) … /* TGL */ #define INTEL_TGL_GT1_IDS(MACRO__, ...) … #define INTEL_TGL_GT2_IDS(MACRO__, ...) … #define INTEL_TGL_IDS(MACRO__, ...) … /* RKL */ #define INTEL_RKL_IDS(MACRO__, ...) … /* DG1 */ #define INTEL_DG1_IDS(MACRO__, ...) … /* ADL-S */ #define INTEL_ADLS_IDS(MACRO__, ...) … /* ADL-P */ #define INTEL_ADLP_IDS(MACRO__, ...) … /* ADL-N */ #define INTEL_ADLN_IDS(MACRO__, ...) … /* RPL-S */ #define INTEL_RPLS_IDS(MACRO__, ...) … /* RPL-U */ #define INTEL_RPLU_IDS(MACRO__, ...) … /* RPL-P */ #define INTEL_RPLP_IDS(MACRO__, ...) … /* DG2 */ #define INTEL_DG2_G10_IDS(MACRO__, ...) … #define INTEL_DG2_G11_IDS(MACRO__, ...) … #define INTEL_DG2_G12_IDS(MACRO__, ...) … #define INTEL_DG2_IDS(MACRO__, ...) … #define INTEL_ATS_M150_IDS(MACRO__, ...) … #define INTEL_ATS_M75_IDS(MACRO__, ...) … #define INTEL_ATS_M_IDS(MACRO__, ...) … /* MTL */ #define INTEL_MTL_IDS(MACRO__, ...) … /* LNL */ #define INTEL_LNL_IDS(MACRO__, ...) … /* BMG */ #define INTEL_BMG_IDS(MACRO__, ...) … #endif /* _I915_PCIIDS_H */
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