// SPDX-License-Identifier: GPL-2.0+ /* * PCIe host controller driver for StarFive JH7110 Soc. * * Copyright (C) 2023 StarFive Technology Co., Ltd. */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/gpio/consumer.h> #include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/of_pci.h> #include <linux/pci.h> #include <linux/phy/phy.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/reset.h> #include "../../pci.h" #include "pcie-plda.h" #define PCIE_FUNC_NUM … /* system control */ #define STG_SYSCON_PCIE0_BASE … #define STG_SYSCON_PCIE1_BASE … #define STG_SYSCON_AR_OFFSET … #define STG_SYSCON_AXI4_SLVL_AR_MASK … #define STG_SYSCON_AXI4_SLVL_PHY_AR(x) … #define STG_SYSCON_AW_OFFSET … #define STG_SYSCON_AXI4_SLVL_AW_MASK … #define STG_SYSCON_AXI4_SLVL_PHY_AW(x) … #define STG_SYSCON_CLKREQ … #define STG_SYSCON_CKREF_SRC_MASK … #define STG_SYSCON_RP_NEP_OFFSET … #define STG_SYSCON_K_RP_NEP … #define STG_SYSCON_LNKSTA_OFFSET … #define DATA_LINK_ACTIVE … /* Parameters for the waiting for link up routine */ #define LINK_WAIT_MAX_RETRIES … #define LINK_WAIT_USLEEP_MIN … #define LINK_WAIT_USLEEP_MAX … struct starfive_jh7110_pcie { … }; /* * JH7110 PCIe port BAR0/1 can be configured as 64-bit prefetchable memory * space. PCIe read and write requests targeting BAR0/1 are routed to so called * 'Bridge Configuration space' in PLDA IP datasheet, which contains the bridge * internal registers, such as interrupt, DMA and ATU registers... * JH7110 can access the Bridge Configuration space by local bus, and don`t * want the bridge internal registers accessed by the DMA from EP devices. * Thus, they are unimplemented and should be hidden here. */ static bool starfive_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn, int offset) { … } static int starfive_pcie_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) { … } static int starfive_pcie_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) { … } static int starfive_pcie_parse_dt(struct starfive_jh7110_pcie *pcie, struct device *dev) { … } static struct pci_ops starfive_pcie_ops = …; static int starfive_pcie_clk_rst_init(struct starfive_jh7110_pcie *pcie) { … } static void starfive_pcie_clk_rst_deinit(struct starfive_jh7110_pcie *pcie) { … } static bool starfive_pcie_link_up(struct plda_pcie_rp *plda) { … } static int starfive_pcie_host_wait_for_link(struct starfive_jh7110_pcie *pcie) { … } static int starfive_pcie_enable_phy(struct device *dev, struct starfive_jh7110_pcie *pcie) { … } static void starfive_pcie_disable_phy(struct starfive_jh7110_pcie *pcie) { … } static void starfive_pcie_host_deinit(struct plda_pcie_rp *plda) { … } static int starfive_pcie_host_init(struct plda_pcie_rp *plda) { … } static const struct plda_pcie_host_ops sf_host_ops = …; static const struct plda_event stf_pcie_event = …; static int starfive_pcie_probe(struct platform_device *pdev) { … } static void starfive_pcie_remove(struct platform_device *pdev) { … } static int starfive_pcie_suspend_noirq(struct device *dev) { … } static int starfive_pcie_resume_noirq(struct device *dev) { … } static const struct dev_pm_ops starfive_pcie_pm_ops = …; static const struct of_device_id starfive_pcie_of_match[] = …; MODULE_DEVICE_TABLE(of, starfive_pcie_of_match); static struct platform_driver starfive_pcie_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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