/* SPDX-License-Identifier: GPL-2.0-only */ /* * rt1318.h -- Platform data for RT1318 * * Copyright 2024 Realtek Semiconductor Corp. */ #include <sound/rt1318.h> #ifndef __RT1318_H__ #define __RT1318_H__ struct rt1318_priv { … }; #define RT1318_PLL_INP_MAX … #define RT1318_PLL_INP_MIN … #define RT1318_PLL_N_MAX … #define RT1318_PLL_K_MAX … #define RT1318_PLL_M_MAX … #define RT1318_LRCLK_192000 … #define RT1318_LRCLK_96000 … #define RT1318_LRCLK_48000 … #define RT1318_LRCLK_44100 … #define RT1318_LRCLK_16000 … #define RT1318_DVOL_STEP … #define RT1318_CLK1 … #define RT1318_CLK2 … #define RT1318_CLK3 … #define RT1318_CLK4 … #define RT1318_CLK5 … #define RT1318_CLK6 … #define RT1318_CLK7 … #define RT1318_PWR_STA1 … #define RT1318_SPK_VOL_TH … #define RT1318_TCON … #define RT1318_SRC_TCON … #define RT1318_TCON_RELATE … #define RT1318_DA_VOL_L_8 … #define RT1318_DA_VOL_L_1_7 … #define RT1318_DA_VOL_R_8 … #define RT1318_DA_VOL_R_1_7 … #define RT1318_FEEDBACK_PATH … #define RT1318_STP_TEMP_L … #define RT1318_STP_SEL_L … #define RT1318_STP_R0_EN_L … #define RT1318_R0_CMP_L_FLAG … #define RT1318_PRE_R0_L_24 … #define RT1318_PRE_R0_L_23_16 … #define RT1318_PRE_R0_L_15_8 … #define RT1318_PRE_R0_L_7_0 … #define RT1318_R0_L_24 … #define RT1318_R0_L_23_16 … #define RT1318_R0_L_15_8 … #define RT1318_R0_L_7_0 … #define RT1318_STP_SEL_R … #define RT1318_STP_R0_EN_R … #define RT1318_R0_CMP_R_FLAG … #define RT1318_PRE_R0_R_24 … #define RT1318_PRE_R0_R_23_16 … #define RT1318_PRE_R0_R_15_8 … #define RT1318_PRE_R0_R_7_0 … #define RT1318_R0_R_24 … #define RT1318_R0_R_23_16 … #define RT1318_R0_R_15_8 … #define RT1318_R0_R_7_0 … #define RT1318_DEV_ID1 … #define RT1318_DEV_ID2 … #define RT1318_PLL1_K … #define RT1318_PLL1_M … #define RT1318_PLL1_N_8 … #define RT1318_PLL1_N_7_0 … #define RT1318_SINE_GEN0 … #define RT1318_TDM_CTRL1 … #define RT1318_TDM_CTRL2 … #define RT1318_TDM_CTRL3 … #define RT1318_TDM_CTRL9 … /* Clock-1 (0xC001) */ #define RT1318_PLLIN_MASK … #define RT1318_PLLIN_BCLK0 … #define RT1318_PLLIN_BCLK1 … #define RT1318_PLLIN_RC … #define RT1318_PLLIN_MCLK … #define RT1318_PLLIN_SDW1 … #define RT1318_PLLIN_SDW2 … #define RT1318_PLLIN_SDW3 … #define RT1318_PLLIN_SDW4 … #define RT1318_SYSCLK_SEL_MASK … #define RT1318_SYSCLK_BCLK … #define RT1318_SYSCLK_SDW … #define RT1318_SYSCLK_PLL2F … #define RT1318_SYSCLK_PLL2B … #define RT1318_SYSCLK_MCLK … #define RT1318_SYSCLK_RC1 … #define RT1318_SYSCLK_RC2 … #define RT1318_SYSCLK_RC3 … /* Clock-2 (0xC003) */ #define RT1318_DIV_AP_MASK … #define RT1318_DIV_AP_SFT … #define RT1318_DIV_AP_DIV1 … #define RT1318_DIV_AP_DIV2 … #define RT1318_DIV_AP_DIV4 … #define RT1318_DIV_AP_DIV8 … #define RT1318_DIV_DAMOD_MASK … #define RT1318_DIV_DAMOD_SFT … #define RT1318_DIV_DAMOD_DIV1 … #define RT1318_DIV_DAMOD_DIV2 … #define RT1318_DIV_DAMOD_DIV4 … #define RT1318_DIV_DAMOD_DIV8 … /* Clock-3 (0xC004) */ #define RT1318_AD_STO1_MASK … #define RT1318_AD_STO1_SFT … #define RT1318_AD_STO1_DIV1 … #define RT1318_AD_STO1_DIV2 … #define RT1318_AD_STO1_DIV4 … #define RT1318_AD_STO1_DIV8 … #define RT1318_AD_STO1_DIV16 … #define RT1318_AD_STO2_MASK … #define RT1318_AD_STO2_SFT … #define RT1318_AD_STO2_DIV1 … #define RT1318_AD_STO2_DIV2 … #define RT1318_AD_STO2_DIV4 … #define RT1318_AD_STO2_DIV8 … #define RT1318_AD_STO2_DIV16 … #define RT1318_AD_STO2_SFT … /* Clock-4 (0xC005) */ #define RT1318_AD_ANA_STO1_MASK … #define RT1318_AD_ANA_STO1_SFT … #define RT1318_AD_ANA_STO1_DIV1 … #define RT1318_AD_ANA_STO1_DIV2 … #define RT1318_AD_ANA_STO1_DIV4 … #define RT1318_AD_ANA_STO1_DIV8 … #define RT1318_AD_ANA_STO1_DIV16 … #define RT1318_AD_ANA_STO2_MASK … #define RT1318_AD_ANA_STO2_DIV1 … #define RT1318_AD_ANA_STO2_DIV2 … #define RT1318_AD_ANA_STO2_DIV4 … #define RT1318_AD_ANA_STO2_DIV8 … #define RT1318_AD_ANA_STO2_DIV16 … #define RT1318_AD_ANA_STO2_SFT … /* Clock-5 (0xC006) */ #define RT1318_DIV_FIFO_IN_MASK … #define RT1318_DIV_FIFO_IN_SFT … #define RT1318_DIV_FIFO_IN_DIV1 … #define RT1318_DIV_FIFO_IN_DIV2 … #define RT1318_DIV_FIFO_IN_DIV4 … #define RT1318_DIV_FIFO_IN_DIV8 … #define RT1318_DIV_FIFO_OUT_MASK … #define RT1318_DIV_FIFO_OUT_DIV1 … #define RT1318_DIV_FIFO_OUT_DIV2 … #define RT1318_DIV_FIFO_OUT_DIV4 … #define RT1318_DIV_FIFO_OUT_DIV8 … #define RT1318_DIV_FIFO_OUT_SFT … /* Clock-6 (0xC007) */ #define RT1318_DIV_NLMS_MASK … #define RT1318_DIV_NLMS_SFT … #define RT1318_DIV_NLMS_DIV1 … #define RT1318_DIV_NLMS_DIV2 … #define RT1318_DIV_NLMS_DIV4 … #define RT1318_DIV_NLMS_DIV8 … #define RT1318_DIV_AD_MONO_MASK … #define RT1318_DIV_AD_MONO_SFT … #define RT1318_DIV_AD_MONO_DIV1 … #define RT1318_DIV_AD_MONO_DIV2 … #define RT1318_DIV_AD_MONO_DIV4 … #define RT1318_DIV_AD_MONO_DIV8 … #define RT1318_DIV_AD_MONO_DIV16 … #define RT1318_DIV_POST_G_MASK … #define RT1318_DIV_POST_G_SFT … #define RT1318_DIV_POST_G_DIV1 … #define RT1318_DIV_POST_G_DIV2 … #define RT1318_DIV_POST_G_DIV4 … #define RT1318_DIV_POST_G_DIV8 … #define RT1318_DIV_POST_G_DIV16 … /* Power Status 1 (0xC121) */ #define RT1318_PDB_CTRL_MASK … #define RT1318_PDB_CTRL_LOW … #define RT1318_PDB_CTRL_HIGH … #define RT1318_PDB_CTRL_SFT … /* SRC Tcon(0xc204) */ #define RT1318_SRCIN_IN_SEL_MASK … #define RT1318_SRCIN_IN_48K … #define RT1318_SRCIN_IN_44P1 … #define RT1318_SRCIN_IN_32K … #define RT1318_SRCIN_IN_16K … #define RT1318_SRCIN_F12288_MASK … #define RT1318_SRCIN_TCON1 … #define RT1318_SRCIN_TCON2 … #define RT1318_SRCIN_TCON4 … #define RT1318_SRCIN_TCON8 … #define RT1318_SRCIN_DACLK_MASK … #define RT1318_DACLK_TCON1 … #define RT1318_DACLK_TCON2 … #define RT1318_DACLK_TCON4 … #define RT1318_DACLK_TCON8 … /* R0 Compare Flag (0xDB35) */ #define RT1318_R0_RANGE_MASK … #define RT1318_R0_OUTOFRANGE … #define RT1318_R0_INRANGE … /* PLL internal setting (0xF20D), K value */ #define RT1318_K_PLL1_MASK … /* PLL internal setting (0xF20F), M value */ #define RT1318_M_PLL1_MASK … /* PLL internal setting (0xF211), N_8 value */ #define RT1318_N_8_PLL1_MASK … /* PLL internal setting (0xF212), N_7_0 value */ #define RT1318_N_7_0_PLL1_MASK … /* TDM CTRL 1 (0xf900) */ #define RT1318_TDM_BCLK_MASK … #define RT1318_TDM_BCLK_NORM … #define RT1318_TDM_BCLK_INV … #define RT1318_I2S_FMT_MASK … #define RT1318_FMT_I2S … #define RT1318_FMT_LEFT_J … #define RT1318_FMT_PCM_A_R … #define RT1318_FMT_PCM_B_R … #define RT1318_FMT_PCM_A_F … #define RT1318_FMT_PCM_B_F … #define RT1318_I2S_FMT_SFT … /* TDM CTRL 2 (0xf901) */ #define RT1318_I2S_CH_TX_MASK … #define RT1318_I2S_CH_TX_2CH … #define RT1318_I2S_CH_TX_4CH … #define RT1318_I2S_CH_TX_6CH … #define RT1318_I2S_CH_TX_8CH … #define RT1318_I2S_CH_RX_MASK … #define RT1318_I2S_CH_RX_2CH … #define RT1318_I2S_CH_RX_4CH … #define RT1318_I2S_CH_RX_6CH … #define RT1318_I2S_CH_RX_8CH … #define RT1318_I2S_DL_MASK … #define RT1318_I2S_DL_SFT … #define RT1318_I2S_DL_16 … #define RT1318_I2S_DL_20 … #define RT1318_I2S_DL_24 … #define RT1318_I2S_DL_32 … #define RT1318_I2S_DL_8 … /* TDM CTRL 3 (0xf902) */ #define RT1318_I2S_TX_CHL_MASK … #define RT1318_I2S_TX_CHL_SFT … #define RT1318_I2S_TX_CHL_16 … #define RT1318_I2S_TX_CHL_20 … #define RT1318_I2S_TX_CHL_24 … #define RT1318_I2S_TX_CHL_32 … #define RT1318_I2S_TX_CHL_8 … #define RT1318_I2S_RX_CHL_MASK … #define RT1318_I2S_RX_CHL_SFT … #define RT1318_I2S_RX_CHL_16 … #define RT1318_I2S_RX_CHL_20 … #define RT1318_I2S_RX_CHL_24 … #define RT1318_I2S_RX_CHL_32 … #define RT1318_I2S_RX_CHL_8 … /* TDM CTRL 9 (0xf908) */ #define RT1318_TDM_I2S_TX_L_DAC1_1_MASK … #define RT1318_TDM_I2S_TX_R_DAC1_1_MASK … #define RT1318_TDM_I2S_TX_L_DAC1_1_SFT … #define RT1318_TDM_I2S_TX_R_DAC1_1_SFT … #define RT1318_REG_DISP_LEN … /* System Clock Source */ enum { … }; /* PLL Source */ enum { … }; /* TDM channel */ enum { … }; /* R0 calibration result */ enum { … }; /* PLL pre-defined M/N/K */ struct pll_calc_map { … }; struct rt1318_pll_code { … }; #endif /* __RT1318_H__ */
Codebase Browser
linux