/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Copyright (C) 2024 ROHM Semiconductors */ #ifndef __MFD_BD96801_H__ #define __MFD_BD96801_H__ #define BD96801_REG_SSCG_CTRL … #define BD96801_REG_SHD_INTB … #define BD96801_LDO5_VOL_LVL_REG … #define BD96801_LDO6_VOL_LVL_REG … #define BD96801_LDO7_VOL_LVL_REG … #define BD96801_REG_BUCK_OVP … #define BD96801_REG_BUCK_OVD … #define BD96801_REG_LDO_OVP … #define BD96801_REG_LDO_OVD … #define BD96801_REG_BOOT_OVERTIME … #define BD96801_REG_WD_TMO … #define BD96801_REG_WD_CONF … #define BD96801_REG_WD_FEED … #define BD96801_REG_WD_FAILCOUNT … #define BD96801_REG_WD_ASK … #define BD96801_REG_WD_STATUS … #define BD96801_REG_PMIC_STATE … #define BD96801_REG_EXT_STATE … #define BD96801_STATE_STBY … #define BD96801_LOCK_REG … #define BD96801_UNLOCK … #define BD96801_LOCK … /* IRQ register area */ #define BD96801_REG_INT_MAIN … /* * The BD96801 has two physical IRQ lines, INTB and ERRB. * * The 'main status register' is located at 0x51. * The ERRB status registers are located at 0x52 ... 0x5B * INTB status registers are at range 0x5c ... 0x63 */ #define BD96801_REG_INT_SYS_ERRB1 … #define BD96801_REG_INT_SYS_INTB … #define BD96801_REG_INT_LDO7_INTB … /* MASK registers */ #define BD96801_REG_MASK_SYS_INTB … #define BD96801_REG_MASK_SYS_ERRB … #define BD96801_MAX_REGISTER … #define BD96801_OTP_ERR_MASK … #define BD96801_DBIST_ERR_MASK … #define BD96801_EEP_ERR_MASK … #define BD96801_ABIST_ERR_MASK … #define BD96801_PRSTB_ERR_MASK … #define BD96801_DRMOS1_ERR_MASK … #define BD96801_DRMOS2_ERR_MASK … #define BD96801_SLAVE_ERR_MASK … #define BD96801_VREF_ERR_MASK … #define BD96801_TSD_ERR_MASK … #define BD96801_UVLO_ERR_MASK … #define BD96801_OVLO_ERR_MASK … #define BD96801_OSC_ERR_MASK … #define BD96801_PON_ERR_MASK … #define BD96801_POFF_ERR_MASK … #define BD96801_CMD_SHDN_ERR_MASK … #define BD96801_INT_PRSTB_WDT_ERR_MASK … #define BD96801_INT_CHIP_IF_ERR_MASK … #define BD96801_INT_SHDN_ERR_MASK … #define BD96801_OUT_PVIN_ERR_MASK … #define BD96801_OUT_OVP_ERR_MASK … #define BD96801_OUT_UVP_ERR_MASK … #define BD96801_OUT_SHDN_ERR_MASK … /* ERRB IRQs */ enum { … }; /* INTB IRQs */ enum { … }; /* IRQ MASKs */ #define BD96801_TW_STAT_MASK … #define BD96801_WDT_ERR_STAT_MASK … #define BD96801_I2C_ERR_STAT_MASK … #define BD96801_CHIP_IF_ERR_STAT_MASK … #define BD96801_BUCK_OCPH_STAT_MASK … #define BD96801_BUCK_OCPL_STAT_MASK … #define BD96801_BUCK_OCPN_STAT_MASK … #define BD96801_BUCK_OVD_STAT_MASK … #define BD96801_BUCK_UVD_STAT_MASK … #define BD96801_BUCK_TW_CH_STAT_MASK … #define BD96801_LDO_OCPH_STAT_MASK … #define BD96801_LDO_OVD_STAT_MASK … #define BD96801_LDO_UVD_STAT_MASK … #endif
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