// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include <linux/clk-provider.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> #include <linux/regmap.h> #include <linux/phy.h> #include <linux/mdio.h> #include <linux/clk.h> #include <linux/gpio/consumer.h> #include <dt-bindings/clock/qcom,qca8k-nsscc.h> #include <dt-bindings/reset/qcom,qca8k-nsscc.h> #include "clk-branch.h" #include "clk-rcg.h" #include "clk-regmap.h" #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" #include "common.h" #include "reset.h" #define QCA8K_CLK_REG_BASE … #define QCA8K_HIGH_ADDR_PREFIX … #define QCA8K_LOW_ADDR_PREFIX … #define QCA8K_CFG_PAGE_REG … #define QCA8K_CLK_REG_MASK … #define QCA8K_CLK_PHY_ADDR_MASK … #define QCA8K_CLK_PAGE_MASK … #define QCA8K_REG_DATA_UPPER_16_BITS … enum { … }; enum { … }; static const struct clk_parent_data nss_cc_uniphy1_tx312p5m_data[] = …; static const struct parent_map nss_cc_uniphy1_tx312p5m_map[] = …; static struct clk_rcg2 nss_cc_switch_core_clk_src = …; static struct clk_branch nss_cc_switch_core_clk = …; static struct clk_branch nss_cc_apb_bridge_clk = …; static const struct clk_parent_data nss_cc_uniphy1_tx_data[] = …; static const struct parent_map nss_cc_uniphy1_tx_map[] = …; static struct clk_rcg2 nss_cc_mac0_tx_clk_src = …; static struct clk_regmap_div nss_cc_mac0_tx_div_clk_src = …; static struct clk_branch nss_cc_mac0_tx_clk = …; static struct clk_branch nss_cc_mac0_tx_srds1_clk = …; static const struct clk_parent_data nss_cc_uniphy1_rx_tx_data[] = …; static const struct parent_map nss_cc_uniphy1_rx_tx_map[] = …; static struct clk_rcg2 nss_cc_mac0_rx_clk_src = …; static struct clk_regmap_div nss_cc_mac0_rx_div_clk_src = …; static struct clk_branch nss_cc_mac0_rx_clk = …; static struct clk_branch nss_cc_mac0_rx_srds1_clk = …; static const struct clk_parent_data nss_cc_uniphy1_rx_tx312p5m_data[] = …; static const struct parent_map nss_cc_uniphy1_rx_tx312p5m_map[] = …; static const struct freq_conf ftbl_nss_cc_mac1_tx_clk_src_25[] = …; static const struct freq_conf ftbl_nss_cc_mac1_tx_clk_src_125[] = …; static const struct freq_conf ftbl_nss_cc_mac1_tx_clk_src_312p5[] = …; static const struct freq_multi_tbl ftbl_nss_cc_mac1_tx_clk_src[] = …; static struct clk_rcg2 nss_cc_mac1_tx_clk_src = …; static struct clk_regmap_div nss_cc_mac1_tx_div_clk_src = …; static struct clk_regmap_div nss_cc_mac1_srds1_ch0_xgmii_rx_div_clk_src = …; static struct clk_branch nss_cc_mac1_srds1_ch0_rx_clk = …; static struct clk_branch nss_cc_mac1_tx_clk = …; static struct clk_branch nss_cc_mac1_gephy0_tx_clk = …; static struct clk_branch nss_cc_mac1_srds1_ch0_xgmii_rx_clk = …; static const struct clk_parent_data nss_cc_uniphy1_tx312p5m_prx_data[] = …; static const struct parent_map nss_cc_uniphy1_tx312p5m_prx_map[] = …; static const struct freq_tbl ftbl_nss_cc_mac1_rx_clk_src[] = …; static struct clk_rcg2 nss_cc_mac1_rx_clk_src = …; static struct clk_regmap_div nss_cc_mac1_rx_div_clk_src = …; static struct clk_regmap_div nss_cc_mac1_srds1_ch0_xgmii_tx_div_clk_src = …; static struct clk_branch nss_cc_mac1_srds1_ch0_tx_clk = …; static struct clk_branch nss_cc_mac1_rx_clk = …; static struct clk_branch nss_cc_mac1_gephy0_rx_clk = …; static struct clk_branch nss_cc_mac1_srds1_ch0_xgmii_tx_clk = …; static struct clk_rcg2 nss_cc_mac2_tx_clk_src = …; static struct clk_regmap_div nss_cc_mac2_tx_div_clk_src = …; static struct clk_regmap_div nss_cc_mac2_srds1_ch1_xgmii_rx_div_clk_src = …; static struct clk_branch nss_cc_mac2_srds1_ch1_rx_clk = …; static struct clk_branch nss_cc_mac2_tx_clk = …; static struct clk_branch nss_cc_mac2_gephy1_tx_clk = …; static struct clk_branch nss_cc_mac2_srds1_ch1_xgmii_rx_clk = …; static struct clk_rcg2 nss_cc_mac2_rx_clk_src = …; static struct clk_regmap_div nss_cc_mac2_rx_div_clk_src = …; static struct clk_regmap_div nss_cc_mac2_srds1_ch1_xgmii_tx_div_clk_src = …; static struct clk_branch nss_cc_mac2_srds1_ch1_tx_clk = …; static struct clk_branch nss_cc_mac2_rx_clk = …; static struct clk_branch nss_cc_mac2_gephy1_rx_clk = …; static struct clk_branch nss_cc_mac2_srds1_ch1_xgmii_tx_clk = …; static struct clk_rcg2 nss_cc_mac3_tx_clk_src = …; static struct clk_regmap_div nss_cc_mac3_tx_div_clk_src = …; static struct clk_regmap_div nss_cc_mac3_srds1_ch2_xgmii_rx_div_clk_src = …; static struct clk_branch nss_cc_mac3_srds1_ch2_rx_clk = …; static struct clk_branch nss_cc_mac3_tx_clk = …; static struct clk_branch nss_cc_mac3_gephy2_tx_clk = …; static struct clk_branch nss_cc_mac3_srds1_ch2_xgmii_rx_clk = …; static struct clk_rcg2 nss_cc_mac3_rx_clk_src = …; static struct clk_regmap_div nss_cc_mac3_rx_div_clk_src = …; static struct clk_regmap_div nss_cc_mac3_srds1_ch2_xgmii_tx_div_clk_src = …; static struct clk_branch nss_cc_mac3_srds1_ch2_tx_clk = …; static struct clk_branch nss_cc_mac3_rx_clk = …; static struct clk_branch nss_cc_mac3_gephy2_rx_clk = …; static struct clk_branch nss_cc_mac3_srds1_ch2_xgmii_tx_clk = …; static const struct clk_parent_data nss_cc_uniphy0_rx_uniphy1_rx_tx312p5m_data[] = …; static const struct parent_map nss_cc_uniphy0_rx_uniphy1_rx_tx312p5m_map[] = …; static const struct freq_conf ftbl_nss_cc_mac4_tx_clk_src_25[] = …; static const struct freq_conf ftbl_nss_cc_mac4_tx_clk_src_125[] = …; static const struct freq_conf ftbl_nss_cc_mac4_tx_clk_src_312p5[] = …; static const struct freq_multi_tbl ftbl_nss_cc_mac4_tx_clk_src[] = …; static struct clk_rcg2 nss_cc_mac4_tx_clk_src = …; static struct clk_regmap_div nss_cc_mac4_tx_div_clk_src = …; static struct clk_regmap_div nss_cc_mac4_srds1_ch3_xgmii_rx_div_clk_src = …; static struct clk_branch nss_cc_mac4_srds1_ch3_rx_clk = …; static struct clk_branch nss_cc_mac4_tx_clk = …; static struct clk_branch nss_cc_mac4_gephy3_tx_clk = …; static struct clk_branch nss_cc_mac4_srds1_ch3_xgmii_rx_clk = …; static const struct clk_parent_data nss_cc_uniphy0_tx_uniphy1_tx312p5m_data[] = …; static const struct parent_map nss_cc_uniphy0_tx_uniphy1_tx312p5m_map[] = …; static const struct freq_conf ftbl_nss_cc_mac4_rx_clk_src_25[] = …; static const struct freq_conf ftbl_nss_cc_mac4_rx_clk_src_125[] = …; static const struct freq_conf ftbl_nss_cc_mac4_rx_clk_src_312p5[] = …; static const struct freq_multi_tbl ftbl_nss_cc_mac4_rx_clk_src[] = …; static struct clk_rcg2 nss_cc_mac4_rx_clk_src = …; static struct clk_regmap_div nss_cc_mac4_rx_div_clk_src = …; static struct clk_regmap_div nss_cc_mac4_srds1_ch3_xgmii_tx_div_clk_src = …; static struct clk_branch nss_cc_mac4_srds1_ch3_tx_clk = …; static struct clk_branch nss_cc_mac4_rx_clk = …; static struct clk_branch nss_cc_mac4_gephy3_rx_clk = …; static struct clk_branch nss_cc_mac4_srds1_ch3_xgmii_tx_clk = …; static const struct clk_parent_data nss_cc_uniphy0_tx_data[] = …; static const struct parent_map nss_cc_uniphy0_tx_map[] = …; static struct clk_rcg2 nss_cc_mac5_tx_clk_src = …; static struct clk_regmap_div nss_cc_mac5_tx_div_clk_src = …; static struct clk_branch nss_cc_mac5_tx_clk = …; static const struct clk_parent_data nss_cc_uniphy0_rx_tx_data[] = …; static const struct parent_map nss_cc_uniphy0_rx_tx_map[] = …; static struct clk_rcg2 nss_cc_mac5_rx_clk_src = …; static struct clk_regmap_div nss_cc_mac5_rx_div_clk_src = …; static struct clk_branch nss_cc_mac5_rx_clk = …; static const struct parent_map nss_cc_mac4_rx_div_mac5_tx_div_map[] = …; static struct clk_regmap_mux nss_cc_mac5_tx_srds0_clk_src = …; static struct clk_branch nss_cc_mac5_tx_srds0_clk = …; static const struct parent_map nss_cc_mac4_tx_div_mac5_rx_div_map[] = …; static struct clk_regmap_mux nss_cc_mac5_rx_srds0_clk_src = …; static struct clk_branch nss_cc_mac5_rx_srds0_clk = …; static const struct parent_map nss_cc_uniphy1_tx312p5m_map2[] = …; static const struct freq_tbl ftbl_nss_cc_ahb_clk_src[] = …; static struct clk_rcg2 nss_cc_ahb_clk_src = …; static struct clk_branch nss_cc_ahb_clk = …; static struct clk_branch nss_cc_sec_ctrl_ahb_clk = …; static struct clk_branch nss_cc_tlmm_clk = …; static struct clk_branch nss_cc_tlmm_ahb_clk = …; static struct clk_branch nss_cc_cnoc_ahb_clk = …; static struct clk_branch nss_cc_mdio_ahb_clk = …; static struct clk_branch nss_cc_mdio_master_ahb_clk = …; static const struct clk_parent_data nss_cc_xo_data[] = …; static const struct parent_map nss_cc_xo_map[] = …; static const struct freq_tbl ftbl_nss_cc_sys_clk_src[] = …; static struct clk_rcg2 nss_cc_sys_clk_src = …; static struct clk_branch nss_cc_srds0_sys_clk = …; static struct clk_branch nss_cc_srds1_sys_clk = …; static struct clk_branch nss_cc_gephy0_sys_clk = …; static struct clk_branch nss_cc_gephy1_sys_clk = …; static struct clk_branch nss_cc_gephy2_sys_clk = …; static struct clk_branch nss_cc_gephy3_sys_clk = …; static struct clk_regmap *nss_cc_qca8k_clocks[] = …; static const struct qcom_reset_map nss_cc_qca8k_resets[] = …; /* For each read/write operation of clock register, there are three MDIO frames * sent to the device. * * 1. The high address part[23:8] of register is packaged into the first MDIO frame * for selecting page. * 2. The low address part[7:0] of register is packaged into the second MDIO frame * with the low 16bit data to read/write. * 3. The low address part[7:0] of register is packaged into the last MDIO frame * with the high 16bit data to read/write. * * The clause22 MDIO frame format used by device is as below. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * | ST| OP| ADDR | REG | TA| DATA | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ static inline void convert_reg_to_mii_addr(u32 regaddr, u16 *reg, u16 *phy_addr, u16 *page) { … } static int qca8k_mii_read(struct mii_bus *bus, u16 switch_phy_id, u32 reg, u32 *val) { … } static void qca8k_mii_write(struct mii_bus *bus, u16 switch_phy_id, u32 reg, u32 val) { … } static int qca8k_mii_page_set(struct mii_bus *bus, u16 switch_phy_id, u32 reg, u16 page) { … } static int qca8k_regmap_read(void *context, unsigned int regaddr, unsigned int *val) { struct mii_bus *bus = context; u16 reg, phy_addr, page; int ret; regaddr += QCA8K_CLK_REG_BASE; convert_reg_to_mii_addr(regaddr, ®, &phy_addr, &page); mutex_lock(&bus->mdio_lock); ret = qca8k_mii_page_set(bus, QCA8K_HIGH_ADDR_PREFIX, QCA8K_CFG_PAGE_REG, page); if (ret < 0) goto qca8k_read_exit; ret = qca8k_mii_read(bus, phy_addr, reg, val); qca8k_read_exit: mutex_unlock(&bus->mdio_lock); return ret; }; static int qca8k_regmap_write(void *context, unsigned int regaddr, unsigned int val) { struct mii_bus *bus = context; u16 reg, phy_addr, page; int ret; regaddr += QCA8K_CLK_REG_BASE; convert_reg_to_mii_addr(regaddr, ®, &phy_addr, &page); mutex_lock(&bus->mdio_lock); ret = qca8k_mii_page_set(bus, QCA8K_HIGH_ADDR_PREFIX, QCA8K_CFG_PAGE_REG, page); if (ret < 0) goto qca8k_write_exit; qca8k_mii_write(bus, phy_addr, reg, val); qca8k_write_exit: mutex_unlock(&bus->mdio_lock); return ret; }; static int qca8k_regmap_update_bits(void *context, unsigned int regaddr, unsigned int mask, unsigned int value) { … } static const struct regmap_config nss_cc_qca8k_regmap_config = …; static const struct qcom_cc_desc nss_cc_qca8k_desc = …; /* * The reference clock of QCA8k NSSCC needs to be enabled to make sure * the GPIO reset taking effect. */ static int nss_cc_qca8k_clock_enable_and_reset(struct device *dev) { … } static int nss_cc_qca8k_probe(struct mdio_device *mdiodev) { … } static const struct of_device_id nss_cc_qca8k_match_table[] = …; MODULE_DEVICE_TABLE(of, nss_cc_qca8k_match_table); static struct mdio_driver nss_cc_qca8k_driver = …; mdio_module_driver(nss_cc_qca8k_driver); MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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