/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ /* * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. */ #ifndef __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__ #define __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__ #define DIV_CLK_MPLL_RP_CPU_NORMAL_0 … #define DIV_CLK_MPLL_AXI_DDR_0 … #define DIV_CLK_FPLL_DDR01_1 … #define DIV_CLK_FPLL_DDR23_1 … #define DIV_CLK_FPLL_RP_CPU_NORMAL_1 … #define DIV_CLK_FPLL_50M_A53 … #define DIV_CLK_FPLL_TOP_RP_CMN_DIV2 … #define DIV_CLK_FPLL_UART_500M … #define DIV_CLK_FPLL_AHB_LPC … #define DIV_CLK_FPLL_EFUSE … #define DIV_CLK_FPLL_TX_ETH0 … #define DIV_CLK_FPLL_PTP_REF_I_ETH0 … #define DIV_CLK_FPLL_REF_ETH0 … #define DIV_CLK_FPLL_EMMC … #define DIV_CLK_FPLL_SD … #define DIV_CLK_FPLL_TOP_AXI0 … #define DIV_CLK_FPLL_TOP_AXI_HSPERI … #define DIV_CLK_FPLL_AXI_DDR_1 … #define DIV_CLK_FPLL_DIV_TIMER1 … #define DIV_CLK_FPLL_DIV_TIMER2 … #define DIV_CLK_FPLL_DIV_TIMER3 … #define DIV_CLK_FPLL_DIV_TIMER4 … #define DIV_CLK_FPLL_DIV_TIMER5 … #define DIV_CLK_FPLL_DIV_TIMER6 … #define DIV_CLK_FPLL_DIV_TIMER7 … #define DIV_CLK_FPLL_DIV_TIMER8 … #define DIV_CLK_FPLL_100K_EMMC … #define DIV_CLK_FPLL_100K_SD … #define DIV_CLK_FPLL_GPIO_DB … #define DIV_CLK_DPLL0_DDR01_0 … #define DIV_CLK_DPLL1_DDR23_0 … #define GATE_CLK_RP_CPU_NORMAL_DIV0 … #define GATE_CLK_AXI_DDR_DIV0 … #define GATE_CLK_RP_CPU_NORMAL_DIV1 … #define GATE_CLK_A53_50M … #define GATE_CLK_TOP_RP_CMN_DIV2 … #define GATE_CLK_HSDMA … #define GATE_CLK_EMMC_100M … #define GATE_CLK_SD_100M … #define GATE_CLK_TX_ETH0 … #define GATE_CLK_PTP_REF_I_ETH0 … #define GATE_CLK_REF_ETH0 … #define GATE_CLK_UART_500M … #define GATE_CLK_EFUSE … #define GATE_CLK_AHB_LPC … #define GATE_CLK_AHB_ROM … #define GATE_CLK_AHB_SF … #define GATE_CLK_APB_UART … #define GATE_CLK_APB_TIMER … #define GATE_CLK_APB_EFUSE … #define GATE_CLK_APB_GPIO … #define GATE_CLK_APB_GPIO_INTR … #define GATE_CLK_APB_SPI … #define GATE_CLK_APB_I2C … #define GATE_CLK_APB_WDT … #define GATE_CLK_APB_PWM … #define GATE_CLK_APB_RTC … #define GATE_CLK_AXI_PCIE0 … #define GATE_CLK_AXI_PCIE1 … #define GATE_CLK_SYSDMA_AXI … #define GATE_CLK_AXI_DBG_I2C … #define GATE_CLK_AXI_SRAM … #define GATE_CLK_AXI_ETH0 … #define GATE_CLK_AXI_EMMC … #define GATE_CLK_AXI_SD … #define GATE_CLK_TOP_AXI0 … #define GATE_CLK_TOP_AXI_HSPERI … #define GATE_CLK_TIMER1 … #define GATE_CLK_TIMER2 … #define GATE_CLK_TIMER3 … #define GATE_CLK_TIMER4 … #define GATE_CLK_TIMER5 … #define GATE_CLK_TIMER6 … #define GATE_CLK_TIMER7 … #define GATE_CLK_TIMER8 … #define GATE_CLK_100K_EMMC … #define GATE_CLK_100K_SD … #define GATE_CLK_GPIO_DB … #define GATE_CLK_AXI_DDR_DIV1 … #define GATE_CLK_DDR01_DIV1 … #define GATE_CLK_DDR23_DIV1 … #define GATE_CLK_DDR01_DIV0 … #define GATE_CLK_DDR23_DIV0 … #define GATE_CLK_DDR01 … #define GATE_CLK_DDR23 … #define GATE_CLK_RP_CPU_NORMAL … #define GATE_CLK_AXI_DDR … #define MUX_CLK_DDR01 … #define MUX_CLK_DDR23 … #define MUX_CLK_RP_CPU_NORMAL … #define MUX_CLK_AXI_DDR … #endif /* __DT_BINDINGS_SOPHGO_SG2042_CLKGEN_H__ */
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