// SPDX-License-Identifier: GPL-2.0 /* * Sophgo SG2042 RP clock Driver * * Copyright (C) 2024 Sophgo Technology Inc. * Copyright (C) 2024 Chen Wang <[email protected]> */ #include <linux/array_size.h> #include <linux/clk-provider.h> #include <linux/platform_device.h> #include <dt-bindings/clock/sophgo,sg2042-rpgate.h> #include "clk-sg2042.h" #define R_SYSGATE_BEGIN … #define R_RP_RXU_CLK_ENABLE … #define R_MP0_STATUS_REG … #define R_MP0_CONTROL_REG … #define R_MP1_STATUS_REG … #define R_MP1_CONTROL_REG … #define R_MP2_STATUS_REG … #define R_MP2_CONTROL_REG … #define R_MP3_STATUS_REG … #define R_MP3_CONTROL_REG … #define R_MP4_STATUS_REG … #define R_MP4_CONTROL_REG … #define R_MP5_STATUS_REG … #define R_MP5_CONTROL_REG … #define R_MP6_STATUS_REG … #define R_MP6_CONTROL_REG … #define R_MP7_STATUS_REG … #define R_MP7_CONTROL_REG … #define R_MP8_STATUS_REG … #define R_MP8_CONTROL_REG … #define R_MP9_STATUS_REG … #define R_MP9_CONTROL_REG … #define R_MP10_STATUS_REG … #define R_MP10_CONTROL_REG … #define R_MP11_STATUS_REG … #define R_MP11_CONTROL_REG … #define R_MP12_STATUS_REG … #define R_MP12_CONTROL_REG … #define R_MP13_STATUS_REG … #define R_MP13_CONTROL_REG … #define R_MP14_STATUS_REG … #define R_MP14_CONTROL_REG … #define R_MP15_STATUS_REG … #define R_MP15_CONTROL_REG … /** * struct sg2042_rpgate_clock - Gate clock for RP(riscv processors) subsystem * @hw: clk_hw for initialization * @id: used to map clk_onecell_data * @offset_enable: offset of gate enable registers * @bit_idx: which bit in the register controls gating of this clock */ struct sg2042_rpgate_clock { … }; /* * Clock initialization macro naming rules: * FW: use CLK_HW_INIT_FW_NAME */ #define SG2042_GATE_FW(_id, _name, _parent, _flags, \ _r_enable, _bit_idx) … /* * Gate clocks for RP subsystem (including the MP subsystem), which control * registers are defined in SYS_CTRL. */ static const struct sg2042_rpgate_clock sg2042_gate_rp[] = …; static DEFINE_SPINLOCK(sg2042_clk_lock); static int sg2042_clk_register_rpgates(struct device *dev, struct sg2042_clk_data *clk_data, const struct sg2042_rpgate_clock gate_clks[], int num_gate_clks) { … } static int sg2042_init_clkdata(struct platform_device *pdev, int num_clks, struct sg2042_clk_data **pp_clk_data) { … } static int sg2042_rpgate_probe(struct platform_device *pdev) { … } static const struct of_device_id sg2042_rpgate_match[] = …; MODULE_DEVICE_TABLE(of, sg2042_rpgate_match); static struct platform_driver sg2042_rpgate_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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