dce_10_0_enum.h | Explore in Territory

/*
 * DCE_10_0 Register documentation
 *
 * Copyright (C) 2014  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef DCE_10_0_ENUM_H
#define DCE_10_0_ENUM_H

DCIO_DC_GENERICA_SEL;
DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
DCIO_DC_GENERICB_SEL;
DCIO_DC_PAD_EXTERN_SIG_SEL;
DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS;
DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
DCIO_DC_GPIO_VIP_DEBUG;
DCIO_DC_GPIO_MACRO_DEBUG;
DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL;
DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN;
DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
DCIO_BL_PWM_CNTL_BL_PWM_EN;
DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
DCIO_BL_PWM_GRP1_REG_LOCK;
DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
DCIO_GSL_SEL;
DCIO_GENLK_CLK_GSL_MASK;
DCIO_GENLK_VSYNC_GSL_MASK;
DCIO_SWAPLOCK_A_GSL_MASK;
DCIO_SWAPLOCK_B_GSL_MASK;
DCIO_GSL_VSYNC_SEL;
DCIO_GSL0_TIMING_SYNC_SEL;
DCIO_GSL0_GLOBAL_UNLOCK_SEL;
DCIO_GSL1_TIMING_SYNC_SEL;
DCIO_GSL1_GLOBAL_UNLOCK_SEL;
DCIO_GSL2_TIMING_SYNC_SEL;
DCIO_GSL2_GLOBAL_UNLOCK_SEL;
DCIO_DC_GPU_TIMER_START_POSITION;
DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_RAMP_DIS;
DCIO_DCO_DCFE_EXT_VSYNC_MUX;
DCIO_DCO_EXT_VSYNC_MASK;
DCIO_DBG_OUT_PIN_SEL;
DCIO_DBG_OUT_12BIT_SEL;
DCIO_DSYNC_SOFT_RESET;
DCIO_DACA_SOFT_RESET;
DCIO_DCRXPHY_SOFT_RESET;
DCIO_DPHY_LANE_SEL;
DCIO_DC_GPU_TIMER_READ_SELECT;
DCIO_IMPCAL_STEP_DELAY;
DCIO_UNIPHY_IMPCAL_SEL;
DCIOCHIP_HPD_SEL;
DCIOCHIP_PAD_MODE;
DCIOCHIP_AUXSLAVE_PAD_MODE;
DCIOCHIP_INVERT;
DCIOCHIP_PD_EN;
DCIOCHIP_GPIO_MASK_EN;
DCIOCHIP_MASK;
DCIOCHIP_GPIO_I2C_MASK;
DCIOCHIP_GPIO_I2C_DRIVE;
DCIOCHIP_GPIO_I2C_EN;
DCIOCHIP_MASK_4BIT;
DCIOCHIP_ENABLE_4BIT;
DCIOCHIP_MASK_5BIT;
DCIOCHIP_ENABLE_5BIT;
DCIOCHIP_MASK_2BIT;
DCIOCHIP_ENABLE_2BIT;
DCIOCHIP_REF_27_SRC_SEL;
DCIOCHIP_DVO_VREFPON;
DCIOCHIP_DVO_VREFSEL;
COL_MAN_UPDATE_LOCK;
COL_MAN_DISABLE_MULTIPLE_UPDATE;
COL_MAN_INPUTCSC_MODE;
COL_MAN_INPUTCSC_TYPE;
COL_MAN_INPUTCSC_CONVERT;
COL_MAN_PRESCALE_MODE;
COL_MAN_OUTPUT_CSC_MODE;
COL_MAN_DENORM_CLAMP_CONTROL;
COL_MAN_GAMMA_CORR_CONTROL;
SurfaceEndian;
ArrayMode;
PipeTiling;
BankTiling;
GroupInterleave;
RowTiling;
BankSwapBytes;
SampleSplitBytes;
NumPipes;
PipeInterleaveSize;
BankInterleaveSize;
NumShaderEngines;
ShaderEngineTileSize;
NumGPUs;
MultiGPUTileSize;
RowSize;
NumLowerPipes;
DebugBlockId;
DebugBlockId_OLD;
DebugBlockId_BY2;
DebugBlockId_BY4;
DebugBlockId_BY8;
DebugBlockId_BY16;
ColorTransform;
CompareRef;
ReadSize;
DepthFormat;
ZFormat;
StencilFormat;
CmaskMode;
QuadExportFormat;
QuadExportFormatOld;
ColorFormat;
SurfaceFormat;
BUF_DATA_FORMAT;
IMG_DATA_FORMAT;
BUF_NUM_FORMAT;
IMG_NUM_FORMAT;
TileType;
NonDispTilingOrder;
MicroTileMode;
TileSplit;
SampleSplit;
PipeConfig;
NumBanks;
BankWidth;
BankHeight;
BankWidthHeight;
MacroTileAspect;
GATCL1RequestType;
TCC_CACHE_POLICIES;
MTYPE;
PERFMON_COUNTER_MODE;
PERFMON_SPM_MODE;
SurfaceTiling;
SurfaceArray;
ColorArray;
DepthArray;
ENUM_NUM_SIMD_PER_CU;
MEM_PWR_FORCE_CTRL;
MEM_PWR_FORCE_CTRL2;
MEM_PWR_DIS_CTRL;
MEM_PWR_SEL_CTRL;
MEM_PWR_SEL_CTRL2;

#endif /* DCE_10_0_ENUM_H */
linux/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h
