/* * Copyright 2023 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef _gc_12_0_0_OFFSET_HEADER #define _gc_12_0_0_OFFSET_HEADER // addressBlock: gc_gfx_cpwd_sdma0_sdmadec // base address: 0x4980 #define regSDMA0_DEC_START … #define regSDMA0_DEC_START_BASE_IDX … #define regSDMA0_MCU_MISC_CNTL … #define regSDMA0_MCU_MISC_CNTL_BASE_IDX … #define regSDMA0_UCODE_REV … #define regSDMA0_UCODE_REV_BASE_IDX … #define regSDMA0_GLOBAL_TIMESTAMP_LO … #define regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX … #define regSDMA0_GLOBAL_TIMESTAMP_HI … #define regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX … #define regSDMA0_POWER_CNTL … #define regSDMA0_POWER_CNTL_BASE_IDX … #define regSDMA0_CNTL … #define regSDMA0_CNTL_BASE_IDX … #define regSDMA0_CHICKEN_BITS … #define regSDMA0_CHICKEN_BITS_BASE_IDX … #define regSDMA0_CACHE_CNTL … #define regSDMA0_CACHE_CNTL_BASE_IDX … #define regSDMA0_RB_RPTR_FETCH … #define regSDMA0_RB_RPTR_FETCH_BASE_IDX … #define regSDMA0_RB_RPTR_FETCH_HI … #define regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX … #define regSDMA0_IB_OFFSET_FETCH … #define regSDMA0_IB_OFFSET_FETCH_BASE_IDX … #define regSDMA0_PROGRAM … #define regSDMA0_PROGRAM_BASE_IDX … #define regSDMA0_STATUS_REG … #define regSDMA0_STATUS_REG_BASE_IDX … #define regSDMA0_STATUS1_REG … #define regSDMA0_STATUS1_REG_BASE_IDX … #define regSDMA0_CNTL1 … #define regSDMA0_CNTL1_BASE_IDX … #define regSDMA0_HBM_PAGE_CONFIG … #define regSDMA0_HBM_PAGE_CONFIG_BASE_IDX … #define regSDMA0_FREEZE … #define regSDMA0_FREEZE_BASE_IDX … #define regSDMA0_PROCESS_QUANTUM0 … #define regSDMA0_PROCESS_QUANTUM0_BASE_IDX … #define regSDMA0_PROCESS_QUANTUM1 … #define regSDMA0_PROCESS_QUANTUM1_BASE_IDX … #define regSDMA0_WATCHDOG_CNTL … #define regSDMA0_WATCHDOG_CNTL_BASE_IDX … #define regSDMA0_QUEUE_STATUS0 … #define regSDMA0_QUEUE_STATUS0_BASE_IDX … #define regSDMA0_EDC_CONFIG … #define regSDMA0_EDC_CONFIG_BASE_IDX … #define regSDMA0_ID … #define regSDMA0_ID_BASE_IDX … #define regSDMA0_VERSION … #define regSDMA0_VERSION_BASE_IDX … #define regSDMA0_STATUS2_REG … #define regSDMA0_STATUS2_REG_BASE_IDX … #define regSDMA0_ATOMIC_CNTL … #define regSDMA0_ATOMIC_CNTL_BASE_IDX … #define regSDMA0_ATOMIC_PREOP_LO … #define regSDMA0_ATOMIC_PREOP_LO_BASE_IDX … #define regSDMA0_ATOMIC_PREOP_HI … #define regSDMA0_ATOMIC_PREOP_HI_BASE_IDX … #define regSDMA0_DCC_CNTL … #define regSDMA0_DCC_CNTL_BASE_IDX … #define regSDMA0_UTCL1_CNTL … #define regSDMA0_UTCL1_CNTL_BASE_IDX … #define regSDMA0_UTCL1_WATERMK … #define regSDMA0_UTCL1_WATERMK_BASE_IDX … #define regSDMA0_UTCL1_TIMEOUT … #define regSDMA0_UTCL1_TIMEOUT_BASE_IDX … #define regSDMA0_UTCL1_PAGE … #define regSDMA0_UTCL1_PAGE_BASE_IDX … #define regSDMA0_EXTERNAL_FROZEN … #define regSDMA0_EXTERNAL_FROZEN_BASE_IDX … #define regSDMA0_UTCL1_RD_STATUS … #define regSDMA0_UTCL1_RD_STATUS_BASE_IDX … #define regSDMA0_UTCL1_WR_STATUS … #define regSDMA0_UTCL1_WR_STATUS_BASE_IDX … #define regSDMA0_UTCL1_INV0 … #define regSDMA0_UTCL1_INV0_BASE_IDX … #define regSDMA0_UTCL1_INV1 … #define regSDMA0_UTCL1_INV1_BASE_IDX … #define regSDMA0_UTCL1_INV2 … #define regSDMA0_UTCL1_INV2_BASE_IDX … #define regSDMA0_UTCL1_RD_XNACK0 … #define regSDMA0_UTCL1_RD_XNACK0_BASE_IDX … #define regSDMA0_UTCL1_RD_XNACK1 … #define regSDMA0_UTCL1_RD_XNACK1_BASE_IDX … #define regSDMA0_UTCL1_WR_XNACK0 … #define regSDMA0_UTCL1_WR_XNACK0_BASE_IDX … #define regSDMA0_UTCL1_WR_XNACK1 … #define regSDMA0_UTCL1_WR_XNACK1_BASE_IDX … #define regSDMA0_RELAX_ORDERING_LUT … #define regSDMA0_RELAX_ORDERING_LUT_BASE_IDX … #define regSDMA0_CHICKEN_BITS_2 … #define regSDMA0_CHICKEN_BITS_2_BASE_IDX … #define regSDMA0_STATUS3_REG … #define regSDMA0_STATUS3_REG_BASE_IDX … #define regSDMA0_GLOBAL_QUANTUM … #define regSDMA0_GLOBAL_QUANTUM_BASE_IDX … #define regSDMA0_ERROR_LOG … #define regSDMA0_ERROR_LOG_BASE_IDX … #define regSDMA0_PUB_DUMMY_REG0 … #define regSDMA0_PUB_DUMMY_REG0_BASE_IDX … #define regSDMA0_PUB_DUMMY_REG1 … #define regSDMA0_PUB_DUMMY_REG1_BASE_IDX … #define regSDMA0_PUB_DUMMY_REG2 … #define regSDMA0_PUB_DUMMY_REG2_BASE_IDX … #define regSDMA0_PUB_DUMMY_REG3 … #define regSDMA0_PUB_DUMMY_REG3_BASE_IDX … #define regSDMA0_MCU_COUNTER … #define regSDMA0_MCU_COUNTER_BASE_IDX … #define regSDMA0_CRD_CNTL … #define regSDMA0_CRD_CNTL_BASE_IDX … #define regSDMA0_RLC_CGCG_CTRL … #define regSDMA0_RLC_CGCG_CTRL_BASE_IDX … #define regSDMA0_GPU_IOV_VIOLATION_LOG … #define regSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX … #define regSDMA0_AQL_STATUS … #define regSDMA0_AQL_STATUS_BASE_IDX … #define regSDMA0_TLBI_GCR_CNTL … #define regSDMA0_TLBI_GCR_CNTL_BASE_IDX … #define regSDMA0_INT_STATUS … #define regSDMA0_INT_STATUS_BASE_IDX … #define regSDMA0_GPU_IOV_VIOLATION_LOG2 … #define regSDMA0_GPU_IOV_VIOLATION_LOG2_BASE_IDX … #define regSDMA0_INVALID_ADDR_LO … #define regSDMA0_INVALID_ADDR_LO_BASE_IDX … #define regSDMA0_INVALID_ADDR_HI … #define regSDMA0_INVALID_ADDR_HI_BASE_IDX … #define regSDMA0_INVALID_ADDR_SRC … #define regSDMA0_INVALID_ADDR_SRC_BASE_IDX … #define regSDMA0_CLOCK_GATING_STATUS … #define regSDMA0_CLOCK_GATING_STATUS_BASE_IDX … #define regSDMA0_STATUS4_REG … #define regSDMA0_STATUS4_REG_BASE_IDX … #define regSDMA0_SCRATCH_RAM_DATA … #define regSDMA0_SCRATCH_RAM_DATA_BASE_IDX … #define regSDMA0_SCRATCH_RAM_ADDR … #define regSDMA0_SCRATCH_RAM_ADDR_BASE_IDX … #define regSDMA0_TIMESTAMP_CNTL … #define regSDMA0_TIMESTAMP_CNTL_BASE_IDX … #define regSDMA0_STATUS5_REG … #define regSDMA0_STATUS5_REG_BASE_IDX … #define regSDMA0_QUEUE_RESET_REQ … #define regSDMA0_QUEUE_RESET_REQ_BASE_IDX … #define regSDMA0_STATUS6_REG … #define regSDMA0_STATUS6_REG_BASE_IDX … #define regSDMA0_STATUS7_REG … #define regSDMA0_STATUS7_REG_BASE_IDX … #define regSDMA0_STATUS8_REG … #define regSDMA0_STATUS8_REG_BASE_IDX … #define regSDMA0_CE_CTRL … #define regSDMA0_CE_CTRL_BASE_IDX … #define regSDMA0_FED_STATUS … #define regSDMA0_FED_STATUS_BASE_IDX … #define regSDMA0_QUEUE0_RB_CNTL … #define regSDMA0_QUEUE0_RB_CNTL_BASE_IDX … #define regSDMA0_QUEUE0_RB_BASE … #define regSDMA0_QUEUE0_RB_BASE_BASE_IDX … #define regSDMA0_QUEUE0_RB_BASE_HI … #define regSDMA0_QUEUE0_RB_BASE_HI_BASE_IDX … #define regSDMA0_QUEUE0_RB_RPTR … #define regSDMA0_QUEUE0_RB_RPTR_BASE_IDX … #define regSDMA0_QUEUE0_RB_RPTR_HI … #define regSDMA0_QUEUE0_RB_RPTR_HI_BASE_IDX … #define regSDMA0_QUEUE0_RB_WPTR … #define regSDMA0_QUEUE0_RB_WPTR_BASE_IDX … #define regSDMA0_QUEUE0_RB_WPTR_HI … #define regSDMA0_QUEUE0_RB_WPTR_HI_BASE_IDX … #define regSDMA0_QUEUE0_RB_RPTR_ADDR_LO … #define regSDMA0_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE0_RB_RPTR_ADDR_HI … #define regSDMA0_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE0_IB_CNTL … #define regSDMA0_QUEUE0_IB_CNTL_BASE_IDX … #define regSDMA0_QUEUE0_IB_RPTR … #define regSDMA0_QUEUE0_IB_RPTR_BASE_IDX … #define regSDMA0_QUEUE0_IB_OFFSET … #define regSDMA0_QUEUE0_IB_OFFSET_BASE_IDX … #define regSDMA0_QUEUE0_IB_BASE_LO … #define regSDMA0_QUEUE0_IB_BASE_LO_BASE_IDX … #define regSDMA0_QUEUE0_IB_BASE_HI … #define regSDMA0_QUEUE0_IB_BASE_HI_BASE_IDX … #define regSDMA0_QUEUE0_IB_SIZE … #define regSDMA0_QUEUE0_IB_SIZE_BASE_IDX … #define regSDMA0_QUEUE0_DOORBELL … #define regSDMA0_QUEUE0_DOORBELL_BASE_IDX … #define regSDMA0_QUEUE0_DOORBELL_LOG … #define regSDMA0_QUEUE0_DOORBELL_LOG_BASE_IDX … #define regSDMA0_QUEUE0_DOORBELL_OFFSET … #define regSDMA0_QUEUE0_DOORBELL_OFFSET_BASE_IDX … #define regSDMA0_QUEUE0_CSA_ADDR_LO … #define regSDMA0_QUEUE0_CSA_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE0_CSA_ADDR_HI … #define regSDMA0_QUEUE0_CSA_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE0_SCHEDULE_CNTL … #define regSDMA0_QUEUE0_SCHEDULE_CNTL_BASE_IDX … #define regSDMA0_QUEUE0_IB_SUB_REMAIN … #define regSDMA0_QUEUE0_IB_SUB_REMAIN_BASE_IDX … #define regSDMA0_QUEUE0_PREEMPT … #define regSDMA0_QUEUE0_PREEMPT_BASE_IDX … #define regSDMA0_QUEUE0_DUMMY_REG … #define regSDMA0_QUEUE0_DUMMY_REG_BASE_IDX … #define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO … #define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI … #define regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE0_RB_AQL_CNTL … #define regSDMA0_QUEUE0_RB_AQL_CNTL_BASE_IDX … #define regSDMA0_QUEUE0_MINOR_PTR_UPDATE … #define regSDMA0_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX … #define regSDMA0_QUEUE0_CONTEXT_SWITCH_STATUS … #define regSDMA0_QUEUE0_CONTEXT_SWITCH_STATUS_BASE_IDX … #define regSDMA0_QUEUE0_MIDCMD_CNTL … #define regSDMA0_QUEUE0_MIDCMD_CNTL_BASE_IDX … #define regSDMA0_QUEUE0_MIDCMD_DATA0 … #define regSDMA0_QUEUE0_MIDCMD_DATA0_BASE_IDX … #define regSDMA0_QUEUE0_MIDCMD_DATA1 … #define regSDMA0_QUEUE0_MIDCMD_DATA1_BASE_IDX … #define regSDMA0_QUEUE0_MIDCMD_DATA2 … #define regSDMA0_QUEUE0_MIDCMD_DATA2_BASE_IDX … #define regSDMA0_QUEUE0_MIDCMD_DATA3 … #define regSDMA0_QUEUE0_MIDCMD_DATA3_BASE_IDX … #define regSDMA0_QUEUE0_MIDCMD_DATA4 … #define regSDMA0_QUEUE0_MIDCMD_DATA4_BASE_IDX … #define regSDMA0_QUEUE0_MIDCMD_DATA5 … #define regSDMA0_QUEUE0_MIDCMD_DATA5_BASE_IDX … #define regSDMA0_QUEUE0_MIDCMD_DATA6 … #define regSDMA0_QUEUE0_MIDCMD_DATA6_BASE_IDX … #define regSDMA0_QUEUE0_MIDCMD_DATA7 … #define regSDMA0_QUEUE0_MIDCMD_DATA7_BASE_IDX … #define regSDMA0_QUEUE0_MIDCMD_DATA8 … #define regSDMA0_QUEUE0_MIDCMD_DATA8_BASE_IDX … #define regSDMA0_QUEUE0_MIDCMD_DATA9 … #define regSDMA0_QUEUE0_MIDCMD_DATA9_BASE_IDX … #define regSDMA0_QUEUE0_MIDCMD_DATA10 … #define regSDMA0_QUEUE0_MIDCMD_DATA10_BASE_IDX … #define regSDMA0_QUEUE0_WAIT_UNSATISFIED_THD … #define regSDMA0_QUEUE0_WAIT_UNSATISFIED_THD_BASE_IDX … #define regSDMA0_QUEUE0_MQD_BASE_ADDR_LO … #define regSDMA0_QUEUE0_MQD_BASE_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE0_MQD_BASE_ADDR_HI … #define regSDMA0_QUEUE0_MQD_BASE_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE0_MQD_CONTROL … #define regSDMA0_QUEUE0_MQD_CONTROL_BASE_IDX … #define regSDMA0_QUEUE0_DEQUEUE_REQUEST … #define regSDMA0_QUEUE0_DEQUEUE_REQUEST_BASE_IDX … #define regSDMA0_QUEUE0_CONTEXT_STATUS … #define regSDMA0_QUEUE0_CONTEXT_STATUS_BASE_IDX … #define regSDMA0_QUEUE1_RB_CNTL … #define regSDMA0_QUEUE1_RB_CNTL_BASE_IDX … #define regSDMA0_QUEUE1_RB_BASE … #define regSDMA0_QUEUE1_RB_BASE_BASE_IDX … #define regSDMA0_QUEUE1_RB_BASE_HI … #define regSDMA0_QUEUE1_RB_BASE_HI_BASE_IDX … #define regSDMA0_QUEUE1_RB_RPTR … #define regSDMA0_QUEUE1_RB_RPTR_BASE_IDX … #define regSDMA0_QUEUE1_RB_RPTR_HI … #define regSDMA0_QUEUE1_RB_RPTR_HI_BASE_IDX … #define regSDMA0_QUEUE1_RB_WPTR … #define regSDMA0_QUEUE1_RB_WPTR_BASE_IDX … #define regSDMA0_QUEUE1_RB_WPTR_HI … #define regSDMA0_QUEUE1_RB_WPTR_HI_BASE_IDX … #define regSDMA0_QUEUE1_RB_RPTR_ADDR_LO … #define regSDMA0_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE1_RB_RPTR_ADDR_HI … #define regSDMA0_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE1_IB_CNTL … #define regSDMA0_QUEUE1_IB_CNTL_BASE_IDX … #define regSDMA0_QUEUE1_IB_RPTR … #define regSDMA0_QUEUE1_IB_RPTR_BASE_IDX … #define regSDMA0_QUEUE1_IB_OFFSET … #define regSDMA0_QUEUE1_IB_OFFSET_BASE_IDX … #define regSDMA0_QUEUE1_IB_BASE_LO … #define regSDMA0_QUEUE1_IB_BASE_LO_BASE_IDX … #define regSDMA0_QUEUE1_IB_BASE_HI … #define regSDMA0_QUEUE1_IB_BASE_HI_BASE_IDX … #define regSDMA0_QUEUE1_IB_SIZE … #define regSDMA0_QUEUE1_IB_SIZE_BASE_IDX … #define regSDMA0_QUEUE1_DOORBELL … #define regSDMA0_QUEUE1_DOORBELL_BASE_IDX … #define regSDMA0_QUEUE1_DOORBELL_LOG … #define regSDMA0_QUEUE1_DOORBELL_LOG_BASE_IDX … #define regSDMA0_QUEUE1_DOORBELL_OFFSET … #define regSDMA0_QUEUE1_DOORBELL_OFFSET_BASE_IDX … #define regSDMA0_QUEUE1_CSA_ADDR_LO … #define regSDMA0_QUEUE1_CSA_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE1_CSA_ADDR_HI … #define regSDMA0_QUEUE1_CSA_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE1_SCHEDULE_CNTL … #define regSDMA0_QUEUE1_SCHEDULE_CNTL_BASE_IDX … #define regSDMA0_QUEUE1_IB_SUB_REMAIN … #define regSDMA0_QUEUE1_IB_SUB_REMAIN_BASE_IDX … #define regSDMA0_QUEUE1_PREEMPT … #define regSDMA0_QUEUE1_PREEMPT_BASE_IDX … #define regSDMA0_QUEUE1_DUMMY_REG … #define regSDMA0_QUEUE1_DUMMY_REG_BASE_IDX … #define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO … #define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI … #define regSDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE1_RB_AQL_CNTL … #define regSDMA0_QUEUE1_RB_AQL_CNTL_BASE_IDX … #define regSDMA0_QUEUE1_MINOR_PTR_UPDATE … #define regSDMA0_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX … #define regSDMA0_QUEUE1_CONTEXT_SWITCH_STATUS … #define regSDMA0_QUEUE1_CONTEXT_SWITCH_STATUS_BASE_IDX … #define regSDMA0_QUEUE1_MIDCMD_CNTL … #define regSDMA0_QUEUE1_MIDCMD_CNTL_BASE_IDX … #define regSDMA0_QUEUE1_MIDCMD_DATA0 … #define regSDMA0_QUEUE1_MIDCMD_DATA0_BASE_IDX … #define regSDMA0_QUEUE1_MIDCMD_DATA1 … #define regSDMA0_QUEUE1_MIDCMD_DATA1_BASE_IDX … #define regSDMA0_QUEUE1_MIDCMD_DATA2 … #define regSDMA0_QUEUE1_MIDCMD_DATA2_BASE_IDX … #define regSDMA0_QUEUE1_MIDCMD_DATA3 … #define regSDMA0_QUEUE1_MIDCMD_DATA3_BASE_IDX … #define regSDMA0_QUEUE1_MIDCMD_DATA4 … #define regSDMA0_QUEUE1_MIDCMD_DATA4_BASE_IDX … #define regSDMA0_QUEUE1_MIDCMD_DATA5 … #define regSDMA0_QUEUE1_MIDCMD_DATA5_BASE_IDX … #define regSDMA0_QUEUE1_MIDCMD_DATA6 … #define regSDMA0_QUEUE1_MIDCMD_DATA6_BASE_IDX … #define regSDMA0_QUEUE1_MIDCMD_DATA7 … #define regSDMA0_QUEUE1_MIDCMD_DATA7_BASE_IDX … #define regSDMA0_QUEUE1_MIDCMD_DATA8 … #define regSDMA0_QUEUE1_MIDCMD_DATA8_BASE_IDX … #define regSDMA0_QUEUE1_MIDCMD_DATA9 … #define regSDMA0_QUEUE1_MIDCMD_DATA9_BASE_IDX … #define regSDMA0_QUEUE1_MIDCMD_DATA10 … #define regSDMA0_QUEUE1_MIDCMD_DATA10_BASE_IDX … #define regSDMA0_QUEUE1_WAIT_UNSATISFIED_THD … #define regSDMA0_QUEUE1_WAIT_UNSATISFIED_THD_BASE_IDX … #define regSDMA0_QUEUE1_MQD_BASE_ADDR_LO … #define regSDMA0_QUEUE1_MQD_BASE_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE1_MQD_BASE_ADDR_HI … #define regSDMA0_QUEUE1_MQD_BASE_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE1_MQD_CONTROL … #define regSDMA0_QUEUE1_MQD_CONTROL_BASE_IDX … #define regSDMA0_QUEUE1_DEQUEUE_REQUEST … #define regSDMA0_QUEUE1_DEQUEUE_REQUEST_BASE_IDX … #define regSDMA0_QUEUE1_CONTEXT_STATUS … #define regSDMA0_QUEUE1_CONTEXT_STATUS_BASE_IDX … #define regSDMA0_QUEUE2_RB_CNTL … #define regSDMA0_QUEUE2_RB_CNTL_BASE_IDX … #define regSDMA0_QUEUE2_RB_BASE … #define regSDMA0_QUEUE2_RB_BASE_BASE_IDX … #define regSDMA0_QUEUE2_RB_BASE_HI … #define regSDMA0_QUEUE2_RB_BASE_HI_BASE_IDX … #define regSDMA0_QUEUE2_RB_RPTR … #define regSDMA0_QUEUE2_RB_RPTR_BASE_IDX … #define regSDMA0_QUEUE2_RB_RPTR_HI … #define regSDMA0_QUEUE2_RB_RPTR_HI_BASE_IDX … #define regSDMA0_QUEUE2_RB_WPTR … #define regSDMA0_QUEUE2_RB_WPTR_BASE_IDX … #define regSDMA0_QUEUE2_RB_WPTR_HI … #define regSDMA0_QUEUE2_RB_WPTR_HI_BASE_IDX … #define regSDMA0_QUEUE2_RB_RPTR_ADDR_LO … #define regSDMA0_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE2_RB_RPTR_ADDR_HI … #define regSDMA0_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE2_IB_CNTL … #define regSDMA0_QUEUE2_IB_CNTL_BASE_IDX … #define regSDMA0_QUEUE2_IB_RPTR … #define regSDMA0_QUEUE2_IB_RPTR_BASE_IDX … #define regSDMA0_QUEUE2_IB_OFFSET … #define regSDMA0_QUEUE2_IB_OFFSET_BASE_IDX … #define regSDMA0_QUEUE2_IB_BASE_LO … #define regSDMA0_QUEUE2_IB_BASE_LO_BASE_IDX … #define regSDMA0_QUEUE2_IB_BASE_HI … #define regSDMA0_QUEUE2_IB_BASE_HI_BASE_IDX … #define regSDMA0_QUEUE2_IB_SIZE … #define regSDMA0_QUEUE2_IB_SIZE_BASE_IDX … #define regSDMA0_QUEUE2_DOORBELL … #define regSDMA0_QUEUE2_DOORBELL_BASE_IDX … #define regSDMA0_QUEUE2_DOORBELL_LOG … #define regSDMA0_QUEUE2_DOORBELL_LOG_BASE_IDX … #define regSDMA0_QUEUE2_DOORBELL_OFFSET … #define regSDMA0_QUEUE2_DOORBELL_OFFSET_BASE_IDX … #define regSDMA0_QUEUE2_CSA_ADDR_LO … #define regSDMA0_QUEUE2_CSA_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE2_CSA_ADDR_HI … #define regSDMA0_QUEUE2_CSA_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE2_SCHEDULE_CNTL … #define regSDMA0_QUEUE2_SCHEDULE_CNTL_BASE_IDX … #define regSDMA0_QUEUE2_IB_SUB_REMAIN … #define regSDMA0_QUEUE2_IB_SUB_REMAIN_BASE_IDX … #define regSDMA0_QUEUE2_PREEMPT … #define regSDMA0_QUEUE2_PREEMPT_BASE_IDX … #define regSDMA0_QUEUE2_DUMMY_REG … #define regSDMA0_QUEUE2_DUMMY_REG_BASE_IDX … #define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO … #define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI … #define regSDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE2_RB_AQL_CNTL … #define regSDMA0_QUEUE2_RB_AQL_CNTL_BASE_IDX … #define regSDMA0_QUEUE2_MINOR_PTR_UPDATE … #define regSDMA0_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX … #define regSDMA0_QUEUE2_CONTEXT_SWITCH_STATUS … #define regSDMA0_QUEUE2_CONTEXT_SWITCH_STATUS_BASE_IDX … #define regSDMA0_QUEUE2_MIDCMD_CNTL … #define regSDMA0_QUEUE2_MIDCMD_CNTL_BASE_IDX … #define regSDMA0_QUEUE2_MIDCMD_DATA0 … #define regSDMA0_QUEUE2_MIDCMD_DATA0_BASE_IDX … #define regSDMA0_QUEUE2_MIDCMD_DATA1 … #define regSDMA0_QUEUE2_MIDCMD_DATA1_BASE_IDX … #define regSDMA0_QUEUE2_MIDCMD_DATA2 … #define regSDMA0_QUEUE2_MIDCMD_DATA2_BASE_IDX … #define regSDMA0_QUEUE2_MIDCMD_DATA3 … #define regSDMA0_QUEUE2_MIDCMD_DATA3_BASE_IDX … #define regSDMA0_QUEUE2_MIDCMD_DATA4 … #define regSDMA0_QUEUE2_MIDCMD_DATA4_BASE_IDX … #define regSDMA0_QUEUE2_MIDCMD_DATA5 … #define regSDMA0_QUEUE2_MIDCMD_DATA5_BASE_IDX … #define regSDMA0_QUEUE2_MIDCMD_DATA6 … #define regSDMA0_QUEUE2_MIDCMD_DATA6_BASE_IDX … #define regSDMA0_QUEUE2_MIDCMD_DATA7 … #define regSDMA0_QUEUE2_MIDCMD_DATA7_BASE_IDX … #define regSDMA0_QUEUE2_MIDCMD_DATA8 … #define regSDMA0_QUEUE2_MIDCMD_DATA8_BASE_IDX … #define regSDMA0_QUEUE2_MIDCMD_DATA9 … #define regSDMA0_QUEUE2_MIDCMD_DATA9_BASE_IDX … #define regSDMA0_QUEUE2_MIDCMD_DATA10 … #define regSDMA0_QUEUE2_MIDCMD_DATA10_BASE_IDX … #define regSDMA0_QUEUE2_WAIT_UNSATISFIED_THD … #define regSDMA0_QUEUE2_WAIT_UNSATISFIED_THD_BASE_IDX … #define regSDMA0_QUEUE2_MQD_BASE_ADDR_LO … #define regSDMA0_QUEUE2_MQD_BASE_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE2_MQD_BASE_ADDR_HI … #define regSDMA0_QUEUE2_MQD_BASE_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE2_MQD_CONTROL … #define regSDMA0_QUEUE2_MQD_CONTROL_BASE_IDX … #define regSDMA0_QUEUE2_DEQUEUE_REQUEST … #define regSDMA0_QUEUE2_DEQUEUE_REQUEST_BASE_IDX … #define regSDMA0_QUEUE2_CONTEXT_STATUS … #define regSDMA0_QUEUE2_CONTEXT_STATUS_BASE_IDX … #define regSDMA0_QUEUE3_RB_CNTL … #define regSDMA0_QUEUE3_RB_CNTL_BASE_IDX … #define regSDMA0_QUEUE3_RB_BASE … #define regSDMA0_QUEUE3_RB_BASE_BASE_IDX … #define regSDMA0_QUEUE3_RB_BASE_HI … #define regSDMA0_QUEUE3_RB_BASE_HI_BASE_IDX … #define regSDMA0_QUEUE3_RB_RPTR … #define regSDMA0_QUEUE3_RB_RPTR_BASE_IDX … #define regSDMA0_QUEUE3_RB_RPTR_HI … #define regSDMA0_QUEUE3_RB_RPTR_HI_BASE_IDX … #define regSDMA0_QUEUE3_RB_WPTR … #define regSDMA0_QUEUE3_RB_WPTR_BASE_IDX … #define regSDMA0_QUEUE3_RB_WPTR_HI … #define regSDMA0_QUEUE3_RB_WPTR_HI_BASE_IDX … #define regSDMA0_QUEUE3_RB_RPTR_ADDR_LO … #define regSDMA0_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE3_RB_RPTR_ADDR_HI … #define regSDMA0_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE3_IB_CNTL … #define regSDMA0_QUEUE3_IB_CNTL_BASE_IDX … #define regSDMA0_QUEUE3_IB_RPTR … #define regSDMA0_QUEUE3_IB_RPTR_BASE_IDX … #define regSDMA0_QUEUE3_IB_OFFSET … #define regSDMA0_QUEUE3_IB_OFFSET_BASE_IDX … #define regSDMA0_QUEUE3_IB_BASE_LO … #define regSDMA0_QUEUE3_IB_BASE_LO_BASE_IDX … #define regSDMA0_QUEUE3_IB_BASE_HI … #define regSDMA0_QUEUE3_IB_BASE_HI_BASE_IDX … #define regSDMA0_QUEUE3_IB_SIZE … #define regSDMA0_QUEUE3_IB_SIZE_BASE_IDX … #define regSDMA0_QUEUE3_DOORBELL … #define regSDMA0_QUEUE3_DOORBELL_BASE_IDX … #define regSDMA0_QUEUE3_DOORBELL_LOG … #define regSDMA0_QUEUE3_DOORBELL_LOG_BASE_IDX … #define regSDMA0_QUEUE3_DOORBELL_OFFSET … #define regSDMA0_QUEUE3_DOORBELL_OFFSET_BASE_IDX … #define regSDMA0_QUEUE3_CSA_ADDR_LO … #define regSDMA0_QUEUE3_CSA_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE3_CSA_ADDR_HI … #define regSDMA0_QUEUE3_CSA_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE3_SCHEDULE_CNTL … #define regSDMA0_QUEUE3_SCHEDULE_CNTL_BASE_IDX … #define regSDMA0_QUEUE3_IB_SUB_REMAIN … #define regSDMA0_QUEUE3_IB_SUB_REMAIN_BASE_IDX … #define regSDMA0_QUEUE3_PREEMPT … #define regSDMA0_QUEUE3_PREEMPT_BASE_IDX … #define regSDMA0_QUEUE3_DUMMY_REG … #define regSDMA0_QUEUE3_DUMMY_REG_BASE_IDX … #define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO … #define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI … #define regSDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE3_RB_AQL_CNTL … #define regSDMA0_QUEUE3_RB_AQL_CNTL_BASE_IDX … #define regSDMA0_QUEUE3_MINOR_PTR_UPDATE … #define regSDMA0_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX … #define regSDMA0_QUEUE3_CONTEXT_SWITCH_STATUS … #define regSDMA0_QUEUE3_CONTEXT_SWITCH_STATUS_BASE_IDX … #define regSDMA0_QUEUE3_MIDCMD_CNTL … #define regSDMA0_QUEUE3_MIDCMD_CNTL_BASE_IDX … #define regSDMA0_QUEUE3_MIDCMD_DATA0 … #define regSDMA0_QUEUE3_MIDCMD_DATA0_BASE_IDX … #define regSDMA0_QUEUE3_MIDCMD_DATA1 … #define regSDMA0_QUEUE3_MIDCMD_DATA1_BASE_IDX … #define regSDMA0_QUEUE3_MIDCMD_DATA2 … #define regSDMA0_QUEUE3_MIDCMD_DATA2_BASE_IDX … #define regSDMA0_QUEUE3_MIDCMD_DATA3 … #define regSDMA0_QUEUE3_MIDCMD_DATA3_BASE_IDX … #define regSDMA0_QUEUE3_MIDCMD_DATA4 … #define regSDMA0_QUEUE3_MIDCMD_DATA4_BASE_IDX … #define regSDMA0_QUEUE3_MIDCMD_DATA5 … #define regSDMA0_QUEUE3_MIDCMD_DATA5_BASE_IDX … #define regSDMA0_QUEUE3_MIDCMD_DATA6 … #define regSDMA0_QUEUE3_MIDCMD_DATA6_BASE_IDX … #define regSDMA0_QUEUE3_MIDCMD_DATA7 … #define regSDMA0_QUEUE3_MIDCMD_DATA7_BASE_IDX … #define regSDMA0_QUEUE3_MIDCMD_DATA8 … #define regSDMA0_QUEUE3_MIDCMD_DATA8_BASE_IDX … #define regSDMA0_QUEUE3_MIDCMD_DATA9 … #define regSDMA0_QUEUE3_MIDCMD_DATA9_BASE_IDX … #define regSDMA0_QUEUE3_MIDCMD_DATA10 … #define regSDMA0_QUEUE3_MIDCMD_DATA10_BASE_IDX … #define regSDMA0_QUEUE3_WAIT_UNSATISFIED_THD … #define regSDMA0_QUEUE3_WAIT_UNSATISFIED_THD_BASE_IDX … #define regSDMA0_QUEUE3_MQD_BASE_ADDR_LO … #define regSDMA0_QUEUE3_MQD_BASE_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE3_MQD_BASE_ADDR_HI … #define regSDMA0_QUEUE3_MQD_BASE_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE3_MQD_CONTROL … #define regSDMA0_QUEUE3_MQD_CONTROL_BASE_IDX … #define regSDMA0_QUEUE3_DEQUEUE_REQUEST … #define regSDMA0_QUEUE3_DEQUEUE_REQUEST_BASE_IDX … #define regSDMA0_QUEUE3_CONTEXT_STATUS … #define regSDMA0_QUEUE3_CONTEXT_STATUS_BASE_IDX … #define regSDMA0_QUEUE4_RB_CNTL … #define regSDMA0_QUEUE4_RB_CNTL_BASE_IDX … #define regSDMA0_QUEUE4_RB_BASE … #define regSDMA0_QUEUE4_RB_BASE_BASE_IDX … #define regSDMA0_QUEUE4_RB_BASE_HI … #define regSDMA0_QUEUE4_RB_BASE_HI_BASE_IDX … #define regSDMA0_QUEUE4_RB_RPTR … #define regSDMA0_QUEUE4_RB_RPTR_BASE_IDX … #define regSDMA0_QUEUE4_RB_RPTR_HI … #define regSDMA0_QUEUE4_RB_RPTR_HI_BASE_IDX … #define regSDMA0_QUEUE4_RB_WPTR … #define regSDMA0_QUEUE4_RB_WPTR_BASE_IDX … #define regSDMA0_QUEUE4_RB_WPTR_HI … #define regSDMA0_QUEUE4_RB_WPTR_HI_BASE_IDX … #define regSDMA0_QUEUE4_RB_RPTR_ADDR_LO … #define regSDMA0_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE4_RB_RPTR_ADDR_HI … #define regSDMA0_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE4_IB_CNTL … #define regSDMA0_QUEUE4_IB_CNTL_BASE_IDX … #define regSDMA0_QUEUE4_IB_RPTR … #define regSDMA0_QUEUE4_IB_RPTR_BASE_IDX … #define regSDMA0_QUEUE4_IB_OFFSET … #define regSDMA0_QUEUE4_IB_OFFSET_BASE_IDX … #define regSDMA0_QUEUE4_IB_BASE_LO … #define regSDMA0_QUEUE4_IB_BASE_LO_BASE_IDX … #define regSDMA0_QUEUE4_IB_BASE_HI … #define regSDMA0_QUEUE4_IB_BASE_HI_BASE_IDX … #define regSDMA0_QUEUE4_IB_SIZE … #define regSDMA0_QUEUE4_IB_SIZE_BASE_IDX … #define regSDMA0_QUEUE4_DOORBELL … #define regSDMA0_QUEUE4_DOORBELL_BASE_IDX … #define regSDMA0_QUEUE4_DOORBELL_LOG … #define regSDMA0_QUEUE4_DOORBELL_LOG_BASE_IDX … #define regSDMA0_QUEUE4_DOORBELL_OFFSET … #define regSDMA0_QUEUE4_DOORBELL_OFFSET_BASE_IDX … #define regSDMA0_QUEUE4_CSA_ADDR_LO … #define regSDMA0_QUEUE4_CSA_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE4_CSA_ADDR_HI … #define regSDMA0_QUEUE4_CSA_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE4_SCHEDULE_CNTL … #define regSDMA0_QUEUE4_SCHEDULE_CNTL_BASE_IDX … #define regSDMA0_QUEUE4_IB_SUB_REMAIN … #define regSDMA0_QUEUE4_IB_SUB_REMAIN_BASE_IDX … #define regSDMA0_QUEUE4_PREEMPT … #define regSDMA0_QUEUE4_PREEMPT_BASE_IDX … #define regSDMA0_QUEUE4_DUMMY_REG … #define regSDMA0_QUEUE4_DUMMY_REG_BASE_IDX … #define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO … #define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI … #define regSDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE4_RB_AQL_CNTL … #define regSDMA0_QUEUE4_RB_AQL_CNTL_BASE_IDX … #define regSDMA0_QUEUE4_MINOR_PTR_UPDATE … #define regSDMA0_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX … #define regSDMA0_QUEUE4_CONTEXT_SWITCH_STATUS … #define regSDMA0_QUEUE4_CONTEXT_SWITCH_STATUS_BASE_IDX … #define regSDMA0_QUEUE4_MIDCMD_CNTL … #define regSDMA0_QUEUE4_MIDCMD_CNTL_BASE_IDX … #define regSDMA0_QUEUE4_MIDCMD_DATA0 … #define regSDMA0_QUEUE4_MIDCMD_DATA0_BASE_IDX … #define regSDMA0_QUEUE4_MIDCMD_DATA1 … #define regSDMA0_QUEUE4_MIDCMD_DATA1_BASE_IDX … #define regSDMA0_QUEUE4_MIDCMD_DATA2 … #define regSDMA0_QUEUE4_MIDCMD_DATA2_BASE_IDX … #define regSDMA0_QUEUE4_MIDCMD_DATA3 … #define regSDMA0_QUEUE4_MIDCMD_DATA3_BASE_IDX … #define regSDMA0_QUEUE4_MIDCMD_DATA4 … #define regSDMA0_QUEUE4_MIDCMD_DATA4_BASE_IDX … #define regSDMA0_QUEUE4_MIDCMD_DATA5 … #define regSDMA0_QUEUE4_MIDCMD_DATA5_BASE_IDX … #define regSDMA0_QUEUE4_MIDCMD_DATA6 … #define regSDMA0_QUEUE4_MIDCMD_DATA6_BASE_IDX … #define regSDMA0_QUEUE4_MIDCMD_DATA7 … #define regSDMA0_QUEUE4_MIDCMD_DATA7_BASE_IDX … #define regSDMA0_QUEUE4_MIDCMD_DATA8 … #define regSDMA0_QUEUE4_MIDCMD_DATA8_BASE_IDX … #define regSDMA0_QUEUE4_MIDCMD_DATA9 … #define regSDMA0_QUEUE4_MIDCMD_DATA9_BASE_IDX … #define regSDMA0_QUEUE4_MIDCMD_DATA10 … #define regSDMA0_QUEUE4_MIDCMD_DATA10_BASE_IDX … #define regSDMA0_QUEUE4_WAIT_UNSATISFIED_THD … #define regSDMA0_QUEUE4_WAIT_UNSATISFIED_THD_BASE_IDX … #define regSDMA0_QUEUE4_MQD_BASE_ADDR_LO … #define regSDMA0_QUEUE4_MQD_BASE_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE4_MQD_BASE_ADDR_HI … #define regSDMA0_QUEUE4_MQD_BASE_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE4_MQD_CONTROL … #define regSDMA0_QUEUE4_MQD_CONTROL_BASE_IDX … #define regSDMA0_QUEUE4_DEQUEUE_REQUEST … #define regSDMA0_QUEUE4_DEQUEUE_REQUEST_BASE_IDX … #define regSDMA0_QUEUE4_CONTEXT_STATUS … #define regSDMA0_QUEUE4_CONTEXT_STATUS_BASE_IDX … #define regSDMA0_QUEUE5_RB_CNTL … #define regSDMA0_QUEUE5_RB_CNTL_BASE_IDX … #define regSDMA0_QUEUE5_RB_BASE … #define regSDMA0_QUEUE5_RB_BASE_BASE_IDX … #define regSDMA0_QUEUE5_RB_BASE_HI … #define regSDMA0_QUEUE5_RB_BASE_HI_BASE_IDX … #define regSDMA0_QUEUE5_RB_RPTR … #define regSDMA0_QUEUE5_RB_RPTR_BASE_IDX … #define regSDMA0_QUEUE5_RB_RPTR_HI … #define regSDMA0_QUEUE5_RB_RPTR_HI_BASE_IDX … #define regSDMA0_QUEUE5_RB_WPTR … #define regSDMA0_QUEUE5_RB_WPTR_BASE_IDX … #define regSDMA0_QUEUE5_RB_WPTR_HI … #define regSDMA0_QUEUE5_RB_WPTR_HI_BASE_IDX … #define regSDMA0_QUEUE5_RB_RPTR_ADDR_LO … #define regSDMA0_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE5_RB_RPTR_ADDR_HI … #define regSDMA0_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE5_IB_CNTL … #define regSDMA0_QUEUE5_IB_CNTL_BASE_IDX … #define regSDMA0_QUEUE5_IB_RPTR … #define regSDMA0_QUEUE5_IB_RPTR_BASE_IDX … #define regSDMA0_QUEUE5_IB_OFFSET … #define regSDMA0_QUEUE5_IB_OFFSET_BASE_IDX … #define regSDMA0_QUEUE5_IB_BASE_LO … #define regSDMA0_QUEUE5_IB_BASE_LO_BASE_IDX … #define regSDMA0_QUEUE5_IB_BASE_HI … #define regSDMA0_QUEUE5_IB_BASE_HI_BASE_IDX … #define regSDMA0_QUEUE5_IB_SIZE … #define regSDMA0_QUEUE5_IB_SIZE_BASE_IDX … #define regSDMA0_QUEUE5_DOORBELL … #define regSDMA0_QUEUE5_DOORBELL_BASE_IDX … #define regSDMA0_QUEUE5_DOORBELL_LOG … #define regSDMA0_QUEUE5_DOORBELL_LOG_BASE_IDX … #define regSDMA0_QUEUE5_DOORBELL_OFFSET … #define regSDMA0_QUEUE5_DOORBELL_OFFSET_BASE_IDX … #define regSDMA0_QUEUE5_CSA_ADDR_LO … #define regSDMA0_QUEUE5_CSA_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE5_CSA_ADDR_HI … #define regSDMA0_QUEUE5_CSA_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE5_SCHEDULE_CNTL … #define regSDMA0_QUEUE5_SCHEDULE_CNTL_BASE_IDX … #define regSDMA0_QUEUE5_IB_SUB_REMAIN … #define regSDMA0_QUEUE5_IB_SUB_REMAIN_BASE_IDX … #define regSDMA0_QUEUE5_PREEMPT … #define regSDMA0_QUEUE5_PREEMPT_BASE_IDX … #define regSDMA0_QUEUE5_DUMMY_REG … #define regSDMA0_QUEUE5_DUMMY_REG_BASE_IDX … #define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO … #define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI … #define regSDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE5_RB_AQL_CNTL … #define regSDMA0_QUEUE5_RB_AQL_CNTL_BASE_IDX … #define regSDMA0_QUEUE5_MINOR_PTR_UPDATE … #define regSDMA0_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX … #define regSDMA0_QUEUE5_CONTEXT_SWITCH_STATUS … #define regSDMA0_QUEUE5_CONTEXT_SWITCH_STATUS_BASE_IDX … #define regSDMA0_QUEUE5_MIDCMD_CNTL … #define regSDMA0_QUEUE5_MIDCMD_CNTL_BASE_IDX … #define regSDMA0_QUEUE5_MIDCMD_DATA0 … #define regSDMA0_QUEUE5_MIDCMD_DATA0_BASE_IDX … #define regSDMA0_QUEUE5_MIDCMD_DATA1 … #define regSDMA0_QUEUE5_MIDCMD_DATA1_BASE_IDX … #define regSDMA0_QUEUE5_MIDCMD_DATA2 … #define regSDMA0_QUEUE5_MIDCMD_DATA2_BASE_IDX … #define regSDMA0_QUEUE5_MIDCMD_DATA3 … #define regSDMA0_QUEUE5_MIDCMD_DATA3_BASE_IDX … #define regSDMA0_QUEUE5_MIDCMD_DATA4 … #define regSDMA0_QUEUE5_MIDCMD_DATA4_BASE_IDX … #define regSDMA0_QUEUE5_MIDCMD_DATA5 … #define regSDMA0_QUEUE5_MIDCMD_DATA5_BASE_IDX … #define regSDMA0_QUEUE5_MIDCMD_DATA6 … #define regSDMA0_QUEUE5_MIDCMD_DATA6_BASE_IDX … #define regSDMA0_QUEUE5_MIDCMD_DATA7 … #define regSDMA0_QUEUE5_MIDCMD_DATA7_BASE_IDX … #define regSDMA0_QUEUE5_MIDCMD_DATA8 … #define regSDMA0_QUEUE5_MIDCMD_DATA8_BASE_IDX … #define regSDMA0_QUEUE5_MIDCMD_DATA9 … #define regSDMA0_QUEUE5_MIDCMD_DATA9_BASE_IDX … #define regSDMA0_QUEUE5_MIDCMD_DATA10 … #define regSDMA0_QUEUE5_MIDCMD_DATA10_BASE_IDX … #define regSDMA0_QUEUE5_WAIT_UNSATISFIED_THD … #define regSDMA0_QUEUE5_WAIT_UNSATISFIED_THD_BASE_IDX … #define regSDMA0_QUEUE5_MQD_BASE_ADDR_LO … #define regSDMA0_QUEUE5_MQD_BASE_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE5_MQD_BASE_ADDR_HI … #define regSDMA0_QUEUE5_MQD_BASE_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE5_MQD_CONTROL … #define regSDMA0_QUEUE5_MQD_CONTROL_BASE_IDX … #define regSDMA0_QUEUE5_DEQUEUE_REQUEST … #define regSDMA0_QUEUE5_DEQUEUE_REQUEST_BASE_IDX … #define regSDMA0_QUEUE5_CONTEXT_STATUS … #define regSDMA0_QUEUE5_CONTEXT_STATUS_BASE_IDX … #define regSDMA0_QUEUE6_RB_CNTL … #define regSDMA0_QUEUE6_RB_CNTL_BASE_IDX … #define regSDMA0_QUEUE6_RB_BASE … #define regSDMA0_QUEUE6_RB_BASE_BASE_IDX … #define regSDMA0_QUEUE6_RB_BASE_HI … #define regSDMA0_QUEUE6_RB_BASE_HI_BASE_IDX … #define regSDMA0_QUEUE6_RB_RPTR … #define regSDMA0_QUEUE6_RB_RPTR_BASE_IDX … #define regSDMA0_QUEUE6_RB_RPTR_HI … #define regSDMA0_QUEUE6_RB_RPTR_HI_BASE_IDX … #define regSDMA0_QUEUE6_RB_WPTR … #define regSDMA0_QUEUE6_RB_WPTR_BASE_IDX … #define regSDMA0_QUEUE6_RB_WPTR_HI … #define regSDMA0_QUEUE6_RB_WPTR_HI_BASE_IDX … #define regSDMA0_QUEUE6_RB_RPTR_ADDR_LO … #define regSDMA0_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE6_RB_RPTR_ADDR_HI … #define regSDMA0_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE6_IB_CNTL … #define regSDMA0_QUEUE6_IB_CNTL_BASE_IDX … #define regSDMA0_QUEUE6_IB_RPTR … #define regSDMA0_QUEUE6_IB_RPTR_BASE_IDX … #define regSDMA0_QUEUE6_IB_OFFSET … #define regSDMA0_QUEUE6_IB_OFFSET_BASE_IDX … #define regSDMA0_QUEUE6_IB_BASE_LO … #define regSDMA0_QUEUE6_IB_BASE_LO_BASE_IDX … #define regSDMA0_QUEUE6_IB_BASE_HI … #define regSDMA0_QUEUE6_IB_BASE_HI_BASE_IDX … #define regSDMA0_QUEUE6_IB_SIZE … #define regSDMA0_QUEUE6_IB_SIZE_BASE_IDX … #define regSDMA0_QUEUE6_DOORBELL … #define regSDMA0_QUEUE6_DOORBELL_BASE_IDX … #define regSDMA0_QUEUE6_DOORBELL_LOG … #define regSDMA0_QUEUE6_DOORBELL_LOG_BASE_IDX … #define regSDMA0_QUEUE6_DOORBELL_OFFSET … #define regSDMA0_QUEUE6_DOORBELL_OFFSET_BASE_IDX … #define regSDMA0_QUEUE6_CSA_ADDR_LO … #define regSDMA0_QUEUE6_CSA_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE6_CSA_ADDR_HI … #define regSDMA0_QUEUE6_CSA_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE6_SCHEDULE_CNTL … #define regSDMA0_QUEUE6_SCHEDULE_CNTL_BASE_IDX … #define regSDMA0_QUEUE6_IB_SUB_REMAIN … #define regSDMA0_QUEUE6_IB_SUB_REMAIN_BASE_IDX … #define regSDMA0_QUEUE6_PREEMPT … #define regSDMA0_QUEUE6_PREEMPT_BASE_IDX … #define regSDMA0_QUEUE6_DUMMY_REG … #define regSDMA0_QUEUE6_DUMMY_REG_BASE_IDX … #define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO … #define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI … #define regSDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE6_RB_AQL_CNTL … #define regSDMA0_QUEUE6_RB_AQL_CNTL_BASE_IDX … #define regSDMA0_QUEUE6_MINOR_PTR_UPDATE … #define regSDMA0_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX … #define regSDMA0_QUEUE6_CONTEXT_SWITCH_STATUS … #define regSDMA0_QUEUE6_CONTEXT_SWITCH_STATUS_BASE_IDX … #define regSDMA0_QUEUE6_MIDCMD_CNTL … #define regSDMA0_QUEUE6_MIDCMD_CNTL_BASE_IDX … #define regSDMA0_QUEUE6_MIDCMD_DATA0 … #define regSDMA0_QUEUE6_MIDCMD_DATA0_BASE_IDX … #define regSDMA0_QUEUE6_MIDCMD_DATA1 … #define regSDMA0_QUEUE6_MIDCMD_DATA1_BASE_IDX … #define regSDMA0_QUEUE6_MIDCMD_DATA2 … #define regSDMA0_QUEUE6_MIDCMD_DATA2_BASE_IDX … #define regSDMA0_QUEUE6_MIDCMD_DATA3 … #define regSDMA0_QUEUE6_MIDCMD_DATA3_BASE_IDX … #define regSDMA0_QUEUE6_MIDCMD_DATA4 … #define regSDMA0_QUEUE6_MIDCMD_DATA4_BASE_IDX … #define regSDMA0_QUEUE6_MIDCMD_DATA5 … #define regSDMA0_QUEUE6_MIDCMD_DATA5_BASE_IDX … #define regSDMA0_QUEUE6_MIDCMD_DATA6 … #define regSDMA0_QUEUE6_MIDCMD_DATA6_BASE_IDX … #define regSDMA0_QUEUE6_MIDCMD_DATA7 … #define regSDMA0_QUEUE6_MIDCMD_DATA7_BASE_IDX … #define regSDMA0_QUEUE6_MIDCMD_DATA8 … #define regSDMA0_QUEUE6_MIDCMD_DATA8_BASE_IDX … #define regSDMA0_QUEUE6_MIDCMD_DATA9 … #define regSDMA0_QUEUE6_MIDCMD_DATA9_BASE_IDX … #define regSDMA0_QUEUE6_MIDCMD_DATA10 … #define regSDMA0_QUEUE6_MIDCMD_DATA10_BASE_IDX … #define regSDMA0_QUEUE6_WAIT_UNSATISFIED_THD … #define regSDMA0_QUEUE6_WAIT_UNSATISFIED_THD_BASE_IDX … #define regSDMA0_QUEUE6_MQD_BASE_ADDR_LO … #define regSDMA0_QUEUE6_MQD_BASE_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE6_MQD_BASE_ADDR_HI … #define regSDMA0_QUEUE6_MQD_BASE_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE6_MQD_CONTROL … #define regSDMA0_QUEUE6_MQD_CONTROL_BASE_IDX … #define regSDMA0_QUEUE6_DEQUEUE_REQUEST … #define regSDMA0_QUEUE6_DEQUEUE_REQUEST_BASE_IDX … #define regSDMA0_QUEUE6_CONTEXT_STATUS … #define regSDMA0_QUEUE6_CONTEXT_STATUS_BASE_IDX … #define regSDMA0_QUEUE7_RB_CNTL … #define regSDMA0_QUEUE7_RB_CNTL_BASE_IDX … #define regSDMA0_QUEUE7_RB_BASE … #define regSDMA0_QUEUE7_RB_BASE_BASE_IDX … #define regSDMA0_QUEUE7_RB_BASE_HI … #define regSDMA0_QUEUE7_RB_BASE_HI_BASE_IDX … #define regSDMA0_QUEUE7_RB_RPTR … #define regSDMA0_QUEUE7_RB_RPTR_BASE_IDX … #define regSDMA0_QUEUE7_RB_RPTR_HI … #define regSDMA0_QUEUE7_RB_RPTR_HI_BASE_IDX … #define regSDMA0_QUEUE7_RB_WPTR … #define regSDMA0_QUEUE7_RB_WPTR_BASE_IDX … #define regSDMA0_QUEUE7_RB_WPTR_HI … #define regSDMA0_QUEUE7_RB_WPTR_HI_BASE_IDX … #define regSDMA0_QUEUE7_RB_RPTR_ADDR_LO … #define regSDMA0_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE7_RB_RPTR_ADDR_HI … #define regSDMA0_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE7_IB_CNTL … #define regSDMA0_QUEUE7_IB_CNTL_BASE_IDX … #define regSDMA0_QUEUE7_IB_RPTR … #define regSDMA0_QUEUE7_IB_RPTR_BASE_IDX … #define regSDMA0_QUEUE7_IB_OFFSET … #define regSDMA0_QUEUE7_IB_OFFSET_BASE_IDX … #define regSDMA0_QUEUE7_IB_BASE_LO … #define regSDMA0_QUEUE7_IB_BASE_LO_BASE_IDX … #define regSDMA0_QUEUE7_IB_BASE_HI … #define regSDMA0_QUEUE7_IB_BASE_HI_BASE_IDX … #define regSDMA0_QUEUE7_IB_SIZE … #define regSDMA0_QUEUE7_IB_SIZE_BASE_IDX … #define regSDMA0_QUEUE7_DOORBELL … #define regSDMA0_QUEUE7_DOORBELL_BASE_IDX … #define regSDMA0_QUEUE7_DOORBELL_LOG … #define regSDMA0_QUEUE7_DOORBELL_LOG_BASE_IDX … #define regSDMA0_QUEUE7_DOORBELL_OFFSET … #define regSDMA0_QUEUE7_DOORBELL_OFFSET_BASE_IDX … #define regSDMA0_QUEUE7_CSA_ADDR_LO … #define regSDMA0_QUEUE7_CSA_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE7_CSA_ADDR_HI … #define regSDMA0_QUEUE7_CSA_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE7_SCHEDULE_CNTL … #define regSDMA0_QUEUE7_SCHEDULE_CNTL_BASE_IDX … #define regSDMA0_QUEUE7_IB_SUB_REMAIN … #define regSDMA0_QUEUE7_IB_SUB_REMAIN_BASE_IDX … #define regSDMA0_QUEUE7_PREEMPT … #define regSDMA0_QUEUE7_PREEMPT_BASE_IDX … #define regSDMA0_QUEUE7_DUMMY_REG … #define regSDMA0_QUEUE7_DUMMY_REG_BASE_IDX … #define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO … #define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI … #define regSDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE7_RB_AQL_CNTL … #define regSDMA0_QUEUE7_RB_AQL_CNTL_BASE_IDX … #define regSDMA0_QUEUE7_MINOR_PTR_UPDATE … #define regSDMA0_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX … #define regSDMA0_QUEUE7_CONTEXT_SWITCH_STATUS … #define regSDMA0_QUEUE7_CONTEXT_SWITCH_STATUS_BASE_IDX … #define regSDMA0_QUEUE7_MIDCMD_CNTL … #define regSDMA0_QUEUE7_MIDCMD_CNTL_BASE_IDX … #define regSDMA0_QUEUE7_MIDCMD_DATA0 … #define regSDMA0_QUEUE7_MIDCMD_DATA0_BASE_IDX … #define regSDMA0_QUEUE7_MIDCMD_DATA1 … #define regSDMA0_QUEUE7_MIDCMD_DATA1_BASE_IDX … #define regSDMA0_QUEUE7_MIDCMD_DATA2 … #define regSDMA0_QUEUE7_MIDCMD_DATA2_BASE_IDX … #define regSDMA0_QUEUE7_MIDCMD_DATA3 … #define regSDMA0_QUEUE7_MIDCMD_DATA3_BASE_IDX … #define regSDMA0_QUEUE7_MIDCMD_DATA4 … #define regSDMA0_QUEUE7_MIDCMD_DATA4_BASE_IDX … #define regSDMA0_QUEUE7_MIDCMD_DATA5 … #define regSDMA0_QUEUE7_MIDCMD_DATA5_BASE_IDX … #define regSDMA0_QUEUE7_MIDCMD_DATA6 … #define regSDMA0_QUEUE7_MIDCMD_DATA6_BASE_IDX … #define regSDMA0_QUEUE7_MIDCMD_DATA7 … #define regSDMA0_QUEUE7_MIDCMD_DATA7_BASE_IDX … #define regSDMA0_QUEUE7_MIDCMD_DATA8 … #define regSDMA0_QUEUE7_MIDCMD_DATA8_BASE_IDX … #define regSDMA0_QUEUE7_MIDCMD_DATA9 … #define regSDMA0_QUEUE7_MIDCMD_DATA9_BASE_IDX … #define regSDMA0_QUEUE7_MIDCMD_DATA10 … #define regSDMA0_QUEUE7_MIDCMD_DATA10_BASE_IDX … #define regSDMA0_QUEUE7_WAIT_UNSATISFIED_THD … #define regSDMA0_QUEUE7_WAIT_UNSATISFIED_THD_BASE_IDX … #define regSDMA0_QUEUE7_MQD_BASE_ADDR_LO … #define regSDMA0_QUEUE7_MQD_BASE_ADDR_LO_BASE_IDX … #define regSDMA0_QUEUE7_MQD_BASE_ADDR_HI … #define regSDMA0_QUEUE7_MQD_BASE_ADDR_HI_BASE_IDX … #define regSDMA0_QUEUE7_MQD_CONTROL … #define regSDMA0_QUEUE7_MQD_CONTROL_BASE_IDX … #define regSDMA0_QUEUE7_DEQUEUE_REQUEST … #define regSDMA0_QUEUE7_DEQUEUE_REQUEST_BASE_IDX … #define regSDMA0_QUEUE7_CONTEXT_STATUS … #define regSDMA0_QUEUE7_CONTEXT_STATUS_BASE_IDX … // addressBlock: gc_gfx_cpwd_sdma0_sdmahypdec // base address: 0x3e200 #define regSDMA0_VM_CTX_LO … #define regSDMA0_VM_CTX_LO_BASE_IDX … #define regSDMA0_VM_CTX_HI … #define regSDMA0_VM_CTX_HI_BASE_IDX … #define regSDMA0_ACTIVE_FCN_ID … #define regSDMA0_ACTIVE_FCN_ID_BASE_IDX … #define regSDMA0_VIRT_RESET_REQ … #define regSDMA0_VIRT_RESET_REQ_BASE_IDX … #define regSDMA0_VM_CNTL … #define regSDMA0_VM_CNTL_BASE_IDX … #define regSDMA0_MCU_CNTL … #define regSDMA0_MCU_CNTL_BASE_IDX … #define regSDMA0_IC_BASE_LO … #define regSDMA0_IC_BASE_LO_BASE_IDX … #define regSDMA0_IC_BASE_HI … #define regSDMA0_IC_BASE_HI_BASE_IDX … #define regSDMA0_IC_BASE_CNTL … #define regSDMA0_IC_BASE_CNTL_BASE_IDX … #define regSDMA0_IC_OP_CNTL … #define regSDMA0_IC_OP_CNTL_BASE_IDX … #define regSDMA0_IC_CNTL … #define regSDMA0_IC_CNTL_BASE_IDX … // addressBlock: gc_gfx_cpwd_sdma0_sdmapspdec // base address: 0x3f200 #define regSDMA0_MCU_DM_FROM_RST_ADDR_OFFSET … #define regSDMA0_MCU_DM_FROM_RST_ADDR_OFFSET_BASE_IDX … // addressBlock: gc_gfx_cpwd_sdma0_sdmaperfsdec // base address: 0x37880 #define regSDMA0_PERFCNT_PERFCOUNTER0_CFG … #define regSDMA0_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX … #define regSDMA0_PERFCNT_PERFCOUNTER1_CFG … #define regSDMA0_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX … #define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL … #define regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define regSDMA0_PERFCNT_MISC_CNTL … #define regSDMA0_PERFCNT_MISC_CNTL_BASE_IDX … #define regSDMA0_PERFCOUNTER0_SELECT … #define regSDMA0_PERFCOUNTER0_SELECT_BASE_IDX … #define regSDMA0_PERFCOUNTER0_SELECT1 … #define regSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX … #define regSDMA0_PERFCOUNTER1_SELECT … #define regSDMA0_PERFCOUNTER1_SELECT_BASE_IDX … #define regSDMA0_PERFCOUNTER1_SELECT1 … #define regSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX … // addressBlock: gc_gfx_cpwd_sdma0_sdmaperfddec // base address: 0x35980 #define regSDMA0_PERFCNT_PERFCOUNTER_LO … #define regSDMA0_PERFCNT_PERFCOUNTER_LO_BASE_IDX … #define regSDMA0_PERFCNT_PERFCOUNTER_HI … #define regSDMA0_PERFCNT_PERFCOUNTER_HI_BASE_IDX … #define regSDMA0_PERFCOUNTER0_LO … #define regSDMA0_PERFCOUNTER0_LO_BASE_IDX … #define regSDMA0_PERFCOUNTER0_HI … #define regSDMA0_PERFCOUNTER0_HI_BASE_IDX … #define regSDMA0_PERFCOUNTER1_LO … #define regSDMA0_PERFCOUNTER1_LO_BASE_IDX … #define regSDMA0_PERFCOUNTER1_HI … #define regSDMA0_PERFCOUNTER1_HI_BASE_IDX … // addressBlock: gc_gfx_cpwd_sdma0_sdmapwrdec // base address: 0x3c430 #define regGFX_ICG_SDMA0_CTRL … #define regGFX_ICG_SDMA0_CTRL_BASE_IDX … // addressBlock: gc_gfx_cpwd_sdma0_sdmadec:1 // base address: 0x6180 #define regSDMA1_DEC_START … #define regSDMA1_DEC_START_BASE_IDX … #define regSDMA1_MCU_MISC_CNTL … #define regSDMA1_MCU_MISC_CNTL_BASE_IDX … #define regSDMA1_UCODE_REV … #define regSDMA1_UCODE_REV_BASE_IDX … #define regSDMA1_GLOBAL_TIMESTAMP_LO … #define regSDMA1_GLOBAL_TIMESTAMP_LO_BASE_IDX … #define regSDMA1_GLOBAL_TIMESTAMP_HI … #define regSDMA1_GLOBAL_TIMESTAMP_HI_BASE_IDX … #define regSDMA1_POWER_CNTL … #define regSDMA1_POWER_CNTL_BASE_IDX … #define regSDMA1_CNTL … #define regSDMA1_CNTL_BASE_IDX … #define regSDMA1_CHICKEN_BITS … #define regSDMA1_CHICKEN_BITS_BASE_IDX … #define regSDMA1_CACHE_CNTL … #define regSDMA1_CACHE_CNTL_BASE_IDX … #define regSDMA1_RB_RPTR_FETCH … #define regSDMA1_RB_RPTR_FETCH_BASE_IDX … #define regSDMA1_RB_RPTR_FETCH_HI … #define regSDMA1_RB_RPTR_FETCH_HI_BASE_IDX … #define regSDMA1_IB_OFFSET_FETCH … #define regSDMA1_IB_OFFSET_FETCH_BASE_IDX … #define regSDMA1_PROGRAM … #define regSDMA1_PROGRAM_BASE_IDX … #define regSDMA1_STATUS_REG … #define regSDMA1_STATUS_REG_BASE_IDX … #define regSDMA1_STATUS1_REG … #define regSDMA1_STATUS1_REG_BASE_IDX … #define regSDMA1_CNTL1 … #define regSDMA1_CNTL1_BASE_IDX … #define regSDMA1_HBM_PAGE_CONFIG … #define regSDMA1_HBM_PAGE_CONFIG_BASE_IDX … #define regSDMA1_FREEZE … #define regSDMA1_FREEZE_BASE_IDX … #define regSDMA1_PROCESS_QUANTUM0 … #define regSDMA1_PROCESS_QUANTUM0_BASE_IDX … #define regSDMA1_PROCESS_QUANTUM1 … #define regSDMA1_PROCESS_QUANTUM1_BASE_IDX … #define regSDMA1_WATCHDOG_CNTL … #define regSDMA1_WATCHDOG_CNTL_BASE_IDX … #define regSDMA1_QUEUE_STATUS0 … #define regSDMA1_QUEUE_STATUS0_BASE_IDX … #define regSDMA1_EDC_CONFIG … #define regSDMA1_EDC_CONFIG_BASE_IDX … #define regSDMA1_ID … #define regSDMA1_ID_BASE_IDX … #define regSDMA1_VERSION … #define regSDMA1_VERSION_BASE_IDX … #define regSDMA1_STATUS2_REG … #define regSDMA1_STATUS2_REG_BASE_IDX … #define regSDMA1_ATOMIC_CNTL … #define regSDMA1_ATOMIC_CNTL_BASE_IDX … #define regSDMA1_ATOMIC_PREOP_LO … #define regSDMA1_ATOMIC_PREOP_LO_BASE_IDX … #define regSDMA1_ATOMIC_PREOP_HI … #define regSDMA1_ATOMIC_PREOP_HI_BASE_IDX … #define regSDMA1_DCC_CNTL … #define regSDMA1_DCC_CNTL_BASE_IDX … #define regSDMA1_UTCL1_CNTL … #define regSDMA1_UTCL1_CNTL_BASE_IDX … #define regSDMA1_UTCL1_WATERMK … #define regSDMA1_UTCL1_WATERMK_BASE_IDX … #define regSDMA1_UTCL1_TIMEOUT … #define regSDMA1_UTCL1_TIMEOUT_BASE_IDX … #define regSDMA1_UTCL1_PAGE … #define regSDMA1_UTCL1_PAGE_BASE_IDX … #define regSDMA1_EXTERNAL_FROZEN … #define regSDMA1_EXTERNAL_FROZEN_BASE_IDX … #define regSDMA1_UTCL1_RD_STATUS … #define regSDMA1_UTCL1_RD_STATUS_BASE_IDX … #define regSDMA1_UTCL1_WR_STATUS … #define regSDMA1_UTCL1_WR_STATUS_BASE_IDX … #define regSDMA1_UTCL1_INV0 … #define regSDMA1_UTCL1_INV0_BASE_IDX … #define regSDMA1_UTCL1_INV1 … #define regSDMA1_UTCL1_INV1_BASE_IDX … #define regSDMA1_UTCL1_INV2 … #define regSDMA1_UTCL1_INV2_BASE_IDX … #define regSDMA1_UTCL1_RD_XNACK0 … #define regSDMA1_UTCL1_RD_XNACK0_BASE_IDX … #define regSDMA1_UTCL1_RD_XNACK1 … #define regSDMA1_UTCL1_RD_XNACK1_BASE_IDX … #define regSDMA1_UTCL1_WR_XNACK0 … #define regSDMA1_UTCL1_WR_XNACK0_BASE_IDX … #define regSDMA1_UTCL1_WR_XNACK1 … #define regSDMA1_UTCL1_WR_XNACK1_BASE_IDX … #define regSDMA1_RELAX_ORDERING_LUT … #define regSDMA1_RELAX_ORDERING_LUT_BASE_IDX … #define regSDMA1_CHICKEN_BITS_2 … #define regSDMA1_CHICKEN_BITS_2_BASE_IDX … #define regSDMA1_STATUS3_REG … #define regSDMA1_STATUS3_REG_BASE_IDX … #define regSDMA1_GLOBAL_QUANTUM … #define regSDMA1_GLOBAL_QUANTUM_BASE_IDX … #define regSDMA1_ERROR_LOG … #define regSDMA1_ERROR_LOG_BASE_IDX … #define regSDMA1_PUB_DUMMY_REG0 … #define regSDMA1_PUB_DUMMY_REG0_BASE_IDX … #define regSDMA1_PUB_DUMMY_REG1 … #define regSDMA1_PUB_DUMMY_REG1_BASE_IDX … #define regSDMA1_PUB_DUMMY_REG2 … #define regSDMA1_PUB_DUMMY_REG2_BASE_IDX … #define regSDMA1_PUB_DUMMY_REG3 … #define regSDMA1_PUB_DUMMY_REG3_BASE_IDX … #define regSDMA1_MCU_COUNTER … #define regSDMA1_MCU_COUNTER_BASE_IDX … #define regSDMA1_CRD_CNTL … #define regSDMA1_CRD_CNTL_BASE_IDX … #define regSDMA1_RLC_CGCG_CTRL … #define regSDMA1_RLC_CGCG_CTRL_BASE_IDX … #define regSDMA1_GPU_IOV_VIOLATION_LOG … #define regSDMA1_GPU_IOV_VIOLATION_LOG_BASE_IDX … #define regSDMA1_AQL_STATUS … #define regSDMA1_AQL_STATUS_BASE_IDX … #define regSDMA1_TLBI_GCR_CNTL … #define regSDMA1_TLBI_GCR_CNTL_BASE_IDX … #define regSDMA1_INT_STATUS … #define regSDMA1_INT_STATUS_BASE_IDX … #define regSDMA1_GPU_IOV_VIOLATION_LOG2 … #define regSDMA1_GPU_IOV_VIOLATION_LOG2_BASE_IDX … #define regSDMA1_INVALID_ADDR_LO … #define regSDMA1_INVALID_ADDR_LO_BASE_IDX … #define regSDMA1_INVALID_ADDR_HI … #define regSDMA1_INVALID_ADDR_HI_BASE_IDX … #define regSDMA1_INVALID_ADDR_SRC … #define regSDMA1_INVALID_ADDR_SRC_BASE_IDX … #define regSDMA1_CLOCK_GATING_STATUS … #define regSDMA1_CLOCK_GATING_STATUS_BASE_IDX … #define regSDMA1_STATUS4_REG … #define regSDMA1_STATUS4_REG_BASE_IDX … #define regSDMA1_SCRATCH_RAM_DATA … #define regSDMA1_SCRATCH_RAM_DATA_BASE_IDX … #define regSDMA1_SCRATCH_RAM_ADDR … #define regSDMA1_SCRATCH_RAM_ADDR_BASE_IDX … #define regSDMA1_TIMESTAMP_CNTL … #define regSDMA1_TIMESTAMP_CNTL_BASE_IDX … #define regSDMA1_STATUS5_REG … #define regSDMA1_STATUS5_REG_BASE_IDX … #define regSDMA1_QUEUE_RESET_REQ … #define regSDMA1_QUEUE_RESET_REQ_BASE_IDX … #define regSDMA1_STATUS6_REG … #define regSDMA1_STATUS6_REG_BASE_IDX … #define regSDMA1_STATUS7_REG … #define regSDMA1_STATUS7_REG_BASE_IDX … #define regSDMA1_STATUS8_REG … #define regSDMA1_STATUS8_REG_BASE_IDX … #define regSDMA1_CE_CTRL … #define regSDMA1_CE_CTRL_BASE_IDX … #define regSDMA1_FED_STATUS … #define regSDMA1_FED_STATUS_BASE_IDX … #define regSDMA1_QUEUE0_RB_CNTL … #define regSDMA1_QUEUE0_RB_CNTL_BASE_IDX … #define regSDMA1_QUEUE0_RB_BASE … #define regSDMA1_QUEUE0_RB_BASE_BASE_IDX … #define regSDMA1_QUEUE0_RB_BASE_HI … #define regSDMA1_QUEUE0_RB_BASE_HI_BASE_IDX … #define regSDMA1_QUEUE0_RB_RPTR … #define regSDMA1_QUEUE0_RB_RPTR_BASE_IDX … #define regSDMA1_QUEUE0_RB_RPTR_HI … #define regSDMA1_QUEUE0_RB_RPTR_HI_BASE_IDX … #define regSDMA1_QUEUE0_RB_WPTR … #define regSDMA1_QUEUE0_RB_WPTR_BASE_IDX … #define regSDMA1_QUEUE0_RB_WPTR_HI … #define regSDMA1_QUEUE0_RB_WPTR_HI_BASE_IDX … #define regSDMA1_QUEUE0_RB_RPTR_ADDR_LO … #define regSDMA1_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE0_RB_RPTR_ADDR_HI … #define regSDMA1_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE0_IB_CNTL … #define regSDMA1_QUEUE0_IB_CNTL_BASE_IDX … #define regSDMA1_QUEUE0_IB_RPTR … #define regSDMA1_QUEUE0_IB_RPTR_BASE_IDX … #define regSDMA1_QUEUE0_IB_OFFSET … #define regSDMA1_QUEUE0_IB_OFFSET_BASE_IDX … #define regSDMA1_QUEUE0_IB_BASE_LO … #define regSDMA1_QUEUE0_IB_BASE_LO_BASE_IDX … #define regSDMA1_QUEUE0_IB_BASE_HI … #define regSDMA1_QUEUE0_IB_BASE_HI_BASE_IDX … #define regSDMA1_QUEUE0_IB_SIZE … #define regSDMA1_QUEUE0_IB_SIZE_BASE_IDX … #define regSDMA1_QUEUE0_DOORBELL … #define regSDMA1_QUEUE0_DOORBELL_BASE_IDX … #define regSDMA1_QUEUE0_DOORBELL_LOG … #define regSDMA1_QUEUE0_DOORBELL_LOG_BASE_IDX … #define regSDMA1_QUEUE0_DOORBELL_OFFSET … #define regSDMA1_QUEUE0_DOORBELL_OFFSET_BASE_IDX … #define regSDMA1_QUEUE0_CSA_ADDR_LO … #define regSDMA1_QUEUE0_CSA_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE0_CSA_ADDR_HI … #define regSDMA1_QUEUE0_CSA_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE0_SCHEDULE_CNTL … #define regSDMA1_QUEUE0_SCHEDULE_CNTL_BASE_IDX … #define regSDMA1_QUEUE0_IB_SUB_REMAIN … #define regSDMA1_QUEUE0_IB_SUB_REMAIN_BASE_IDX … #define regSDMA1_QUEUE0_PREEMPT … #define regSDMA1_QUEUE0_PREEMPT_BASE_IDX … #define regSDMA1_QUEUE0_DUMMY_REG … #define regSDMA1_QUEUE0_DUMMY_REG_BASE_IDX … #define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO … #define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI … #define regSDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE0_RB_AQL_CNTL … #define regSDMA1_QUEUE0_RB_AQL_CNTL_BASE_IDX … #define regSDMA1_QUEUE0_MINOR_PTR_UPDATE … #define regSDMA1_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX … #define regSDMA1_QUEUE0_CONTEXT_SWITCH_STATUS … #define regSDMA1_QUEUE0_CONTEXT_SWITCH_STATUS_BASE_IDX … #define regSDMA1_QUEUE0_MIDCMD_CNTL … #define regSDMA1_QUEUE0_MIDCMD_CNTL_BASE_IDX … #define regSDMA1_QUEUE0_MIDCMD_DATA0 … #define regSDMA1_QUEUE0_MIDCMD_DATA0_BASE_IDX … #define regSDMA1_QUEUE0_MIDCMD_DATA1 … #define regSDMA1_QUEUE0_MIDCMD_DATA1_BASE_IDX … #define regSDMA1_QUEUE0_MIDCMD_DATA2 … #define regSDMA1_QUEUE0_MIDCMD_DATA2_BASE_IDX … #define regSDMA1_QUEUE0_MIDCMD_DATA3 … #define regSDMA1_QUEUE0_MIDCMD_DATA3_BASE_IDX … #define regSDMA1_QUEUE0_MIDCMD_DATA4 … #define regSDMA1_QUEUE0_MIDCMD_DATA4_BASE_IDX … #define regSDMA1_QUEUE0_MIDCMD_DATA5 … #define regSDMA1_QUEUE0_MIDCMD_DATA5_BASE_IDX … #define regSDMA1_QUEUE0_MIDCMD_DATA6 … #define regSDMA1_QUEUE0_MIDCMD_DATA6_BASE_IDX … #define regSDMA1_QUEUE0_MIDCMD_DATA7 … #define regSDMA1_QUEUE0_MIDCMD_DATA7_BASE_IDX … #define regSDMA1_QUEUE0_MIDCMD_DATA8 … #define regSDMA1_QUEUE0_MIDCMD_DATA8_BASE_IDX … #define regSDMA1_QUEUE0_MIDCMD_DATA9 … #define regSDMA1_QUEUE0_MIDCMD_DATA9_BASE_IDX … #define regSDMA1_QUEUE0_MIDCMD_DATA10 … #define regSDMA1_QUEUE0_MIDCMD_DATA10_BASE_IDX … #define regSDMA1_QUEUE0_WAIT_UNSATISFIED_THD … #define regSDMA1_QUEUE0_WAIT_UNSATISFIED_THD_BASE_IDX … #define regSDMA1_QUEUE0_MQD_BASE_ADDR_LO … #define regSDMA1_QUEUE0_MQD_BASE_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE0_MQD_BASE_ADDR_HI … #define regSDMA1_QUEUE0_MQD_BASE_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE0_MQD_CONTROL … #define regSDMA1_QUEUE0_MQD_CONTROL_BASE_IDX … #define regSDMA1_QUEUE0_DEQUEUE_REQUEST … #define regSDMA1_QUEUE0_DEQUEUE_REQUEST_BASE_IDX … #define regSDMA1_QUEUE0_CONTEXT_STATUS … #define regSDMA1_QUEUE0_CONTEXT_STATUS_BASE_IDX … #define regSDMA1_QUEUE1_RB_CNTL … #define regSDMA1_QUEUE1_RB_CNTL_BASE_IDX … #define regSDMA1_QUEUE1_RB_BASE … #define regSDMA1_QUEUE1_RB_BASE_BASE_IDX … #define regSDMA1_QUEUE1_RB_BASE_HI … #define regSDMA1_QUEUE1_RB_BASE_HI_BASE_IDX … #define regSDMA1_QUEUE1_RB_RPTR … #define regSDMA1_QUEUE1_RB_RPTR_BASE_IDX … #define regSDMA1_QUEUE1_RB_RPTR_HI … #define regSDMA1_QUEUE1_RB_RPTR_HI_BASE_IDX … #define regSDMA1_QUEUE1_RB_WPTR … #define regSDMA1_QUEUE1_RB_WPTR_BASE_IDX … #define regSDMA1_QUEUE1_RB_WPTR_HI … #define regSDMA1_QUEUE1_RB_WPTR_HI_BASE_IDX … #define regSDMA1_QUEUE1_RB_RPTR_ADDR_LO … #define regSDMA1_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE1_RB_RPTR_ADDR_HI … #define regSDMA1_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE1_IB_CNTL … #define regSDMA1_QUEUE1_IB_CNTL_BASE_IDX … #define regSDMA1_QUEUE1_IB_RPTR … #define regSDMA1_QUEUE1_IB_RPTR_BASE_IDX … #define regSDMA1_QUEUE1_IB_OFFSET … #define regSDMA1_QUEUE1_IB_OFFSET_BASE_IDX … #define regSDMA1_QUEUE1_IB_BASE_LO … #define regSDMA1_QUEUE1_IB_BASE_LO_BASE_IDX … #define regSDMA1_QUEUE1_IB_BASE_HI … #define regSDMA1_QUEUE1_IB_BASE_HI_BASE_IDX … #define regSDMA1_QUEUE1_IB_SIZE … #define regSDMA1_QUEUE1_IB_SIZE_BASE_IDX … #define regSDMA1_QUEUE1_DOORBELL … #define regSDMA1_QUEUE1_DOORBELL_BASE_IDX … #define regSDMA1_QUEUE1_DOORBELL_LOG … #define regSDMA1_QUEUE1_DOORBELL_LOG_BASE_IDX … #define regSDMA1_QUEUE1_DOORBELL_OFFSET … #define regSDMA1_QUEUE1_DOORBELL_OFFSET_BASE_IDX … #define regSDMA1_QUEUE1_CSA_ADDR_LO … #define regSDMA1_QUEUE1_CSA_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE1_CSA_ADDR_HI … #define regSDMA1_QUEUE1_CSA_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE1_SCHEDULE_CNTL … #define regSDMA1_QUEUE1_SCHEDULE_CNTL_BASE_IDX … #define regSDMA1_QUEUE1_IB_SUB_REMAIN … #define regSDMA1_QUEUE1_IB_SUB_REMAIN_BASE_IDX … #define regSDMA1_QUEUE1_PREEMPT … #define regSDMA1_QUEUE1_PREEMPT_BASE_IDX … #define regSDMA1_QUEUE1_DUMMY_REG … #define regSDMA1_QUEUE1_DUMMY_REG_BASE_IDX … #define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO … #define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI … #define regSDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE1_RB_AQL_CNTL … #define regSDMA1_QUEUE1_RB_AQL_CNTL_BASE_IDX … #define regSDMA1_QUEUE1_MINOR_PTR_UPDATE … #define regSDMA1_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX … #define regSDMA1_QUEUE1_CONTEXT_SWITCH_STATUS … #define regSDMA1_QUEUE1_CONTEXT_SWITCH_STATUS_BASE_IDX … #define regSDMA1_QUEUE1_MIDCMD_CNTL … #define regSDMA1_QUEUE1_MIDCMD_CNTL_BASE_IDX … #define regSDMA1_QUEUE1_MIDCMD_DATA0 … #define regSDMA1_QUEUE1_MIDCMD_DATA0_BASE_IDX … #define regSDMA1_QUEUE1_MIDCMD_DATA1 … #define regSDMA1_QUEUE1_MIDCMD_DATA1_BASE_IDX … #define regSDMA1_QUEUE1_MIDCMD_DATA2 … #define regSDMA1_QUEUE1_MIDCMD_DATA2_BASE_IDX … #define regSDMA1_QUEUE1_MIDCMD_DATA3 … #define regSDMA1_QUEUE1_MIDCMD_DATA3_BASE_IDX … #define regSDMA1_QUEUE1_MIDCMD_DATA4 … #define regSDMA1_QUEUE1_MIDCMD_DATA4_BASE_IDX … #define regSDMA1_QUEUE1_MIDCMD_DATA5 … #define regSDMA1_QUEUE1_MIDCMD_DATA5_BASE_IDX … #define regSDMA1_QUEUE1_MIDCMD_DATA6 … #define regSDMA1_QUEUE1_MIDCMD_DATA6_BASE_IDX … #define regSDMA1_QUEUE1_MIDCMD_DATA7 … #define regSDMA1_QUEUE1_MIDCMD_DATA7_BASE_IDX … #define regSDMA1_QUEUE1_MIDCMD_DATA8 … #define regSDMA1_QUEUE1_MIDCMD_DATA8_BASE_IDX … #define regSDMA1_QUEUE1_MIDCMD_DATA9 … #define regSDMA1_QUEUE1_MIDCMD_DATA9_BASE_IDX … #define regSDMA1_QUEUE1_MIDCMD_DATA10 … #define regSDMA1_QUEUE1_MIDCMD_DATA10_BASE_IDX … #define regSDMA1_QUEUE1_WAIT_UNSATISFIED_THD … #define regSDMA1_QUEUE1_WAIT_UNSATISFIED_THD_BASE_IDX … #define regSDMA1_QUEUE1_MQD_BASE_ADDR_LO … #define regSDMA1_QUEUE1_MQD_BASE_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE1_MQD_BASE_ADDR_HI … #define regSDMA1_QUEUE1_MQD_BASE_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE1_MQD_CONTROL … #define regSDMA1_QUEUE1_MQD_CONTROL_BASE_IDX … #define regSDMA1_QUEUE1_DEQUEUE_REQUEST … #define regSDMA1_QUEUE1_DEQUEUE_REQUEST_BASE_IDX … #define regSDMA1_QUEUE1_CONTEXT_STATUS … #define regSDMA1_QUEUE1_CONTEXT_STATUS_BASE_IDX … #define regSDMA1_QUEUE2_RB_CNTL … #define regSDMA1_QUEUE2_RB_CNTL_BASE_IDX … #define regSDMA1_QUEUE2_RB_BASE … #define regSDMA1_QUEUE2_RB_BASE_BASE_IDX … #define regSDMA1_QUEUE2_RB_BASE_HI … #define regSDMA1_QUEUE2_RB_BASE_HI_BASE_IDX … #define regSDMA1_QUEUE2_RB_RPTR … #define regSDMA1_QUEUE2_RB_RPTR_BASE_IDX … #define regSDMA1_QUEUE2_RB_RPTR_HI … #define regSDMA1_QUEUE2_RB_RPTR_HI_BASE_IDX … #define regSDMA1_QUEUE2_RB_WPTR … #define regSDMA1_QUEUE2_RB_WPTR_BASE_IDX … #define regSDMA1_QUEUE2_RB_WPTR_HI … #define regSDMA1_QUEUE2_RB_WPTR_HI_BASE_IDX … #define regSDMA1_QUEUE2_RB_RPTR_ADDR_LO … #define regSDMA1_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE2_RB_RPTR_ADDR_HI … #define regSDMA1_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE2_IB_CNTL … #define regSDMA1_QUEUE2_IB_CNTL_BASE_IDX … #define regSDMA1_QUEUE2_IB_RPTR … #define regSDMA1_QUEUE2_IB_RPTR_BASE_IDX … #define regSDMA1_QUEUE2_IB_OFFSET … #define regSDMA1_QUEUE2_IB_OFFSET_BASE_IDX … #define regSDMA1_QUEUE2_IB_BASE_LO … #define regSDMA1_QUEUE2_IB_BASE_LO_BASE_IDX … #define regSDMA1_QUEUE2_IB_BASE_HI … #define regSDMA1_QUEUE2_IB_BASE_HI_BASE_IDX … #define regSDMA1_QUEUE2_IB_SIZE … #define regSDMA1_QUEUE2_IB_SIZE_BASE_IDX … #define regSDMA1_QUEUE2_DOORBELL … #define regSDMA1_QUEUE2_DOORBELL_BASE_IDX … #define regSDMA1_QUEUE2_DOORBELL_LOG … #define regSDMA1_QUEUE2_DOORBELL_LOG_BASE_IDX … #define regSDMA1_QUEUE2_DOORBELL_OFFSET … #define regSDMA1_QUEUE2_DOORBELL_OFFSET_BASE_IDX … #define regSDMA1_QUEUE2_CSA_ADDR_LO … #define regSDMA1_QUEUE2_CSA_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE2_CSA_ADDR_HI … #define regSDMA1_QUEUE2_CSA_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE2_SCHEDULE_CNTL … #define regSDMA1_QUEUE2_SCHEDULE_CNTL_BASE_IDX … #define regSDMA1_QUEUE2_IB_SUB_REMAIN … #define regSDMA1_QUEUE2_IB_SUB_REMAIN_BASE_IDX … #define regSDMA1_QUEUE2_PREEMPT … #define regSDMA1_QUEUE2_PREEMPT_BASE_IDX … #define regSDMA1_QUEUE2_DUMMY_REG … #define regSDMA1_QUEUE2_DUMMY_REG_BASE_IDX … #define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO … #define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI … #define regSDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE2_RB_AQL_CNTL … #define regSDMA1_QUEUE2_RB_AQL_CNTL_BASE_IDX … #define regSDMA1_QUEUE2_MINOR_PTR_UPDATE … #define regSDMA1_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX … #define regSDMA1_QUEUE2_CONTEXT_SWITCH_STATUS … #define regSDMA1_QUEUE2_CONTEXT_SWITCH_STATUS_BASE_IDX … #define regSDMA1_QUEUE2_MIDCMD_CNTL … #define regSDMA1_QUEUE2_MIDCMD_CNTL_BASE_IDX … #define regSDMA1_QUEUE2_MIDCMD_DATA0 … #define regSDMA1_QUEUE2_MIDCMD_DATA0_BASE_IDX … #define regSDMA1_QUEUE2_MIDCMD_DATA1 … #define regSDMA1_QUEUE2_MIDCMD_DATA1_BASE_IDX … #define regSDMA1_QUEUE2_MIDCMD_DATA2 … #define regSDMA1_QUEUE2_MIDCMD_DATA2_BASE_IDX … #define regSDMA1_QUEUE2_MIDCMD_DATA3 … #define regSDMA1_QUEUE2_MIDCMD_DATA3_BASE_IDX … #define regSDMA1_QUEUE2_MIDCMD_DATA4 … #define regSDMA1_QUEUE2_MIDCMD_DATA4_BASE_IDX … #define regSDMA1_QUEUE2_MIDCMD_DATA5 … #define regSDMA1_QUEUE2_MIDCMD_DATA5_BASE_IDX … #define regSDMA1_QUEUE2_MIDCMD_DATA6 … #define regSDMA1_QUEUE2_MIDCMD_DATA6_BASE_IDX … #define regSDMA1_QUEUE2_MIDCMD_DATA7 … #define regSDMA1_QUEUE2_MIDCMD_DATA7_BASE_IDX … #define regSDMA1_QUEUE2_MIDCMD_DATA8 … #define regSDMA1_QUEUE2_MIDCMD_DATA8_BASE_IDX … #define regSDMA1_QUEUE2_MIDCMD_DATA9 … #define regSDMA1_QUEUE2_MIDCMD_DATA9_BASE_IDX … #define regSDMA1_QUEUE2_MIDCMD_DATA10 … #define regSDMA1_QUEUE2_MIDCMD_DATA10_BASE_IDX … #define regSDMA1_QUEUE2_WAIT_UNSATISFIED_THD … #define regSDMA1_QUEUE2_WAIT_UNSATISFIED_THD_BASE_IDX … #define regSDMA1_QUEUE2_MQD_BASE_ADDR_LO … #define regSDMA1_QUEUE2_MQD_BASE_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE2_MQD_BASE_ADDR_HI … #define regSDMA1_QUEUE2_MQD_BASE_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE2_MQD_CONTROL … #define regSDMA1_QUEUE2_MQD_CONTROL_BASE_IDX … #define regSDMA1_QUEUE2_DEQUEUE_REQUEST … #define regSDMA1_QUEUE2_DEQUEUE_REQUEST_BASE_IDX … #define regSDMA1_QUEUE2_CONTEXT_STATUS … #define regSDMA1_QUEUE2_CONTEXT_STATUS_BASE_IDX … #define regSDMA1_QUEUE3_RB_CNTL … #define regSDMA1_QUEUE3_RB_CNTL_BASE_IDX … #define regSDMA1_QUEUE3_RB_BASE … #define regSDMA1_QUEUE3_RB_BASE_BASE_IDX … #define regSDMA1_QUEUE3_RB_BASE_HI … #define regSDMA1_QUEUE3_RB_BASE_HI_BASE_IDX … #define regSDMA1_QUEUE3_RB_RPTR … #define regSDMA1_QUEUE3_RB_RPTR_BASE_IDX … #define regSDMA1_QUEUE3_RB_RPTR_HI … #define regSDMA1_QUEUE3_RB_RPTR_HI_BASE_IDX … #define regSDMA1_QUEUE3_RB_WPTR … #define regSDMA1_QUEUE3_RB_WPTR_BASE_IDX … #define regSDMA1_QUEUE3_RB_WPTR_HI … #define regSDMA1_QUEUE3_RB_WPTR_HI_BASE_IDX … #define regSDMA1_QUEUE3_RB_RPTR_ADDR_LO … #define regSDMA1_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE3_RB_RPTR_ADDR_HI … #define regSDMA1_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE3_IB_CNTL … #define regSDMA1_QUEUE3_IB_CNTL_BASE_IDX … #define regSDMA1_QUEUE3_IB_RPTR … #define regSDMA1_QUEUE3_IB_RPTR_BASE_IDX … #define regSDMA1_QUEUE3_IB_OFFSET … #define regSDMA1_QUEUE3_IB_OFFSET_BASE_IDX … #define regSDMA1_QUEUE3_IB_BASE_LO … #define regSDMA1_QUEUE3_IB_BASE_LO_BASE_IDX … #define regSDMA1_QUEUE3_IB_BASE_HI … #define regSDMA1_QUEUE3_IB_BASE_HI_BASE_IDX … #define regSDMA1_QUEUE3_IB_SIZE … #define regSDMA1_QUEUE3_IB_SIZE_BASE_IDX … #define regSDMA1_QUEUE3_DOORBELL … #define regSDMA1_QUEUE3_DOORBELL_BASE_IDX … #define regSDMA1_QUEUE3_DOORBELL_LOG … #define regSDMA1_QUEUE3_DOORBELL_LOG_BASE_IDX … #define regSDMA1_QUEUE3_DOORBELL_OFFSET … #define regSDMA1_QUEUE3_DOORBELL_OFFSET_BASE_IDX … #define regSDMA1_QUEUE3_CSA_ADDR_LO … #define regSDMA1_QUEUE3_CSA_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE3_CSA_ADDR_HI … #define regSDMA1_QUEUE3_CSA_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE3_SCHEDULE_CNTL … #define regSDMA1_QUEUE3_SCHEDULE_CNTL_BASE_IDX … #define regSDMA1_QUEUE3_IB_SUB_REMAIN … #define regSDMA1_QUEUE3_IB_SUB_REMAIN_BASE_IDX … #define regSDMA1_QUEUE3_PREEMPT … #define regSDMA1_QUEUE3_PREEMPT_BASE_IDX … #define regSDMA1_QUEUE3_DUMMY_REG … #define regSDMA1_QUEUE3_DUMMY_REG_BASE_IDX … #define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO … #define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI … #define regSDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE3_RB_AQL_CNTL … #define regSDMA1_QUEUE3_RB_AQL_CNTL_BASE_IDX … #define regSDMA1_QUEUE3_MINOR_PTR_UPDATE … #define regSDMA1_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX … #define regSDMA1_QUEUE3_CONTEXT_SWITCH_STATUS … #define regSDMA1_QUEUE3_CONTEXT_SWITCH_STATUS_BASE_IDX … #define regSDMA1_QUEUE3_MIDCMD_CNTL … #define regSDMA1_QUEUE3_MIDCMD_CNTL_BASE_IDX … #define regSDMA1_QUEUE3_MIDCMD_DATA0 … #define regSDMA1_QUEUE3_MIDCMD_DATA0_BASE_IDX … #define regSDMA1_QUEUE3_MIDCMD_DATA1 … #define regSDMA1_QUEUE3_MIDCMD_DATA1_BASE_IDX … #define regSDMA1_QUEUE3_MIDCMD_DATA2 … #define regSDMA1_QUEUE3_MIDCMD_DATA2_BASE_IDX … #define regSDMA1_QUEUE3_MIDCMD_DATA3 … #define regSDMA1_QUEUE3_MIDCMD_DATA3_BASE_IDX … #define regSDMA1_QUEUE3_MIDCMD_DATA4 … #define regSDMA1_QUEUE3_MIDCMD_DATA4_BASE_IDX … #define regSDMA1_QUEUE3_MIDCMD_DATA5 … #define regSDMA1_QUEUE3_MIDCMD_DATA5_BASE_IDX … #define regSDMA1_QUEUE3_MIDCMD_DATA6 … #define regSDMA1_QUEUE3_MIDCMD_DATA6_BASE_IDX … #define regSDMA1_QUEUE3_MIDCMD_DATA7 … #define regSDMA1_QUEUE3_MIDCMD_DATA7_BASE_IDX … #define regSDMA1_QUEUE3_MIDCMD_DATA8 … #define regSDMA1_QUEUE3_MIDCMD_DATA8_BASE_IDX … #define regSDMA1_QUEUE3_MIDCMD_DATA9 … #define regSDMA1_QUEUE3_MIDCMD_DATA9_BASE_IDX … #define regSDMA1_QUEUE3_MIDCMD_DATA10 … #define regSDMA1_QUEUE3_MIDCMD_DATA10_BASE_IDX … #define regSDMA1_QUEUE3_WAIT_UNSATISFIED_THD … #define regSDMA1_QUEUE3_WAIT_UNSATISFIED_THD_BASE_IDX … #define regSDMA1_QUEUE3_MQD_BASE_ADDR_LO … #define regSDMA1_QUEUE3_MQD_BASE_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE3_MQD_BASE_ADDR_HI … #define regSDMA1_QUEUE3_MQD_BASE_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE3_MQD_CONTROL … #define regSDMA1_QUEUE3_MQD_CONTROL_BASE_IDX … #define regSDMA1_QUEUE3_DEQUEUE_REQUEST … #define regSDMA1_QUEUE3_DEQUEUE_REQUEST_BASE_IDX … #define regSDMA1_QUEUE3_CONTEXT_STATUS … #define regSDMA1_QUEUE3_CONTEXT_STATUS_BASE_IDX … #define regSDMA1_QUEUE4_RB_CNTL … #define regSDMA1_QUEUE4_RB_CNTL_BASE_IDX … #define regSDMA1_QUEUE4_RB_BASE … #define regSDMA1_QUEUE4_RB_BASE_BASE_IDX … #define regSDMA1_QUEUE4_RB_BASE_HI … #define regSDMA1_QUEUE4_RB_BASE_HI_BASE_IDX … #define regSDMA1_QUEUE4_RB_RPTR … #define regSDMA1_QUEUE4_RB_RPTR_BASE_IDX … #define regSDMA1_QUEUE4_RB_RPTR_HI … #define regSDMA1_QUEUE4_RB_RPTR_HI_BASE_IDX … #define regSDMA1_QUEUE4_RB_WPTR … #define regSDMA1_QUEUE4_RB_WPTR_BASE_IDX … #define regSDMA1_QUEUE4_RB_WPTR_HI … #define regSDMA1_QUEUE4_RB_WPTR_HI_BASE_IDX … #define regSDMA1_QUEUE4_RB_RPTR_ADDR_LO … #define regSDMA1_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE4_RB_RPTR_ADDR_HI … #define regSDMA1_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE4_IB_CNTL … #define regSDMA1_QUEUE4_IB_CNTL_BASE_IDX … #define regSDMA1_QUEUE4_IB_RPTR … #define regSDMA1_QUEUE4_IB_RPTR_BASE_IDX … #define regSDMA1_QUEUE4_IB_OFFSET … #define regSDMA1_QUEUE4_IB_OFFSET_BASE_IDX … #define regSDMA1_QUEUE4_IB_BASE_LO … #define regSDMA1_QUEUE4_IB_BASE_LO_BASE_IDX … #define regSDMA1_QUEUE4_IB_BASE_HI … #define regSDMA1_QUEUE4_IB_BASE_HI_BASE_IDX … #define regSDMA1_QUEUE4_IB_SIZE … #define regSDMA1_QUEUE4_IB_SIZE_BASE_IDX … #define regSDMA1_QUEUE4_DOORBELL … #define regSDMA1_QUEUE4_DOORBELL_BASE_IDX … #define regSDMA1_QUEUE4_DOORBELL_LOG … #define regSDMA1_QUEUE4_DOORBELL_LOG_BASE_IDX … #define regSDMA1_QUEUE4_DOORBELL_OFFSET … #define regSDMA1_QUEUE4_DOORBELL_OFFSET_BASE_IDX … #define regSDMA1_QUEUE4_CSA_ADDR_LO … #define regSDMA1_QUEUE4_CSA_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE4_CSA_ADDR_HI … #define regSDMA1_QUEUE4_CSA_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE4_SCHEDULE_CNTL … #define regSDMA1_QUEUE4_SCHEDULE_CNTL_BASE_IDX … #define regSDMA1_QUEUE4_IB_SUB_REMAIN … #define regSDMA1_QUEUE4_IB_SUB_REMAIN_BASE_IDX … #define regSDMA1_QUEUE4_PREEMPT … #define regSDMA1_QUEUE4_PREEMPT_BASE_IDX … #define regSDMA1_QUEUE4_DUMMY_REG … #define regSDMA1_QUEUE4_DUMMY_REG_BASE_IDX … #define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO … #define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI … #define regSDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE4_RB_AQL_CNTL … #define regSDMA1_QUEUE4_RB_AQL_CNTL_BASE_IDX … #define regSDMA1_QUEUE4_MINOR_PTR_UPDATE … #define regSDMA1_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX … #define regSDMA1_QUEUE4_CONTEXT_SWITCH_STATUS … #define regSDMA1_QUEUE4_CONTEXT_SWITCH_STATUS_BASE_IDX … #define regSDMA1_QUEUE4_MIDCMD_CNTL … #define regSDMA1_QUEUE4_MIDCMD_CNTL_BASE_IDX … #define regSDMA1_QUEUE4_MIDCMD_DATA0 … #define regSDMA1_QUEUE4_MIDCMD_DATA0_BASE_IDX … #define regSDMA1_QUEUE4_MIDCMD_DATA1 … #define regSDMA1_QUEUE4_MIDCMD_DATA1_BASE_IDX … #define regSDMA1_QUEUE4_MIDCMD_DATA2 … #define regSDMA1_QUEUE4_MIDCMD_DATA2_BASE_IDX … #define regSDMA1_QUEUE4_MIDCMD_DATA3 … #define regSDMA1_QUEUE4_MIDCMD_DATA3_BASE_IDX … #define regSDMA1_QUEUE4_MIDCMD_DATA4 … #define regSDMA1_QUEUE4_MIDCMD_DATA4_BASE_IDX … #define regSDMA1_QUEUE4_MIDCMD_DATA5 … #define regSDMA1_QUEUE4_MIDCMD_DATA5_BASE_IDX … #define regSDMA1_QUEUE4_MIDCMD_DATA6 … #define regSDMA1_QUEUE4_MIDCMD_DATA6_BASE_IDX … #define regSDMA1_QUEUE4_MIDCMD_DATA7 … #define regSDMA1_QUEUE4_MIDCMD_DATA7_BASE_IDX … #define regSDMA1_QUEUE4_MIDCMD_DATA8 … #define regSDMA1_QUEUE4_MIDCMD_DATA8_BASE_IDX … #define regSDMA1_QUEUE4_MIDCMD_DATA9 … #define regSDMA1_QUEUE4_MIDCMD_DATA9_BASE_IDX … #define regSDMA1_QUEUE4_MIDCMD_DATA10 … #define regSDMA1_QUEUE4_MIDCMD_DATA10_BASE_IDX … #define regSDMA1_QUEUE4_WAIT_UNSATISFIED_THD … #define regSDMA1_QUEUE4_WAIT_UNSATISFIED_THD_BASE_IDX … #define regSDMA1_QUEUE4_MQD_BASE_ADDR_LO … #define regSDMA1_QUEUE4_MQD_BASE_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE4_MQD_BASE_ADDR_HI … #define regSDMA1_QUEUE4_MQD_BASE_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE4_MQD_CONTROL … #define regSDMA1_QUEUE4_MQD_CONTROL_BASE_IDX … #define regSDMA1_QUEUE4_DEQUEUE_REQUEST … #define regSDMA1_QUEUE4_DEQUEUE_REQUEST_BASE_IDX … #define regSDMA1_QUEUE4_CONTEXT_STATUS … #define regSDMA1_QUEUE4_CONTEXT_STATUS_BASE_IDX … #define regSDMA1_QUEUE5_RB_CNTL … #define regSDMA1_QUEUE5_RB_CNTL_BASE_IDX … #define regSDMA1_QUEUE5_RB_BASE … #define regSDMA1_QUEUE5_RB_BASE_BASE_IDX … #define regSDMA1_QUEUE5_RB_BASE_HI … #define regSDMA1_QUEUE5_RB_BASE_HI_BASE_IDX … #define regSDMA1_QUEUE5_RB_RPTR … #define regSDMA1_QUEUE5_RB_RPTR_BASE_IDX … #define regSDMA1_QUEUE5_RB_RPTR_HI … #define regSDMA1_QUEUE5_RB_RPTR_HI_BASE_IDX … #define regSDMA1_QUEUE5_RB_WPTR … #define regSDMA1_QUEUE5_RB_WPTR_BASE_IDX … #define regSDMA1_QUEUE5_RB_WPTR_HI … #define regSDMA1_QUEUE5_RB_WPTR_HI_BASE_IDX … #define regSDMA1_QUEUE5_RB_RPTR_ADDR_LO … #define regSDMA1_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE5_RB_RPTR_ADDR_HI … #define regSDMA1_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE5_IB_CNTL … #define regSDMA1_QUEUE5_IB_CNTL_BASE_IDX … #define regSDMA1_QUEUE5_IB_RPTR … #define regSDMA1_QUEUE5_IB_RPTR_BASE_IDX … #define regSDMA1_QUEUE5_IB_OFFSET … #define regSDMA1_QUEUE5_IB_OFFSET_BASE_IDX … #define regSDMA1_QUEUE5_IB_BASE_LO … #define regSDMA1_QUEUE5_IB_BASE_LO_BASE_IDX … #define regSDMA1_QUEUE5_IB_BASE_HI … #define regSDMA1_QUEUE5_IB_BASE_HI_BASE_IDX … #define regSDMA1_QUEUE5_IB_SIZE … #define regSDMA1_QUEUE5_IB_SIZE_BASE_IDX … #define regSDMA1_QUEUE5_DOORBELL … #define regSDMA1_QUEUE5_DOORBELL_BASE_IDX … #define regSDMA1_QUEUE5_DOORBELL_LOG … #define regSDMA1_QUEUE5_DOORBELL_LOG_BASE_IDX … #define regSDMA1_QUEUE5_DOORBELL_OFFSET … #define regSDMA1_QUEUE5_DOORBELL_OFFSET_BASE_IDX … #define regSDMA1_QUEUE5_CSA_ADDR_LO … #define regSDMA1_QUEUE5_CSA_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE5_CSA_ADDR_HI … #define regSDMA1_QUEUE5_CSA_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE5_SCHEDULE_CNTL … #define regSDMA1_QUEUE5_SCHEDULE_CNTL_BASE_IDX … #define regSDMA1_QUEUE5_IB_SUB_REMAIN … #define regSDMA1_QUEUE5_IB_SUB_REMAIN_BASE_IDX … #define regSDMA1_QUEUE5_PREEMPT … #define regSDMA1_QUEUE5_PREEMPT_BASE_IDX … #define regSDMA1_QUEUE5_DUMMY_REG … #define regSDMA1_QUEUE5_DUMMY_REG_BASE_IDX … #define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO … #define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI … #define regSDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE5_RB_AQL_CNTL … #define regSDMA1_QUEUE5_RB_AQL_CNTL_BASE_IDX … #define regSDMA1_QUEUE5_MINOR_PTR_UPDATE … #define regSDMA1_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX … #define regSDMA1_QUEUE5_CONTEXT_SWITCH_STATUS … #define regSDMA1_QUEUE5_CONTEXT_SWITCH_STATUS_BASE_IDX … #define regSDMA1_QUEUE5_MIDCMD_CNTL … #define regSDMA1_QUEUE5_MIDCMD_CNTL_BASE_IDX … #define regSDMA1_QUEUE5_MIDCMD_DATA0 … #define regSDMA1_QUEUE5_MIDCMD_DATA0_BASE_IDX … #define regSDMA1_QUEUE5_MIDCMD_DATA1 … #define regSDMA1_QUEUE5_MIDCMD_DATA1_BASE_IDX … #define regSDMA1_QUEUE5_MIDCMD_DATA2 … #define regSDMA1_QUEUE5_MIDCMD_DATA2_BASE_IDX … #define regSDMA1_QUEUE5_MIDCMD_DATA3 … #define regSDMA1_QUEUE5_MIDCMD_DATA3_BASE_IDX … #define regSDMA1_QUEUE5_MIDCMD_DATA4 … #define regSDMA1_QUEUE5_MIDCMD_DATA4_BASE_IDX … #define regSDMA1_QUEUE5_MIDCMD_DATA5 … #define regSDMA1_QUEUE5_MIDCMD_DATA5_BASE_IDX … #define regSDMA1_QUEUE5_MIDCMD_DATA6 … #define regSDMA1_QUEUE5_MIDCMD_DATA6_BASE_IDX … #define regSDMA1_QUEUE5_MIDCMD_DATA7 … #define regSDMA1_QUEUE5_MIDCMD_DATA7_BASE_IDX … #define regSDMA1_QUEUE5_MIDCMD_DATA8 … #define regSDMA1_QUEUE5_MIDCMD_DATA8_BASE_IDX … #define regSDMA1_QUEUE5_MIDCMD_DATA9 … #define regSDMA1_QUEUE5_MIDCMD_DATA9_BASE_IDX … #define regSDMA1_QUEUE5_MIDCMD_DATA10 … #define regSDMA1_QUEUE5_MIDCMD_DATA10_BASE_IDX … #define regSDMA1_QUEUE5_WAIT_UNSATISFIED_THD … #define regSDMA1_QUEUE5_WAIT_UNSATISFIED_THD_BASE_IDX … #define regSDMA1_QUEUE5_MQD_BASE_ADDR_LO … #define regSDMA1_QUEUE5_MQD_BASE_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE5_MQD_BASE_ADDR_HI … #define regSDMA1_QUEUE5_MQD_BASE_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE5_MQD_CONTROL … #define regSDMA1_QUEUE5_MQD_CONTROL_BASE_IDX … #define regSDMA1_QUEUE5_DEQUEUE_REQUEST … #define regSDMA1_QUEUE5_DEQUEUE_REQUEST_BASE_IDX … #define regSDMA1_QUEUE5_CONTEXT_STATUS … #define regSDMA1_QUEUE5_CONTEXT_STATUS_BASE_IDX … #define regSDMA1_QUEUE6_RB_CNTL … #define regSDMA1_QUEUE6_RB_CNTL_BASE_IDX … #define regSDMA1_QUEUE6_RB_BASE … #define regSDMA1_QUEUE6_RB_BASE_BASE_IDX … #define regSDMA1_QUEUE6_RB_BASE_HI … #define regSDMA1_QUEUE6_RB_BASE_HI_BASE_IDX … #define regSDMA1_QUEUE6_RB_RPTR … #define regSDMA1_QUEUE6_RB_RPTR_BASE_IDX … #define regSDMA1_QUEUE6_RB_RPTR_HI … #define regSDMA1_QUEUE6_RB_RPTR_HI_BASE_IDX … #define regSDMA1_QUEUE6_RB_WPTR … #define regSDMA1_QUEUE6_RB_WPTR_BASE_IDX … #define regSDMA1_QUEUE6_RB_WPTR_HI … #define regSDMA1_QUEUE6_RB_WPTR_HI_BASE_IDX … #define regSDMA1_QUEUE6_RB_RPTR_ADDR_LO … #define regSDMA1_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE6_RB_RPTR_ADDR_HI … #define regSDMA1_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE6_IB_CNTL … #define regSDMA1_QUEUE6_IB_CNTL_BASE_IDX … #define regSDMA1_QUEUE6_IB_RPTR … #define regSDMA1_QUEUE6_IB_RPTR_BASE_IDX … #define regSDMA1_QUEUE6_IB_OFFSET … #define regSDMA1_QUEUE6_IB_OFFSET_BASE_IDX … #define regSDMA1_QUEUE6_IB_BASE_LO … #define regSDMA1_QUEUE6_IB_BASE_LO_BASE_IDX … #define regSDMA1_QUEUE6_IB_BASE_HI … #define regSDMA1_QUEUE6_IB_BASE_HI_BASE_IDX … #define regSDMA1_QUEUE6_IB_SIZE … #define regSDMA1_QUEUE6_IB_SIZE_BASE_IDX … #define regSDMA1_QUEUE6_DOORBELL … #define regSDMA1_QUEUE6_DOORBELL_BASE_IDX … #define regSDMA1_QUEUE6_DOORBELL_LOG … #define regSDMA1_QUEUE6_DOORBELL_LOG_BASE_IDX … #define regSDMA1_QUEUE6_DOORBELL_OFFSET … #define regSDMA1_QUEUE6_DOORBELL_OFFSET_BASE_IDX … #define regSDMA1_QUEUE6_CSA_ADDR_LO … #define regSDMA1_QUEUE6_CSA_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE6_CSA_ADDR_HI … #define regSDMA1_QUEUE6_CSA_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE6_SCHEDULE_CNTL … #define regSDMA1_QUEUE6_SCHEDULE_CNTL_BASE_IDX … #define regSDMA1_QUEUE6_IB_SUB_REMAIN … #define regSDMA1_QUEUE6_IB_SUB_REMAIN_BASE_IDX … #define regSDMA1_QUEUE6_PREEMPT … #define regSDMA1_QUEUE6_PREEMPT_BASE_IDX … #define regSDMA1_QUEUE6_DUMMY_REG … #define regSDMA1_QUEUE6_DUMMY_REG_BASE_IDX … #define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO … #define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI … #define regSDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE6_RB_AQL_CNTL … #define regSDMA1_QUEUE6_RB_AQL_CNTL_BASE_IDX … #define regSDMA1_QUEUE6_MINOR_PTR_UPDATE … #define regSDMA1_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX … #define regSDMA1_QUEUE6_CONTEXT_SWITCH_STATUS … #define regSDMA1_QUEUE6_CONTEXT_SWITCH_STATUS_BASE_IDX … #define regSDMA1_QUEUE6_MIDCMD_CNTL … #define regSDMA1_QUEUE6_MIDCMD_CNTL_BASE_IDX … #define regSDMA1_QUEUE6_MIDCMD_DATA0 … #define regSDMA1_QUEUE6_MIDCMD_DATA0_BASE_IDX … #define regSDMA1_QUEUE6_MIDCMD_DATA1 … #define regSDMA1_QUEUE6_MIDCMD_DATA1_BASE_IDX … #define regSDMA1_QUEUE6_MIDCMD_DATA2 … #define regSDMA1_QUEUE6_MIDCMD_DATA2_BASE_IDX … #define regSDMA1_QUEUE6_MIDCMD_DATA3 … #define regSDMA1_QUEUE6_MIDCMD_DATA3_BASE_IDX … #define regSDMA1_QUEUE6_MIDCMD_DATA4 … #define regSDMA1_QUEUE6_MIDCMD_DATA4_BASE_IDX … #define regSDMA1_QUEUE6_MIDCMD_DATA5 … #define regSDMA1_QUEUE6_MIDCMD_DATA5_BASE_IDX … #define regSDMA1_QUEUE6_MIDCMD_DATA6 … #define regSDMA1_QUEUE6_MIDCMD_DATA6_BASE_IDX … #define regSDMA1_QUEUE6_MIDCMD_DATA7 … #define regSDMA1_QUEUE6_MIDCMD_DATA7_BASE_IDX … #define regSDMA1_QUEUE6_MIDCMD_DATA8 … #define regSDMA1_QUEUE6_MIDCMD_DATA8_BASE_IDX … #define regSDMA1_QUEUE6_MIDCMD_DATA9 … #define regSDMA1_QUEUE6_MIDCMD_DATA9_BASE_IDX … #define regSDMA1_QUEUE6_MIDCMD_DATA10 … #define regSDMA1_QUEUE6_MIDCMD_DATA10_BASE_IDX … #define regSDMA1_QUEUE6_WAIT_UNSATISFIED_THD … #define regSDMA1_QUEUE6_WAIT_UNSATISFIED_THD_BASE_IDX … #define regSDMA1_QUEUE6_MQD_BASE_ADDR_LO … #define regSDMA1_QUEUE6_MQD_BASE_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE6_MQD_BASE_ADDR_HI … #define regSDMA1_QUEUE6_MQD_BASE_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE6_MQD_CONTROL … #define regSDMA1_QUEUE6_MQD_CONTROL_BASE_IDX … #define regSDMA1_QUEUE6_DEQUEUE_REQUEST … #define regSDMA1_QUEUE6_DEQUEUE_REQUEST_BASE_IDX … #define regSDMA1_QUEUE6_CONTEXT_STATUS … #define regSDMA1_QUEUE6_CONTEXT_STATUS_BASE_IDX … #define regSDMA1_QUEUE7_RB_CNTL … #define regSDMA1_QUEUE7_RB_CNTL_BASE_IDX … #define regSDMA1_QUEUE7_RB_BASE … #define regSDMA1_QUEUE7_RB_BASE_BASE_IDX … #define regSDMA1_QUEUE7_RB_BASE_HI … #define regSDMA1_QUEUE7_RB_BASE_HI_BASE_IDX … #define regSDMA1_QUEUE7_RB_RPTR … #define regSDMA1_QUEUE7_RB_RPTR_BASE_IDX … #define regSDMA1_QUEUE7_RB_RPTR_HI … #define regSDMA1_QUEUE7_RB_RPTR_HI_BASE_IDX … #define regSDMA1_QUEUE7_RB_WPTR … #define regSDMA1_QUEUE7_RB_WPTR_BASE_IDX … #define regSDMA1_QUEUE7_RB_WPTR_HI … #define regSDMA1_QUEUE7_RB_WPTR_HI_BASE_IDX … #define regSDMA1_QUEUE7_RB_RPTR_ADDR_LO … #define regSDMA1_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE7_RB_RPTR_ADDR_HI … #define regSDMA1_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE7_IB_CNTL … #define regSDMA1_QUEUE7_IB_CNTL_BASE_IDX … #define regSDMA1_QUEUE7_IB_RPTR … #define regSDMA1_QUEUE7_IB_RPTR_BASE_IDX … #define regSDMA1_QUEUE7_IB_OFFSET … #define regSDMA1_QUEUE7_IB_OFFSET_BASE_IDX … #define regSDMA1_QUEUE7_IB_BASE_LO … #define regSDMA1_QUEUE7_IB_BASE_LO_BASE_IDX … #define regSDMA1_QUEUE7_IB_BASE_HI … #define regSDMA1_QUEUE7_IB_BASE_HI_BASE_IDX … #define regSDMA1_QUEUE7_IB_SIZE … #define regSDMA1_QUEUE7_IB_SIZE_BASE_IDX … #define regSDMA1_QUEUE7_DOORBELL … #define regSDMA1_QUEUE7_DOORBELL_BASE_IDX … #define regSDMA1_QUEUE7_DOORBELL_LOG … #define regSDMA1_QUEUE7_DOORBELL_LOG_BASE_IDX … #define regSDMA1_QUEUE7_DOORBELL_OFFSET … #define regSDMA1_QUEUE7_DOORBELL_OFFSET_BASE_IDX … #define regSDMA1_QUEUE7_CSA_ADDR_LO … #define regSDMA1_QUEUE7_CSA_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE7_CSA_ADDR_HI … #define regSDMA1_QUEUE7_CSA_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE7_SCHEDULE_CNTL … #define regSDMA1_QUEUE7_SCHEDULE_CNTL_BASE_IDX … #define regSDMA1_QUEUE7_IB_SUB_REMAIN … #define regSDMA1_QUEUE7_IB_SUB_REMAIN_BASE_IDX … #define regSDMA1_QUEUE7_PREEMPT … #define regSDMA1_QUEUE7_PREEMPT_BASE_IDX … #define regSDMA1_QUEUE7_DUMMY_REG … #define regSDMA1_QUEUE7_DUMMY_REG_BASE_IDX … #define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO … #define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI … #define regSDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE7_RB_AQL_CNTL … #define regSDMA1_QUEUE7_RB_AQL_CNTL_BASE_IDX … #define regSDMA1_QUEUE7_MINOR_PTR_UPDATE … #define regSDMA1_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX … #define regSDMA1_QUEUE7_CONTEXT_SWITCH_STATUS … #define regSDMA1_QUEUE7_CONTEXT_SWITCH_STATUS_BASE_IDX … #define regSDMA1_QUEUE7_MIDCMD_CNTL … #define regSDMA1_QUEUE7_MIDCMD_CNTL_BASE_IDX … #define regSDMA1_QUEUE7_MIDCMD_DATA0 … #define regSDMA1_QUEUE7_MIDCMD_DATA0_BASE_IDX … #define regSDMA1_QUEUE7_MIDCMD_DATA1 … #define regSDMA1_QUEUE7_MIDCMD_DATA1_BASE_IDX … #define regSDMA1_QUEUE7_MIDCMD_DATA2 … #define regSDMA1_QUEUE7_MIDCMD_DATA2_BASE_IDX … #define regSDMA1_QUEUE7_MIDCMD_DATA3 … #define regSDMA1_QUEUE7_MIDCMD_DATA3_BASE_IDX … #define regSDMA1_QUEUE7_MIDCMD_DATA4 … #define regSDMA1_QUEUE7_MIDCMD_DATA4_BASE_IDX … #define regSDMA1_QUEUE7_MIDCMD_DATA5 … #define regSDMA1_QUEUE7_MIDCMD_DATA5_BASE_IDX … #define regSDMA1_QUEUE7_MIDCMD_DATA6 … #define regSDMA1_QUEUE7_MIDCMD_DATA6_BASE_IDX … #define regSDMA1_QUEUE7_MIDCMD_DATA7 … #define regSDMA1_QUEUE7_MIDCMD_DATA7_BASE_IDX … #define regSDMA1_QUEUE7_MIDCMD_DATA8 … #define regSDMA1_QUEUE7_MIDCMD_DATA8_BASE_IDX … #define regSDMA1_QUEUE7_MIDCMD_DATA9 … #define regSDMA1_QUEUE7_MIDCMD_DATA9_BASE_IDX … #define regSDMA1_QUEUE7_MIDCMD_DATA10 … #define regSDMA1_QUEUE7_MIDCMD_DATA10_BASE_IDX … #define regSDMA1_QUEUE7_WAIT_UNSATISFIED_THD … #define regSDMA1_QUEUE7_WAIT_UNSATISFIED_THD_BASE_IDX … #define regSDMA1_QUEUE7_MQD_BASE_ADDR_LO … #define regSDMA1_QUEUE7_MQD_BASE_ADDR_LO_BASE_IDX … #define regSDMA1_QUEUE7_MQD_BASE_ADDR_HI … #define regSDMA1_QUEUE7_MQD_BASE_ADDR_HI_BASE_IDX … #define regSDMA1_QUEUE7_MQD_CONTROL … #define regSDMA1_QUEUE7_MQD_CONTROL_BASE_IDX … #define regSDMA1_QUEUE7_DEQUEUE_REQUEST … #define regSDMA1_QUEUE7_DEQUEUE_REQUEST_BASE_IDX … #define regSDMA1_QUEUE7_CONTEXT_STATUS … #define regSDMA1_QUEUE7_CONTEXT_STATUS_BASE_IDX … // addressBlock: gc_gfx_cpwd_sdma0_sdmahypdec:1 // base address: 0x3e280 #define regSDMA1_VM_CTX_LO … #define regSDMA1_VM_CTX_LO_BASE_IDX … #define regSDMA1_VM_CTX_HI … #define regSDMA1_VM_CTX_HI_BASE_IDX … #define regSDMA1_ACTIVE_FCN_ID … #define regSDMA1_ACTIVE_FCN_ID_BASE_IDX … #define regSDMA1_VIRT_RESET_REQ … #define regSDMA1_VIRT_RESET_REQ_BASE_IDX … #define regSDMA1_VM_CNTL … #define regSDMA1_VM_CNTL_BASE_IDX … #define regSDMA1_MCU_CNTL … #define regSDMA1_MCU_CNTL_BASE_IDX … #define regSDMA1_IC_BASE_LO … #define regSDMA1_IC_BASE_LO_BASE_IDX … #define regSDMA1_IC_BASE_HI … #define regSDMA1_IC_BASE_HI_BASE_IDX … #define regSDMA1_IC_BASE_CNTL … #define regSDMA1_IC_BASE_CNTL_BASE_IDX … #define regSDMA1_IC_OP_CNTL … #define regSDMA1_IC_OP_CNTL_BASE_IDX … #define regSDMA1_IC_CNTL … #define regSDMA1_IC_CNTL_BASE_IDX … // addressBlock: gc_gfx_cpwd_sdma0_sdmapspdec:1 // base address: 0x3f340 #define regSDMA1_MCU_DM_FROM_RST_ADDR_OFFSET … #define regSDMA1_MCU_DM_FROM_RST_ADDR_OFFSET_BASE_IDX … // addressBlock: gc_gfx_cpwd_sdma0_sdmaperfsdec:1 // base address: 0x378b0 #define regSDMA1_PERFCNT_PERFCOUNTER0_CFG … #define regSDMA1_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX … #define regSDMA1_PERFCNT_PERFCOUNTER1_CFG … #define regSDMA1_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX … #define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL … #define regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define regSDMA1_PERFCNT_MISC_CNTL … #define regSDMA1_PERFCNT_MISC_CNTL_BASE_IDX … #define regSDMA1_PERFCOUNTER0_SELECT … #define regSDMA1_PERFCOUNTER0_SELECT_BASE_IDX … #define regSDMA1_PERFCOUNTER0_SELECT1 … #define regSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX … #define regSDMA1_PERFCOUNTER1_SELECT … #define regSDMA1_PERFCOUNTER1_SELECT_BASE_IDX … #define regSDMA1_PERFCOUNTER1_SELECT1 … #define regSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX … // addressBlock: gc_gfx_cpwd_sdma0_sdmaperfddec:1 // base address: 0x359b0 #define regSDMA1_PERFCNT_PERFCOUNTER_LO … #define regSDMA1_PERFCNT_PERFCOUNTER_LO_BASE_IDX … #define regSDMA1_PERFCNT_PERFCOUNTER_HI … #define regSDMA1_PERFCNT_PERFCOUNTER_HI_BASE_IDX … #define regSDMA1_PERFCOUNTER0_LO … #define regSDMA1_PERFCOUNTER0_LO_BASE_IDX … #define regSDMA1_PERFCOUNTER0_HI … #define regSDMA1_PERFCOUNTER0_HI_BASE_IDX … #define regSDMA1_PERFCOUNTER1_LO … #define regSDMA1_PERFCOUNTER1_LO_BASE_IDX … #define regSDMA1_PERFCOUNTER1_HI … #define regSDMA1_PERFCOUNTER1_HI_BASE_IDX … // addressBlock: gc_gfx_cpwd_sdma0_sdmapwrdec:1 // base address: 0x3c434 #define regGFX_ICG_SDMA1_CTRL … #define regGFX_ICG_SDMA1_CTRL_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_grbmdec // base address: 0x8000 #define regGRBM_CNTL … #define regGRBM_CNTL_BASE_IDX … #define regGRBM_SKEW_CNTL … #define regGRBM_SKEW_CNTL_BASE_IDX … #define regGRBM_STATUS2 … #define regGRBM_STATUS2_BASE_IDX … #define regGRBM_PWR_CNTL … #define regGRBM_PWR_CNTL_BASE_IDX … #define regGRBM_STATUS … #define regGRBM_STATUS_BASE_IDX … #define regGRBM_STATUS_SE0 … #define regGRBM_STATUS_SE0_BASE_IDX … #define regGRBM_STATUS_SE1 … #define regGRBM_STATUS_SE1_BASE_IDX … #define regGRBM_STATUS3 … #define regGRBM_STATUS3_BASE_IDX … #define regGRBM_SOFT_RESET … #define regGRBM_SOFT_RESET_BASE_IDX … #define regGRBM_GFX_CLKEN_CNTL … #define regGRBM_GFX_CLKEN_CNTL_BASE_IDX … #define regGRBM_WAIT_IDLE_CLOCKS … #define regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX … #define regGRBM_STATUS_SE2 … #define regGRBM_STATUS_SE2_BASE_IDX … #define regGRBM_STATUS_SE3 … #define regGRBM_STATUS_SE3_BASE_IDX … #define regGRBM_READ_ERROR … #define regGRBM_READ_ERROR_BASE_IDX … #define regGRBM_READ_ERROR2 … #define regGRBM_READ_ERROR2_BASE_IDX … #define regGRBM_INT_CNTL … #define regGRBM_INT_CNTL_BASE_IDX … #define regGRBM_TRAP_OP … #define regGRBM_TRAP_OP_BASE_IDX … #define regGRBM_TRAP_ADDR … #define regGRBM_TRAP_ADDR_BASE_IDX … #define regGRBM_TRAP_ADDR_MSK … #define regGRBM_TRAP_ADDR_MSK_BASE_IDX … #define regGRBM_TRAP_WD … #define regGRBM_TRAP_WD_BASE_IDX … #define regGRBM_TRAP_WD_MSK … #define regGRBM_TRAP_WD_MSK_BASE_IDX … #define regGRBM_DSM_BYPASS … #define regGRBM_DSM_BYPASS_BASE_IDX … #define regGRBM_WRITE_ERROR … #define regGRBM_WRITE_ERROR_BASE_IDX … #define regGRBM_CHIP_REVISION … #define regGRBM_CHIP_REVISION_BASE_IDX … #define regGRBM_IH_CREDIT … #define regGRBM_IH_CREDIT_BASE_IDX … #define regGRBM_PWR_CNTL2 … #define regGRBM_PWR_CNTL2_BASE_IDX … #define regGRBM_UTCL2_INVAL_RANGE_START … #define regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX … #define regGRBM_UTCL2_INVAL_RANGE_END … #define regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX … #define regGRBM_INVALID_PIPE … #define regGRBM_INVALID_PIPE_BASE_IDX … #define regGRBM_FENCE_RANGE0 … #define regGRBM_FENCE_RANGE0_BASE_IDX … #define regGRBM_FENCE_RANGE1 … #define regGRBM_FENCE_RANGE1_BASE_IDX … #define regGRBM_CHICKEN_BITS0 … #define regGRBM_CHICKEN_BITS0_BASE_IDX … #define regGRBM_CHICKEN_BITS1 … #define regGRBM_CHICKEN_BITS1_BASE_IDX … #define regCC_GC_FULL_SA_UNIT_DISABLE … #define regCC_GC_FULL_SA_UNIT_DISABLE_BASE_IDX … #define regGRBM_SCRATCH_REG0 … #define regGRBM_SCRATCH_REG0_BASE_IDX … #define regGRBM_SCRATCH_REG1 … #define regGRBM_SCRATCH_REG1_BASE_IDX … #define regGRBM_SCRATCH_REG2 … #define regGRBM_SCRATCH_REG2_BASE_IDX … #define regGRBM_SCRATCH_REG3 … #define regGRBM_SCRATCH_REG3_BASE_IDX … #define regGRBM_SCRATCH_REG4 … #define regGRBM_SCRATCH_REG4_BASE_IDX … #define regGRBM_SCRATCH_REG5 … #define regGRBM_SCRATCH_REG5_BASE_IDX … #define regGRBM_SCRATCH_REG6 … #define regGRBM_SCRATCH_REG6_BASE_IDX … #define regGRBM_SCRATCH_REG7 … #define regGRBM_SCRATCH_REG7_BASE_IDX … #define regGRBM_INTF_CNTL … #define regGRBM_INTF_CNTL_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_cpdec // base address: 0x8200 #define regCP_CPC_DEBUG_CNTL … #define regCP_CPC_DEBUG_CNTL_BASE_IDX … #define regCP_CPC_DEBUG_DATA … #define regCP_CPC_DEBUG_DATA_BASE_IDX … #define regCP_CPF_DEBUG_CNTL … #define regCP_CPF_DEBUG_CNTL_BASE_IDX … #define regCP_CPC_STATUS … #define regCP_CPC_STATUS_BASE_IDX … #define regCP_CPC_BUSY_STAT … #define regCP_CPC_BUSY_STAT_BASE_IDX … #define regCP_CPC_STALLED_STAT1 … #define regCP_CPC_STALLED_STAT1_BASE_IDX … #define regCP_CPF_STATUS … #define regCP_CPF_STATUS_BASE_IDX … #define regCP_CPF_BUSY_STAT … #define regCP_CPF_BUSY_STAT_BASE_IDX … #define regCP_CPF_STALLED_STAT1 … #define regCP_CPF_STALLED_STAT1_BASE_IDX … #define regCP_CPC_BUSY_STAT2 … #define regCP_CPC_BUSY_STAT2_BASE_IDX … #define regCP_CPC_GRBM_FREE_COUNT … #define regCP_CPC_GRBM_FREE_COUNT_BASE_IDX … #define regCP_CPC_PRIV_VIOLATION_ADDR … #define regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX … #define regCP_CPC_PRIV_VIOLATION_ADDR_HI … #define regCP_CPC_PRIV_VIOLATION_ADDR_HI_BASE_IDX … #define regCP_MEC_ME1_HEADER_DUMP … #define regCP_MEC_ME1_HEADER_DUMP_BASE_IDX … #define regCP_CPC_SCRATCH_INDEX … #define regCP_CPC_SCRATCH_INDEX_BASE_IDX … #define regCP_CPC_SCRATCH_DATA … #define regCP_CPC_SCRATCH_DATA_BASE_IDX … #define regCP_CPF_GRBM_FREE_COUNT … #define regCP_CPF_GRBM_FREE_COUNT_BASE_IDX … #define regCP_CPF_BUSY_STAT2 … #define regCP_CPF_BUSY_STAT2_BASE_IDX … #define regCP_CPC_HALT_HYST_COUNT … #define regCP_CPC_HALT_HYST_COUNT_BASE_IDX … #define regCP_STALLED_STAT3 … #define regCP_STALLED_STAT3_BASE_IDX … #define regCP_STALLED_STAT1 … #define regCP_STALLED_STAT1_BASE_IDX … #define regCP_STALLED_STAT2 … #define regCP_STALLED_STAT2_BASE_IDX … #define regCP_BUSY_STAT … #define regCP_BUSY_STAT_BASE_IDX … #define regCP_STAT … #define regCP_STAT_BASE_IDX … #define regCP_ME_HEADER_DUMP … #define regCP_ME_HEADER_DUMP_BASE_IDX … #define regCP_PFP_HEADER_DUMP … #define regCP_PFP_HEADER_DUMP_BASE_IDX … #define regCP_GRBM_FREE_COUNT … #define regCP_GRBM_FREE_COUNT_BASE_IDX … #define regCP_PFP_INSTR_PNTR … #define regCP_PFP_INSTR_PNTR_BASE_IDX … #define regCP_ME_INSTR_PNTR … #define regCP_ME_INSTR_PNTR_BASE_IDX … #define regCP_CSF_STAT … #define regCP_CSF_STAT_BASE_IDX … #define regCP_CNTX_STAT … #define regCP_CNTX_STAT_BASE_IDX … #define regCP_ME_PREEMPTION … #define regCP_ME_PREEMPTION_BASE_IDX … #define regCP_RB0_RPTR … #define regCP_RB0_RPTR_BASE_IDX … #define regCP_RB_RPTR … #define regCP_RB_RPTR_BASE_IDX … #define regCP_RB_WPTR_DELAY … #define regCP_RB_WPTR_DELAY_BASE_IDX … #define regCP_RB_WPTR_POLL_CNTL … #define regCP_RB_WPTR_POLL_CNTL_BASE_IDX … #define regCP_ROQ1_THRESHOLDS … #define regCP_ROQ1_THRESHOLDS_BASE_IDX … #define regCP_ROQ2_THRESHOLDS … #define regCP_ROQ2_THRESHOLDS_BASE_IDX … #define regCP_STQ_THRESHOLDS … #define regCP_STQ_THRESHOLDS_BASE_IDX … #define regCP_MEQ_THRESHOLDS … #define regCP_MEQ_THRESHOLDS_BASE_IDX … #define regCP_ROQ_AVAIL … #define regCP_ROQ_AVAIL_BASE_IDX … #define regCP_STQ_AVAIL … #define regCP_STQ_AVAIL_BASE_IDX … #define regCP_ROQ2_AVAIL … #define regCP_ROQ2_AVAIL_BASE_IDX … #define regCP_MEQ_AVAIL … #define regCP_MEQ_AVAIL_BASE_IDX … #define regCP_CMD_INDEX … #define regCP_CMD_INDEX_BASE_IDX … #define regCP_CMD_DATA … #define regCP_CMD_DATA_BASE_IDX … #define regCP_ROQ_RB_STAT … #define regCP_ROQ_RB_STAT_BASE_IDX … #define regCP_ROQ_IB1_STAT … #define regCP_ROQ_IB1_STAT_BASE_IDX … #define regCP_ROQ_IB2_STAT … #define regCP_ROQ_IB2_STAT_BASE_IDX … #define regCP_STQ_STAT … #define regCP_STQ_STAT_BASE_IDX … #define regCP_STQ_WR_STAT … #define regCP_STQ_WR_STAT_BASE_IDX … #define regCP_MEQ_STAT … #define regCP_MEQ_STAT_BASE_IDX … #define regCP_ROQ3_THRESHOLDS … #define regCP_ROQ3_THRESHOLDS_BASE_IDX … #define regCP_ROQ_DB_STAT … #define regCP_ROQ_DB_STAT_BASE_IDX … #define regCP_INT_STAT_DEBUG … #define regCP_INT_STAT_DEBUG_BASE_IDX … #define regCP_DEBUG_CNTL … #define regCP_DEBUG_CNTL_BASE_IDX … #define regCP_DEBUG_DATA … #define regCP_DEBUG_DATA_BASE_IDX … #define regCP_PRIV_VIOLATION_ADDR … #define regCP_PRIV_VIOLATION_ADDR_BASE_IDX … #define regCP_PRIV_VIOLATION_ADDR_HI … #define regCP_PRIV_VIOLATION_ADDR_HI_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_padec // base address: 0x8800 #define regVGT_DMA_DATA_FIFO_DEPTH … #define regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX … #define regVGT_DMA_REQ_FIFO_DEPTH … #define regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX … #define regVGT_DRAW_INIT_FIFO_DEPTH … #define regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX … #define regVGT_MC_LAT_CNTL … #define regVGT_MC_LAT_CNTL_BASE_IDX … #define regIA_UTCL1_STATUS_2 … #define regIA_UTCL1_STATUS_2_BASE_IDX … #define regGE_WD_CNTL_STATUS … #define regGE_WD_CNTL_STATUS_BASE_IDX … #define regWD_UTCL1_CNTL … #define regWD_UTCL1_CNTL_BASE_IDX … #define regWD_UTCL1_STATUS … #define regWD_UTCL1_STATUS_BASE_IDX … #define regIA_UTCL1_CNTL … #define regIA_UTCL1_CNTL_BASE_IDX … #define regIA_UTCL1_STATUS … #define regIA_UTCL1_STATUS_BASE_IDX … #define regGRBM_CC_GC_SA_UNIT_DISABLE … #define regGRBM_CC_GC_SA_UNIT_DISABLE_BASE_IDX … #define regGE_PRIV_CONTROL … #define regGE_PRIV_CONTROL_BASE_IDX … #define regGE_STATUS … #define regGE_STATUS_BASE_IDX … #define regVGT_GS_MAX_WAVE_ID … #define regVGT_GS_MAX_WAVE_ID_BASE_IDX … #define regGFX_PIPE_CONTROL … #define regGFX_PIPE_CONTROL_BASE_IDX … #define regVGT_RESET_DEBUG … #define regVGT_RESET_DEBUG_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_shdec // base address: 0xb000 #define regCOMPUTE_DISPATCH_INITIATOR … #define regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX … #define regCOMPUTE_DIM_X … #define regCOMPUTE_DIM_X_BASE_IDX … #define regCOMPUTE_DIM_Y … #define regCOMPUTE_DIM_Y_BASE_IDX … #define regCOMPUTE_DIM_Z … #define regCOMPUTE_DIM_Z_BASE_IDX … #define regCOMPUTE_START_X … #define regCOMPUTE_START_X_BASE_IDX … #define regCOMPUTE_START_Y … #define regCOMPUTE_START_Y_BASE_IDX … #define regCOMPUTE_START_Z … #define regCOMPUTE_START_Z_BASE_IDX … #define regCOMPUTE_NUM_THREAD_X … #define regCOMPUTE_NUM_THREAD_X_BASE_IDX … #define regCOMPUTE_NUM_THREAD_Y … #define regCOMPUTE_NUM_THREAD_Y_BASE_IDX … #define regCOMPUTE_NUM_THREAD_Z … #define regCOMPUTE_NUM_THREAD_Z_BASE_IDX … #define regCOMPUTE_PIPELINESTAT_ENABLE … #define regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX … #define regCOMPUTE_PERFCOUNT_ENABLE … #define regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX … #define regCOMPUTE_PGM_LO … #define regCOMPUTE_PGM_LO_BASE_IDX … #define regCOMPUTE_PGM_HI … #define regCOMPUTE_PGM_HI_BASE_IDX … #define regCOMPUTE_DISPATCH_PKT_ADDR_LO … #define regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX … #define regCOMPUTE_DISPATCH_PKT_ADDR_HI … #define regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX … #define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO … #define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX … #define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI … #define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX … #define regCOMPUTE_PGM_RSRC1 … #define regCOMPUTE_PGM_RSRC1_BASE_IDX … #define regCOMPUTE_PGM_RSRC2 … #define regCOMPUTE_PGM_RSRC2_BASE_IDX … #define regCOMPUTE_VMID … #define regCOMPUTE_VMID_BASE_IDX … #define regCOMPUTE_RESOURCE_LIMITS … #define regCOMPUTE_RESOURCE_LIMITS_BASE_IDX … #define regCOMPUTE_DESTINATION_EN_SE0 … #define regCOMPUTE_DESTINATION_EN_SE0_BASE_IDX … #define regCOMPUTE_STATIC_THREAD_MGMT_SE0 … #define regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX … #define regCOMPUTE_DESTINATION_EN_SE1 … #define regCOMPUTE_DESTINATION_EN_SE1_BASE_IDX … #define regCOMPUTE_STATIC_THREAD_MGMT_SE1 … #define regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX … #define regCOMPUTE_TMPRING_SIZE … #define regCOMPUTE_TMPRING_SIZE_BASE_IDX … #define regCOMPUTE_DESTINATION_EN_SE2 … #define regCOMPUTE_DESTINATION_EN_SE2_BASE_IDX … #define regCOMPUTE_STATIC_THREAD_MGMT_SE2 … #define regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX … #define regCOMPUTE_DESTINATION_EN_SE3 … #define regCOMPUTE_DESTINATION_EN_SE3_BASE_IDX … #define regCOMPUTE_STATIC_THREAD_MGMT_SE3 … #define regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX … #define regCOMPUTE_RESTART_X … #define regCOMPUTE_RESTART_X_BASE_IDX … #define regCOMPUTE_RESTART_Y … #define regCOMPUTE_RESTART_Y_BASE_IDX … #define regCOMPUTE_RESTART_Z … #define regCOMPUTE_RESTART_Z_BASE_IDX … #define regCOMPUTE_THREAD_TRACE_ENABLE … #define regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX … #define regCOMPUTE_MISC_RESERVED … #define regCOMPUTE_MISC_RESERVED_BASE_IDX … #define regCOMPUTE_DISPATCH_ID … #define regCOMPUTE_DISPATCH_ID_BASE_IDX … #define regCOMPUTE_THREADGROUP_ID … #define regCOMPUTE_THREADGROUP_ID_BASE_IDX … #define regCOMPUTE_REQ_CTRL … #define regCOMPUTE_REQ_CTRL_BASE_IDX … #define regCOMPUTE_STATIC_THREAD_MGMT_SE8 … #define regCOMPUTE_STATIC_THREAD_MGMT_SE8_BASE_IDX … #define regCOMPUTE_USER_ACCUM_0 … #define regCOMPUTE_USER_ACCUM_0_BASE_IDX … #define regCOMPUTE_USER_ACCUM_1 … #define regCOMPUTE_USER_ACCUM_1_BASE_IDX … #define regCOMPUTE_USER_ACCUM_2 … #define regCOMPUTE_USER_ACCUM_2_BASE_IDX … #define regCOMPUTE_USER_ACCUM_3 … #define regCOMPUTE_USER_ACCUM_3_BASE_IDX … #define regCOMPUTE_PGM_RSRC3 … #define regCOMPUTE_PGM_RSRC3_BASE_IDX … #define regCOMPUTE_DDID_INDEX … #define regCOMPUTE_DDID_INDEX_BASE_IDX … #define regCOMPUTE_SHADER_CHKSUM … #define regCOMPUTE_SHADER_CHKSUM_BASE_IDX … #define regCOMPUTE_STATIC_THREAD_MGMT_SE4 … #define regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX … #define regCOMPUTE_STATIC_THREAD_MGMT_SE5 … #define regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX … #define regCOMPUTE_STATIC_THREAD_MGMT_SE6 … #define regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX … #define regCOMPUTE_STATIC_THREAD_MGMT_SE7 … #define regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX … #define regCOMPUTE_DISPATCH_INTERLEAVE … #define regCOMPUTE_DISPATCH_INTERLEAVE_BASE_IDX … #define regCOMPUTE_RELAUNCH … #define regCOMPUTE_RELAUNCH_BASE_IDX … #define regCOMPUTE_WAVE_RESTORE_ADDR_LO … #define regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX … #define regCOMPUTE_WAVE_RESTORE_ADDR_HI … #define regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX … #define regCOMPUTE_RELAUNCH2 … #define regCOMPUTE_RELAUNCH2_BASE_IDX … #define regCOMPUTE_PRESCALED_DIM_X … #define regCOMPUTE_PRESCALED_DIM_X_BASE_IDX … #define regCOMPUTE_PRESCALED_DIM_Y … #define regCOMPUTE_PRESCALED_DIM_Y_BASE_IDX … #define regCOMPUTE_PRESCALED_DIM_Z … #define regCOMPUTE_PRESCALED_DIM_Z_BASE_IDX … #define regCOMPUTE_USER_DATA_0 … #define regCOMPUTE_USER_DATA_0_BASE_IDX … #define regCOMPUTE_USER_DATA_1 … #define regCOMPUTE_USER_DATA_1_BASE_IDX … #define regCOMPUTE_USER_DATA_2 … #define regCOMPUTE_USER_DATA_2_BASE_IDX … #define regCOMPUTE_USER_DATA_3 … #define regCOMPUTE_USER_DATA_3_BASE_IDX … #define regCOMPUTE_USER_DATA_4 … #define regCOMPUTE_USER_DATA_4_BASE_IDX … #define regCOMPUTE_USER_DATA_5 … #define regCOMPUTE_USER_DATA_5_BASE_IDX … #define regCOMPUTE_USER_DATA_6 … #define regCOMPUTE_USER_DATA_6_BASE_IDX … #define regCOMPUTE_USER_DATA_7 … #define regCOMPUTE_USER_DATA_7_BASE_IDX … #define regCOMPUTE_USER_DATA_8 … #define regCOMPUTE_USER_DATA_8_BASE_IDX … #define regCOMPUTE_USER_DATA_9 … #define regCOMPUTE_USER_DATA_9_BASE_IDX … #define regCOMPUTE_USER_DATA_10 … #define regCOMPUTE_USER_DATA_10_BASE_IDX … #define regCOMPUTE_USER_DATA_11 … #define regCOMPUTE_USER_DATA_11_BASE_IDX … #define regCOMPUTE_USER_DATA_12 … #define regCOMPUTE_USER_DATA_12_BASE_IDX … #define regCOMPUTE_USER_DATA_13 … #define regCOMPUTE_USER_DATA_13_BASE_IDX … #define regCOMPUTE_USER_DATA_14 … #define regCOMPUTE_USER_DATA_14_BASE_IDX … #define regCOMPUTE_USER_DATA_15 … #define regCOMPUTE_USER_DATA_15_BASE_IDX … #define regCOMPUTE_DISPATCH_TUNNEL … #define regCOMPUTE_DISPATCH_TUNNEL_BASE_IDX … #define regCOMPUTE_DISPATCH_END … #define regCOMPUTE_DISPATCH_END_BASE_IDX … #define regCOMPUTE_NOWHERE … #define regCOMPUTE_NOWHERE_BASE_IDX … #define regSH_RESERVED_REG0 … #define regSH_RESERVED_REG0_BASE_IDX … #define regSH_RESERVED_REG1 … #define regSH_RESERVED_REG1_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_rasdec // base address: 0xce00 #define regRAS_GE_SIGNATURE0 … #define regRAS_GE_SIGNATURE0_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_pfonly_gccacdec // base address: 0x2eb40 #define regGC_CAC_CTRL_1 … #define regGC_CAC_CTRL_1_BASE_IDX … #define regGC_CAC_CTRL_2 … #define regGC_CAC_CTRL_2_BASE_IDX … #define regGC_CAC_AGGR_LOWER … #define regGC_CAC_AGGR_LOWER_BASE_IDX … #define regGC_CAC_AGGR_UPPER … #define regGC_CAC_AGGR_UPPER_BASE_IDX … #define regSE0_CAC_AGGR_LOWER … #define regSE0_CAC_AGGR_LOWER_BASE_IDX … #define regSE0_CAC_AGGR_UPPER … #define regSE0_CAC_AGGR_UPPER_BASE_IDX … #define regSE1_CAC_AGGR_LOWER … #define regSE1_CAC_AGGR_LOWER_BASE_IDX … #define regSE1_CAC_AGGR_UPPER … #define regSE1_CAC_AGGR_UPPER_BASE_IDX … #define regSE2_CAC_AGGR_LOWER … #define regSE2_CAC_AGGR_LOWER_BASE_IDX … #define regSE2_CAC_AGGR_UPPER … #define regSE2_CAC_AGGR_UPPER_BASE_IDX … #define regSE3_CAC_AGGR_LOWER … #define regSE3_CAC_AGGR_LOWER_BASE_IDX … #define regSE3_CAC_AGGR_UPPER … #define regSE3_CAC_AGGR_UPPER_BASE_IDX … #define regGC_CAC_AGGR_GFXCLK_CYCLE … #define regGC_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX … #define regSE0_CAC_AGGR_GFXCLK_CYCLE … #define regSE0_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX … #define regSE1_CAC_AGGR_GFXCLK_CYCLE … #define regSE1_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX … #define regSE2_CAC_AGGR_GFXCLK_CYCLE … #define regSE2_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX … #define regSE3_CAC_AGGR_GFXCLK_CYCLE … #define regSE3_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX … #define regGC_EDC_CTRL … #define regGC_EDC_CTRL_BASE_IDX … #define regGC_EDC_STRETCH_CTRL … #define regGC_EDC_STRETCH_CTRL_BASE_IDX … #define regGC_EDC_THRESHOLD_LO … #define regGC_EDC_THRESHOLD_LO_BASE_IDX … #define regGC_EDC_THRESHOLD_HI … #define regGC_EDC_THRESHOLD_HI_BASE_IDX … #define regGC_EDC_STRETCH_THRESHOLD_LO … #define regGC_EDC_STRETCH_THRESHOLD_LO_BASE_IDX … #define regGC_EDC_STRETCH_THRESHOLD_HI … #define regGC_EDC_STRETCH_THRESHOLD_HI_BASE_IDX … #define regEDC_HYSTERESIS_CNTL … #define regEDC_HYSTERESIS_CNTL_BASE_IDX … #define regGC_THROTTLE_CTRL … #define regGC_THROTTLE_CTRL_BASE_IDX … #define regGC_THROTTLE_CTRL1 … #define regGC_THROTTLE_CTRL1_BASE_IDX … #define regGC_THROTTLE_CTRL2 … #define regGC_THROTTLE_CTRL2_BASE_IDX … #define regEDC_STALL_PATTERN_CTRL … #define regEDC_STALL_PATTERN_CTRL_BASE_IDX … #define regPCC_STALL_PATTERN_CTRL … #define regPCC_STALL_PATTERN_CTRL_BASE_IDX … #define regPWRBRK_STALL_PATTERN_CTRL … #define regPWRBRK_STALL_PATTERN_CTRL_BASE_IDX … #define regEDC_STALL_PATTERN_1_2 … #define regEDC_STALL_PATTERN_1_2_BASE_IDX … #define regEDC_STALL_PATTERN_3_4 … #define regEDC_STALL_PATTERN_3_4_BASE_IDX … #define regEDC_STALL_PATTERN_5_6 … #define regEDC_STALL_PATTERN_5_6_BASE_IDX … #define regEDC_STALL_PATTERN_7 … #define regEDC_STALL_PATTERN_7_BASE_IDX … #define regPCC_STALL_PATTERN_1_2 … #define regPCC_STALL_PATTERN_1_2_BASE_IDX … #define regPCC_STALL_PATTERN_3_4 … #define regPCC_STALL_PATTERN_3_4_BASE_IDX … #define regPCC_STALL_PATTERN_5_6 … #define regPCC_STALL_PATTERN_5_6_BASE_IDX … #define regPCC_STALL_PATTERN_7 … #define regPCC_STALL_PATTERN_7_BASE_IDX … #define regPWRBRK_STALL_PATTERN_1_2 … #define regPWRBRK_STALL_PATTERN_1_2_BASE_IDX … #define regPWRBRK_STALL_PATTERN_3_4 … #define regPWRBRK_STALL_PATTERN_3_4_BASE_IDX … #define regPWRBRK_STALL_PATTERN_5_6 … #define regPWRBRK_STALL_PATTERN_5_6_BASE_IDX … #define regPWRBRK_STALL_PATTERN_7 … #define regPWRBRK_STALL_PATTERN_7_BASE_IDX … #define regDIDT_STALL_PATTERN_CTRL … #define regDIDT_STALL_PATTERN_CTRL_BASE_IDX … #define regDIDT_STALL_PATTERN_1_2 … #define regDIDT_STALL_PATTERN_1_2_BASE_IDX … #define regDIDT_STALL_PATTERN_3_4 … #define regDIDT_STALL_PATTERN_3_4_BASE_IDX … #define regDIDT_STALL_PATTERN_5_6 … #define regDIDT_STALL_PATTERN_5_6_BASE_IDX … #define regDIDT_STALL_PATTERN_7 … #define regDIDT_STALL_PATTERN_7_BASE_IDX … #define regPCC_PWRBRK_HYSTERESIS_CTRL … #define regPCC_PWRBRK_HYSTERESIS_CTRL_BASE_IDX … #define regEDC_STRETCH_PERF_COUNTER … #define regEDC_STRETCH_PERF_COUNTER_BASE_IDX … #define regEDC_UNSTRETCH_PERF_COUNTER … #define regEDC_UNSTRETCH_PERF_COUNTER_BASE_IDX … #define regEDC_STRETCH_NUM_PERF_COUNTER … #define regEDC_STRETCH_NUM_PERF_COUNTER_BASE_IDX … #define regGC_EDC_STATUS … #define regGC_EDC_STATUS_BASE_IDX … #define regGC_EDC_OVERFLOW … #define regGC_EDC_OVERFLOW_BASE_IDX … #define regGC_EDC_ROLLING_POWER_DELTA_LO … #define regGC_EDC_ROLLING_POWER_DELTA_LO_BASE_IDX … #define regGC_EDC_ROLLING_POWER_DELTA_HI … #define regGC_EDC_ROLLING_POWER_DELTA_HI_BASE_IDX … #define regGC_THROTTLE_STATUS … #define regGC_THROTTLE_STATUS_BASE_IDX … #define regEDC_PERF_COUNTER … #define regEDC_PERF_COUNTER_BASE_IDX … #define regPCC_PERF_COUNTER … #define regPCC_PERF_COUNTER_BASE_IDX … #define regPWRBRK_PERF_COUNTER … #define regPWRBRK_PERF_COUNTER_BASE_IDX … #define regEDC_HYSTERESIS_STAT … #define regEDC_HYSTERESIS_STAT_BASE_IDX … #define regDIDT_HYSTERESIS_STAT … #define regDIDT_HYSTERESIS_STAT_BASE_IDX … #define regDIDT_PERF_COUNTER … #define regDIDT_PERF_COUNTER_BASE_IDX … #define regGC_EDC_CLK_MONITOR_CTRL … #define regGC_EDC_CLK_MONITOR_CTRL_BASE_IDX … #define regGC_CAC_SOFT_CTRL … #define regGC_CAC_SOFT_CTRL_BASE_IDX … #define regGC_CAC_WEIGHT_CP_0 … #define regGC_CAC_WEIGHT_CP_0_BASE_IDX … #define regGC_CAC_WEIGHT_CP_1 … #define regGC_CAC_WEIGHT_CP_1_BASE_IDX … #define regGC_CAC_WEIGHT_EA_0 … #define regGC_CAC_WEIGHT_EA_0_BASE_IDX … #define regGC_CAC_WEIGHT_EA_1 … #define regGC_CAC_WEIGHT_EA_1_BASE_IDX … #define regGC_CAC_WEIGHT_EA_2 … #define regGC_CAC_WEIGHT_EA_2_BASE_IDX … #define regGC_CAC_WEIGHT_UTCL2_ROUTER_0 … #define regGC_CAC_WEIGHT_UTCL2_ROUTER_0_BASE_IDX … #define regGC_CAC_WEIGHT_UTCL2_ROUTER_1 … #define regGC_CAC_WEIGHT_UTCL2_ROUTER_1_BASE_IDX … #define regGC_CAC_WEIGHT_UTCL2_ROUTER_2 … #define regGC_CAC_WEIGHT_UTCL2_ROUTER_2_BASE_IDX … #define regGC_CAC_WEIGHT_UTCL2_ROUTER_3 … #define regGC_CAC_WEIGHT_UTCL2_ROUTER_3_BASE_IDX … #define regGC_CAC_WEIGHT_UTCL2_ROUTER_4 … #define regGC_CAC_WEIGHT_UTCL2_ROUTER_4_BASE_IDX … #define regGC_CAC_WEIGHT_UTCL2_VML2_0 … #define regGC_CAC_WEIGHT_UTCL2_VML2_0_BASE_IDX … #define regGC_CAC_WEIGHT_UTCL2_VML2_1 … #define regGC_CAC_WEIGHT_UTCL2_VML2_1_BASE_IDX … #define regGC_CAC_WEIGHT_UTCL2_VML2_2 … #define regGC_CAC_WEIGHT_UTCL2_VML2_2_BASE_IDX … #define regGC_CAC_WEIGHT_UTCL2_WALKER_0 … #define regGC_CAC_WEIGHT_UTCL2_WALKER_0_BASE_IDX … #define regGC_CAC_WEIGHT_UTCL2_WALKER_1 … #define regGC_CAC_WEIGHT_UTCL2_WALKER_1_BASE_IDX … #define regGC_CAC_WEIGHT_UTCL2_WALKER_2 … #define regGC_CAC_WEIGHT_UTCL2_WALKER_2_BASE_IDX … #define regGC_CAC_WEIGHT_GE_0 … #define regGC_CAC_WEIGHT_GE_0_BASE_IDX … #define regGC_CAC_WEIGHT_GE_1 … #define regGC_CAC_WEIGHT_GE_1_BASE_IDX … #define regGC_CAC_WEIGHT_PMM_0 … #define regGC_CAC_WEIGHT_PMM_0_BASE_IDX … #define regGC_CAC_WEIGHT_SDMA_0 … #define regGC_CAC_WEIGHT_SDMA_0_BASE_IDX … #define regGC_CAC_WEIGHT_SDMA_1 … #define regGC_CAC_WEIGHT_SDMA_1_BASE_IDX … #define regGC_CAC_WEIGHT_SDMA_2 … #define regGC_CAC_WEIGHT_SDMA_2_BASE_IDX … #define regGC_CAC_WEIGHT_SDMA_3 … #define regGC_CAC_WEIGHT_SDMA_3_BASE_IDX … #define regGC_CAC_WEIGHT_SDMA_4 … #define regGC_CAC_WEIGHT_SDMA_4_BASE_IDX … #define regGC_CAC_WEIGHT_SDMA_5 … #define regGC_CAC_WEIGHT_SDMA_5_BASE_IDX … #define regGC_CAC_WEIGHT_CHC_0 … #define regGC_CAC_WEIGHT_CHC_0_BASE_IDX … #define regGC_CAC_WEIGHT_CHC_1 … #define regGC_CAC_WEIGHT_CHC_1_BASE_IDX … #define regGC_CAC_WEIGHT_RLC_0 … #define regGC_CAC_WEIGHT_RLC_0_BASE_IDX … #define regGC_CAC_WEIGHT_GRBM_0 … #define regGC_CAC_WEIGHT_GRBM_0_BASE_IDX … #define regGC_CAC_WEIGHT_GL2C_0 … #define regGC_CAC_WEIGHT_GL2C_0_BASE_IDX … #define regGC_CAC_WEIGHT_GL2C_1 … #define regGC_CAC_WEIGHT_GL2C_1_BASE_IDX … #define regGC_CAC_WEIGHT_GL2C_2 … #define regGC_CAC_WEIGHT_GL2C_2_BASE_IDX … #define regGC_CAC_IND_INDEX … #define regGC_CAC_IND_INDEX_BASE_IDX … #define regGC_CAC_IND_DATA … #define regGC_CAC_IND_DATA_BASE_IDX … // addressBlock: gc_gfx_cpwd_gc_ea_cpwd_gceadec // base address: 0xa800 #define regGC_EA_CPWD_VC_MAP … #define regGC_EA_CPWD_VC_MAP_BASE_IDX … #define regGC_EA_CPWD_SDP_ARB_FINAL … #define regGC_EA_CPWD_SDP_ARB_FINAL_BASE_IDX … #define regGC_EA_CPWD_SDP_PRIORITY … #define regGC_EA_CPWD_SDP_PRIORITY_BASE_IDX … #define regGC_EA_CPWD_SDP_CREDITS … #define regGC_EA_CPWD_SDP_CREDITS_BASE_IDX … #define regGC_EA_CPWD_SDP_TAG_RESERVE0 … #define regGC_EA_CPWD_SDP_TAG_RESERVE0_BASE_IDX … #define regGC_EA_CPWD_SDP_TAG_RESERVE1 … #define regGC_EA_CPWD_SDP_TAG_RESERVE1_BASE_IDX … #define regGC_EA_CPWD_SDP_TAG_RESERVE2 … #define regGC_EA_CPWD_SDP_TAG_RESERVE2_BASE_IDX … #define regGC_EA_CPWD_SDP_VCC_RESERVE0 … #define regGC_EA_CPWD_SDP_VCC_RESERVE0_BASE_IDX … #define regGC_EA_CPWD_SDP_VCC_RESERVE1 … #define regGC_EA_CPWD_SDP_VCC_RESERVE1_BASE_IDX … #define regGC_EA_CPWD_SDP_VCD_RESERVE0 … #define regGC_EA_CPWD_SDP_VCD_RESERVE0_BASE_IDX … #define regGC_EA_CPWD_SDP_VCD_RESERVE1 … #define regGC_EA_CPWD_SDP_VCD_RESERVE1_BASE_IDX … #define regGC_EA_CPWD_SDP_REQ_CNTL … #define regGC_EA_CPWD_SDP_REQ_CNTL_BASE_IDX … #define regGC_EA_CPWD_MISC … #define regGC_EA_CPWD_MISC_BASE_IDX … #define regGC_EA_CPWD_ERR_STATUS … #define regGC_EA_CPWD_ERR_STATUS_BASE_IDX … #define regGC_EA_CPWD_MISC2 … #define regGC_EA_CPWD_MISC2_BASE_IDX … #define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0 … #define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_BASE_IDX … #define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE … #define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE_BASE_IDX … #define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1 … #define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_BASE_IDX … #define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE … #define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE_BASE_IDX … #define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0 … #define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_BASE_IDX … #define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE … #define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE_BASE_IDX … #define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1 … #define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_BASE_IDX … #define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE … #define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE_BASE_IDX … #define regGC_EA_CPWD_SDP_BACKDOOR_MISCCTL … #define regGC_EA_CPWD_SDP_BACKDOOR_MISCCTL_BASE_IDX … #define regGC_EA_CPWD_SDP_BACKDOOR_MISCCTL_WRITE … #define regGC_EA_CPWD_SDP_BACKDOOR_MISCCTL_WRITE_BASE_IDX … #define regGC_EA_CPWD_SDP_ENABLE … #define regGC_EA_CPWD_SDP_ENABLE_BASE_IDX … // addressBlock: gc_gfx_cpwd_gc_ea_se_gceadec // base address: 0xaa00 #define regGC_EA_SE_SDP_ARB_FINAL … #define regGC_EA_SE_SDP_ARB_FINAL_BASE_IDX … #define regGC_EA_SE_SDP_PRIORITY … #define regGC_EA_SE_SDP_PRIORITY_BASE_IDX … #define regGC_EA_SE_SDP_CREDITS … #define regGC_EA_SE_SDP_CREDITS_BASE_IDX … #define regGC_EA_SE_SDP_TAG_RESERVE0 … #define regGC_EA_SE_SDP_TAG_RESERVE0_BASE_IDX … #define regGC_EA_SE_SDP_TAG_RESERVE1 … #define regGC_EA_SE_SDP_TAG_RESERVE1_BASE_IDX … #define regGC_EA_SE_SDP_TAG_RESERVE2 … #define regGC_EA_SE_SDP_TAG_RESERVE2_BASE_IDX … #define regGC_EA_SE_SDP_VCC_RESERVE0 … #define regGC_EA_SE_SDP_VCC_RESERVE0_BASE_IDX … #define regGC_EA_SE_SDP_VCC_RESERVE1 … #define regGC_EA_SE_SDP_VCC_RESERVE1_BASE_IDX … #define regGC_EA_SE_SDP_VCD_RESERVE0 … #define regGC_EA_SE_SDP_VCD_RESERVE0_BASE_IDX … #define regGC_EA_SE_SDP_VCD_RESERVE1 … #define regGC_EA_SE_SDP_VCD_RESERVE1_BASE_IDX … #define regGC_EA_SE_SDP_REQ_CNTL … #define regGC_EA_SE_SDP_REQ_CNTL_BASE_IDX … #define regGC_EA_SE_MISC … #define regGC_EA_SE_MISC_BASE_IDX … #define regGC_EA_SE_MISC2 … #define regGC_EA_SE_MISC2_BASE_IDX … #define regGC_EA_SE_SDP_ENABLE … #define regGC_EA_SE_SDP_ENABLE_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_gcrdec // base address: 0x9f80 #define regGCR_PIO_CNTL … #define regGCR_PIO_CNTL_BASE_IDX … #define regGCR_PIO_DATA … #define regGCR_PIO_DATA_BASE_IDX … #define regPMM_CNTL … #define regPMM_CNTL_BASE_IDX … #define regPMM_STATUS … #define regPMM_STATUS_BASE_IDX … // addressBlock: gc_gfx_cpwd_gcutcl2_gcvmsharedpfdec // base address: 0xa000 #define regGCMC_VM_NB_MMIOBASE … #define regGCMC_VM_NB_MMIOBASE_BASE_IDX … #define regGCMC_VM_NB_MMIOLIMIT … #define regGCMC_VM_NB_MMIOLIMIT_BASE_IDX … #define regGCMC_VM_NB_PCI_CTRL … #define regGCMC_VM_NB_PCI_CTRL_BASE_IDX … #define regGCMC_VM_NB_PCI_ARB … #define regGCMC_VM_NB_PCI_ARB_BASE_IDX … #define regGCMC_VM_NB_TOP_OF_DRAM_SLOT1 … #define regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX … #define regGCMC_VM_NB_LOWER_TOP_OF_DRAM2 … #define regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX … #define regGCMC_VM_NB_UPPER_TOP_OF_DRAM2 … #define regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX … #define regGCMC_VM_FB_OFFSET … #define regGCMC_VM_FB_OFFSET_BASE_IDX … #define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB … #define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX … #define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB … #define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX … #define regGCMC_VM_STEERING … #define regGCMC_VM_STEERING_BASE_IDX … #define regGCMC_SHARED_VIRT_RESET_REQ … #define regGCMC_SHARED_VIRT_RESET_REQ_BASE_IDX … #define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START … #define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX … #define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END … #define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX … #define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START … #define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX … #define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END … #define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX … #define regGCMC_VM_APT_CNTL … #define regGCMC_VM_APT_CNTL_BASE_IDX … #define regGCMC_VM_LOCAL_FB_ADDRESS_START … #define regGCMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX … #define regGCMC_VM_LOCAL_FB_ADDRESS_END … #define regGCMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX … #define regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL … #define regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX … #define regGCUTCL2_ICG_CTRL … #define regGCUTCL2_ICG_CTRL_BASE_IDX … #define regGCMC_SHARED_ACTIVE_FCN_ID … #define regGCMC_SHARED_ACTIVE_FCN_ID_BASE_IDX … #define regGCUTCL2_CGTT_BUSY_CTRL … #define regGCUTCL2_CGTT_BUSY_CTRL_BASE_IDX … #define regGCUTCL2_HARVEST_BYPASS_GROUPS … #define regGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX … #define regGCUTCL2_GROUP_RET_FAULT_STATUS … #define regGCUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX … // addressBlock: gc_gfx_cpwd_gcutcl2_gcvml2pfdec // base address: 0xa090 #define regGCVM_L2_CNTL … #define regGCVM_L2_CNTL_BASE_IDX … #define regGCVM_L2_CNTL2 … #define regGCVM_L2_CNTL2_BASE_IDX … #define regGCVM_L2_CNTL3 … #define regGCVM_L2_CNTL3_BASE_IDX … #define regGCVM_L2_STATUS … #define regGCVM_L2_STATUS_BASE_IDX … #define regGCVM_DUMMY_PAGE_FAULT_CNTL … #define regGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX … #define regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32 … #define regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX … #define regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32 … #define regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX … #define regGCVM_INVALIDATE_CNTL … #define regGCVM_INVALIDATE_CNTL_BASE_IDX … #define regGCVM_L2_PROTECTION_FAULT_CNTL … #define regGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX … #define regGCVM_L2_PROTECTION_FAULT_CNTL2 … #define regGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX … #define regGCVM_L2_PROTECTION_FAULT_MM_CNTL3 … #define regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX … #define regGCVM_L2_PROTECTION_FAULT_MM_CNTL4 … #define regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX … #define regGCVM_L2_PROTECTION_FAULT_STATUS_LO32 … #define regGCVM_L2_PROTECTION_FAULT_STATUS_LO32_BASE_IDX … #define regGCVM_L2_PROTECTION_FAULT_STATUS_HI32 … #define regGCVM_L2_PROTECTION_FAULT_STATUS_HI32_BASE_IDX … #define regGCVM_L2_PROTECTION_FAULT_ADDR_LO32 … #define regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX … #define regGCVM_L2_PROTECTION_FAULT_ADDR_HI32 … #define regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX … #define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 … #define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX … #define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 … #define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX … #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 … #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX … #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 … #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX … #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 … #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX … #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 … #define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX … #define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 … #define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX … #define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 … #define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX … #define regGCVM_L2_CNTL4 … #define regGCVM_L2_CNTL4_BASE_IDX … #define regGCVM_L2_MM_GROUP_RT_CLASSES … #define regGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX … #define regGCVM_L2_BANK_SELECT_RESERVED_CID … #define regGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX … #define regGCVM_L2_BANK_SELECT_RESERVED_CID2 … #define regGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX … #define regGCVM_L2_CACHE_PARITY_CNTL … #define regGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX … #define regGCVM_L2_ICG_CTRL … #define regGCVM_L2_ICG_CTRL_BASE_IDX … #define regGCVM_L2_CNTL5 … #define regGCVM_L2_CNTL5_BASE_IDX … #define regGCVM_L2_GCR_CNTL … #define regGCVM_L2_GCR_CNTL_BASE_IDX … #define regGCVML2_WALKER_MACRO_THROTTLE_TIME … #define regGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX … #define regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT … #define regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX … #define regGCVML2_WALKER_MICRO_THROTTLE_TIME … #define regGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX … #define regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT … #define regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX … #define regGCVM_L2_CGTT_BUSY_CTRL … #define regGCVM_L2_CGTT_BUSY_CTRL_BASE_IDX … #define regGCVM_L2_PTE_CACHE_DUMP_CNTL … #define regGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX … #define regGCVM_L2_PTE_CACHE_DUMP_READ … #define regGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX … #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_LO32 … #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_LO32_BASE_IDX … #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_HI32 … #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_HI32_BASE_IDX … #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR … #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR_BASE_IDX … #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_LO32 … #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_LO32_BASE_IDX … #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_HI32 … #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_HI32_BASE_IDX … #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR … #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR_BASE_IDX … #define regGCVM_L2_BANK_SELECT_MASKS … #define regGCVM_L2_BANK_SELECT_MASKS_BASE_IDX … #define regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC … #define regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX … #define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC … #define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX … #define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC … #define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX … #define regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT … #define regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX … #define regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ … #define regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX … // addressBlock: gc_gfx_cpwd_gcutcl2_gcvmsharedvcdec // base address: 0xa1d0 #define regGCMC_VM_FB_LOCATION_BASE … #define regGCMC_VM_FB_LOCATION_BASE_BASE_IDX … #define regGCMC_VM_FB_LOCATION_TOP … #define regGCMC_VM_FB_LOCATION_TOP_BASE_IDX … #define regGCMC_VM_AGP_TOP … #define regGCMC_VM_AGP_TOP_BASE_IDX … #define regGCMC_VM_AGP_BOT … #define regGCMC_VM_AGP_BOT_BASE_IDX … #define regGCMC_VM_AGP_BASE … #define regGCMC_VM_AGP_BASE_BASE_IDX … #define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR … #define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX … #define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR … #define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX … #define regGCMC_VM_MX_L1_TLB_CNTL … #define regGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX … // addressBlock: gc_gfx_cpwd_gcutcl2_gcvml2vcdec // base address: 0xa210 #define regGCVM_CONTEXT0_CNTL … #define regGCVM_CONTEXT0_CNTL_BASE_IDX … #define regGCVM_CONTEXT1_CNTL … #define regGCVM_CONTEXT1_CNTL_BASE_IDX … #define regGCVM_CONTEXT2_CNTL … #define regGCVM_CONTEXT2_CNTL_BASE_IDX … #define regGCVM_CONTEXT3_CNTL … #define regGCVM_CONTEXT3_CNTL_BASE_IDX … #define regGCVM_CONTEXT4_CNTL … #define regGCVM_CONTEXT4_CNTL_BASE_IDX … #define regGCVM_CONTEXT5_CNTL … #define regGCVM_CONTEXT5_CNTL_BASE_IDX … #define regGCVM_CONTEXT6_CNTL … #define regGCVM_CONTEXT6_CNTL_BASE_IDX … #define regGCVM_CONTEXT7_CNTL … #define regGCVM_CONTEXT7_CNTL_BASE_IDX … #define regGCVM_CONTEXT8_CNTL … #define regGCVM_CONTEXT8_CNTL_BASE_IDX … #define regGCVM_CONTEXT9_CNTL … #define regGCVM_CONTEXT9_CNTL_BASE_IDX … #define regGCVM_CONTEXT10_CNTL … #define regGCVM_CONTEXT10_CNTL_BASE_IDX … #define regGCVM_CONTEXT11_CNTL … #define regGCVM_CONTEXT11_CNTL_BASE_IDX … #define regGCVM_CONTEXT12_CNTL … #define regGCVM_CONTEXT12_CNTL_BASE_IDX … #define regGCVM_CONTEXT13_CNTL … #define regGCVM_CONTEXT13_CNTL_BASE_IDX … #define regGCVM_CONTEXT14_CNTL … #define regGCVM_CONTEXT14_CNTL_BASE_IDX … #define regGCVM_CONTEXT15_CNTL … #define regGCVM_CONTEXT15_CNTL_BASE_IDX … #define regGCVM_CONTEXTS_DISABLE … #define regGCVM_CONTEXTS_DISABLE_BASE_IDX … #define regGCVM_INVALIDATE_ENG0_SEM … #define regGCVM_INVALIDATE_ENG0_SEM_BASE_IDX … #define regGCVM_INVALIDATE_ENG1_SEM … #define regGCVM_INVALIDATE_ENG1_SEM_BASE_IDX … #define regGCVM_INVALIDATE_ENG2_SEM … #define regGCVM_INVALIDATE_ENG2_SEM_BASE_IDX … #define regGCVM_INVALIDATE_ENG3_SEM … #define regGCVM_INVALIDATE_ENG3_SEM_BASE_IDX … #define regGCVM_INVALIDATE_ENG4_SEM … #define regGCVM_INVALIDATE_ENG4_SEM_BASE_IDX … #define regGCVM_INVALIDATE_ENG5_SEM … #define regGCVM_INVALIDATE_ENG5_SEM_BASE_IDX … #define regGCVM_INVALIDATE_ENG6_SEM … #define regGCVM_INVALIDATE_ENG6_SEM_BASE_IDX … #define regGCVM_INVALIDATE_ENG7_SEM … #define regGCVM_INVALIDATE_ENG7_SEM_BASE_IDX … #define regGCVM_INVALIDATE_ENG8_SEM … #define regGCVM_INVALIDATE_ENG8_SEM_BASE_IDX … #define regGCVM_INVALIDATE_ENG9_SEM … #define regGCVM_INVALIDATE_ENG9_SEM_BASE_IDX … #define regGCVM_INVALIDATE_ENG10_SEM … #define regGCVM_INVALIDATE_ENG10_SEM_BASE_IDX … #define regGCVM_INVALIDATE_ENG11_SEM … #define regGCVM_INVALIDATE_ENG11_SEM_BASE_IDX … #define regGCVM_INVALIDATE_ENG12_SEM … #define regGCVM_INVALIDATE_ENG12_SEM_BASE_IDX … #define regGCVM_INVALIDATE_ENG13_SEM … #define regGCVM_INVALIDATE_ENG13_SEM_BASE_IDX … #define regGCVM_INVALIDATE_ENG14_SEM … #define regGCVM_INVALIDATE_ENG14_SEM_BASE_IDX … #define regGCVM_INVALIDATE_ENG15_SEM … #define regGCVM_INVALIDATE_ENG15_SEM_BASE_IDX … #define regGCVM_INVALIDATE_ENG16_SEM … #define regGCVM_INVALIDATE_ENG16_SEM_BASE_IDX … #define regGCVM_INVALIDATE_ENG17_SEM … #define regGCVM_INVALIDATE_ENG17_SEM_BASE_IDX … #define regGCVM_INVALIDATE_ENG0_REQ … #define regGCVM_INVALIDATE_ENG0_REQ_BASE_IDX … #define regGCVM_INVALIDATE_ENG1_REQ … #define regGCVM_INVALIDATE_ENG1_REQ_BASE_IDX … #define regGCVM_INVALIDATE_ENG2_REQ … #define regGCVM_INVALIDATE_ENG2_REQ_BASE_IDX … #define regGCVM_INVALIDATE_ENG3_REQ … #define regGCVM_INVALIDATE_ENG3_REQ_BASE_IDX … #define regGCVM_INVALIDATE_ENG4_REQ … #define regGCVM_INVALIDATE_ENG4_REQ_BASE_IDX … #define regGCVM_INVALIDATE_ENG5_REQ … #define regGCVM_INVALIDATE_ENG5_REQ_BASE_IDX … #define regGCVM_INVALIDATE_ENG6_REQ … #define regGCVM_INVALIDATE_ENG6_REQ_BASE_IDX … #define regGCVM_INVALIDATE_ENG7_REQ … #define regGCVM_INVALIDATE_ENG7_REQ_BASE_IDX … #define regGCVM_INVALIDATE_ENG8_REQ … #define regGCVM_INVALIDATE_ENG8_REQ_BASE_IDX … #define regGCVM_INVALIDATE_ENG9_REQ … #define regGCVM_INVALIDATE_ENG9_REQ_BASE_IDX … #define regGCVM_INVALIDATE_ENG10_REQ … #define regGCVM_INVALIDATE_ENG10_REQ_BASE_IDX … #define regGCVM_INVALIDATE_ENG11_REQ … #define regGCVM_INVALIDATE_ENG11_REQ_BASE_IDX … #define regGCVM_INVALIDATE_ENG12_REQ … #define regGCVM_INVALIDATE_ENG12_REQ_BASE_IDX … #define regGCVM_INVALIDATE_ENG13_REQ … #define regGCVM_INVALIDATE_ENG13_REQ_BASE_IDX … #define regGCVM_INVALIDATE_ENG14_REQ … #define regGCVM_INVALIDATE_ENG14_REQ_BASE_IDX … #define regGCVM_INVALIDATE_ENG15_REQ … #define regGCVM_INVALIDATE_ENG15_REQ_BASE_IDX … #define regGCVM_INVALIDATE_ENG16_REQ … #define regGCVM_INVALIDATE_ENG16_REQ_BASE_IDX … #define regGCVM_INVALIDATE_ENG17_REQ … #define regGCVM_INVALIDATE_ENG17_REQ_BASE_IDX … #define regGCVM_INVALIDATE_ENG0_ACK … #define regGCVM_INVALIDATE_ENG0_ACK_BASE_IDX … #define regGCVM_INVALIDATE_ENG1_ACK … #define regGCVM_INVALIDATE_ENG1_ACK_BASE_IDX … #define regGCVM_INVALIDATE_ENG2_ACK … #define regGCVM_INVALIDATE_ENG2_ACK_BASE_IDX … #define regGCVM_INVALIDATE_ENG3_ACK … #define regGCVM_INVALIDATE_ENG3_ACK_BASE_IDX … #define regGCVM_INVALIDATE_ENG4_ACK … #define regGCVM_INVALIDATE_ENG4_ACK_BASE_IDX … #define regGCVM_INVALIDATE_ENG5_ACK … #define regGCVM_INVALIDATE_ENG5_ACK_BASE_IDX … #define regGCVM_INVALIDATE_ENG6_ACK … #define regGCVM_INVALIDATE_ENG6_ACK_BASE_IDX … #define regGCVM_INVALIDATE_ENG7_ACK … #define regGCVM_INVALIDATE_ENG7_ACK_BASE_IDX … #define regGCVM_INVALIDATE_ENG8_ACK … #define regGCVM_INVALIDATE_ENG8_ACK_BASE_IDX … #define regGCVM_INVALIDATE_ENG9_ACK … #define regGCVM_INVALIDATE_ENG9_ACK_BASE_IDX … #define regGCVM_INVALIDATE_ENG10_ACK … #define regGCVM_INVALIDATE_ENG10_ACK_BASE_IDX … #define regGCVM_INVALIDATE_ENG11_ACK … #define regGCVM_INVALIDATE_ENG11_ACK_BASE_IDX … #define regGCVM_INVALIDATE_ENG12_ACK … #define regGCVM_INVALIDATE_ENG12_ACK_BASE_IDX … #define regGCVM_INVALIDATE_ENG13_ACK … #define regGCVM_INVALIDATE_ENG13_ACK_BASE_IDX … #define regGCVM_INVALIDATE_ENG14_ACK … #define regGCVM_INVALIDATE_ENG14_ACK_BASE_IDX … #define regGCVM_INVALIDATE_ENG15_ACK … #define regGCVM_INVALIDATE_ENG15_ACK_BASE_IDX … #define regGCVM_INVALIDATE_ENG16_ACK … #define regGCVM_INVALIDATE_ENG16_ACK_BASE_IDX … #define regGCVM_INVALIDATE_ENG17_ACK … #define regGCVM_INVALIDATE_ENG17_ACK_BASE_IDX … #define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 … #define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX … #define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 … #define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX … #define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 … #define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX … #define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 … #define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX … #define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 … #define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX … #define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 … #define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX … #define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 … #define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX … #define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 … #define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX … #define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 … #define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX … #define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 … #define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX … #define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 … #define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX … #define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 … #define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX … #define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 … #define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX … #define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 … #define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX … #define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 … #define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX … #define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 … #define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX … #define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 … #define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX … #define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 … #define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX … #define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 … #define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX … #define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 … #define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX … #define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 … #define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX … #define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 … #define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX … #define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 … #define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX … #define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 … #define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX … #define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 … #define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX … #define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 … #define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX … #define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 … #define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX … #define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 … #define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX … #define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 … #define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX … #define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 … #define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX … #define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 … #define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX … #define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 … #define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX … #define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 … #define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX … #define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 … #define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX … #define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 … #define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX … #define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 … #define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX … #define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 … #define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 … #define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 … #define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 … #define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 … #define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 … #define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 … #define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 … #define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 … #define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 … #define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 … #define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 … #define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 … #define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 … #define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 … #define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 … #define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 … #define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 … #define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 … #define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 … #define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 … #define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 … #define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 … #define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 … #define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 … #define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 … #define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 … #define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 … #define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 … #define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 … #define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 … #define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 … #define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 … #define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 … #define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 … #define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 … #define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 … #define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 … #define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 … #define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 … #define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 … #define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 … #define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 … #define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 … #define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 … #define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 … #define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 … #define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 … #define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 … #define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 … #define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 … #define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 … #define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 … #define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 … #define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 … #define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 … #define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 … #define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 … #define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 … #define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 … #define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 … #define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 … #define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 … #define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 … #define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 … #define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 … #define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 … #define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 … #define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 … #define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 … #define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 … #define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 … #define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 … #define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 … #define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 … #define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 … #define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 … #define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 … #define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 … #define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 … #define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 … #define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 … #define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 … #define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 … #define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 … #define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 … #define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 … #define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 … #define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 … #define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 … #define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 … #define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 … #define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 … #define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 … #define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 … #define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX … #define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 … #define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX … #define regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … #define regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES … #define regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX … // addressBlock: gc_gfx_cpwd_gcutcl2_gcvml2perfddec // base address: 0x35380 #define regGCVML2_PERFCOUNTER2_0_LO … #define regGCVML2_PERFCOUNTER2_0_LO_BASE_IDX … #define regGCVML2_PERFCOUNTER2_1_LO … #define regGCVML2_PERFCOUNTER2_1_LO_BASE_IDX … #define regGCVML2_PERFCOUNTER2_0_HI … #define regGCVML2_PERFCOUNTER2_0_HI_BASE_IDX … #define regGCVML2_PERFCOUNTER2_1_HI … #define regGCVML2_PERFCOUNTER2_1_HI_BASE_IDX … // addressBlock: gc_gfx_cpwd_gcutcl2_gcvml2prdec // base address: 0x35390 #define regGCMC_VM_L2_PERFCOUNTER_LO … #define regGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX … #define regGCMC_VM_L2_PERFCOUNTER_HI … #define regGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX … #define regGCUTCL2_PERFCOUNTER_LO … #define regGCUTCL2_PERFCOUNTER_LO_BASE_IDX … #define regGCUTCL2_PERFCOUNTER_HI … #define regGCUTCL2_PERFCOUNTER_HI_BASE_IDX … // addressBlock: gc_gfx_cpwd_gcutcl2_gcvml2perfsdec // base address: 0x37480 #define regGCVML2_PERFCOUNTER2_0_SELECT … #define regGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX … #define regGCVML2_PERFCOUNTER2_1_SELECT … #define regGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX … #define regGCVML2_PERFCOUNTER2_0_SELECT1 … #define regGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX … #define regGCVML2_PERFCOUNTER2_1_SELECT1 … #define regGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX … #define regGCVML2_PERFCOUNTER2_0_MODE … #define regGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX … #define regGCVML2_PERFCOUNTER2_1_MODE … #define regGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX … // addressBlock: gc_gfx_cpwd_gcutcl2_gcvml2pldec // base address: 0x374c0 #define regGCMC_VM_L2_PERFCOUNTER0_CFG … #define regGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX … #define regGCMC_VM_L2_PERFCOUNTER1_CFG … #define regGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX … #define regGCMC_VM_L2_PERFCOUNTER2_CFG … #define regGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX … #define regGCMC_VM_L2_PERFCOUNTER3_CFG … #define regGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX … #define regGCMC_VM_L2_PERFCOUNTER4_CFG … #define regGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX … #define regGCMC_VM_L2_PERFCOUNTER5_CFG … #define regGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX … #define regGCMC_VM_L2_PERFCOUNTER6_CFG … #define regGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX … #define regGCMC_VM_L2_PERFCOUNTER7_CFG … #define regGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX … #define regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL … #define regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … #define regGCUTCL2_PERFCOUNTER0_CFG … #define regGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX … #define regGCUTCL2_PERFCOUNTER1_CFG … #define regGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX … #define regGCUTCL2_PERFCOUNTER2_CFG … #define regGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX … #define regGCUTCL2_PERFCOUNTER3_CFG … #define regGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX … #define regGCUTCL2_PERFCOUNTER_RSLT_CNTL … #define regGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX … // addressBlock: gc_gfx_cpwd_gcutcl2_gcvml2pspdec // base address: 0x3f900 #define regGCUTCL2_TRANSLATION_BYPASS_BY_VMID … #define regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX … #define regGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE … #define regGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE_BASE_IDX … #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL … #define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX … #define regGCVM_IOMMU_CONTROL_REGISTER … #define regGCVM_IOMMU_CONTROL_REGISTER_BASE_IDX … #define regGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER … #define regGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX … #define regGCUTC_TRANSLATION_FAULT_CNTL0 … #define regGCUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX … #define regGCUTC_TRANSLATION_FAULT_CNTL1 … #define regGCUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX … #define regGCUTCL2_COMP_EN_OVERRIDES … #define regGCUTCL2_COMP_EN_OVERRIDES_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_cppdec // base address: 0xc080 #define regCP_CU_MASK_ADDR_LO … #define regCP_CU_MASK_ADDR_LO_BASE_IDX … #define regCP_CU_MASK_ADDR_HI … #define regCP_CU_MASK_ADDR_HI_BASE_IDX … #define regCP_CU_MASK_CNTL … #define regCP_CU_MASK_CNTL_BASE_IDX … #define regCP_EOPQ_WAIT_TIME … #define regCP_EOPQ_WAIT_TIME_BASE_IDX … #define regCP_CPC_MGCG_SYNC_CNTL … #define regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX … #define regCPC_INT_INFO … #define regCPC_INT_INFO_BASE_IDX … #define regCP_VIRT_STATUS … #define regCP_VIRT_STATUS_BASE_IDX … #define regCPC_INT_ADDR … #define regCPC_INT_ADDR_BASE_IDX … #define regCPC_INT_PASID … #define regCPC_INT_PASID_BASE_IDX … #define regCP_GFX_ERROR … #define regCP_GFX_ERROR_BASE_IDX … #define regCPG_UTCL1_CNTL … #define regCPG_UTCL1_CNTL_BASE_IDX … #define regCPC_UTCL1_CNTL … #define regCPC_UTCL1_CNTL_BASE_IDX … #define regCPF_UTCL1_CNTL … #define regCPF_UTCL1_CNTL_BASE_IDX … #define regCP_AQL_SMM_STATUS … #define regCP_AQL_SMM_STATUS_BASE_IDX … #define regCP_RB0_BASE … #define regCP_RB0_BASE_BASE_IDX … #define regCP_RB_BASE … #define regCP_RB_BASE_BASE_IDX … #define regCP_RB0_CNTL … #define regCP_RB0_CNTL_BASE_IDX … #define regCP_RB_CNTL … #define regCP_RB_CNTL_BASE_IDX … #define regCP_RB_RPTR_WR … #define regCP_RB_RPTR_WR_BASE_IDX … #define regCP_RB0_RPTR_ADDR … #define regCP_RB0_RPTR_ADDR_BASE_IDX … #define regCP_RB_RPTR_ADDR … #define regCP_RB_RPTR_ADDR_BASE_IDX … #define regCP_RB0_RPTR_ADDR_HI … #define regCP_RB0_RPTR_ADDR_HI_BASE_IDX … #define regCP_RB_RPTR_ADDR_HI … #define regCP_RB_RPTR_ADDR_HI_BASE_IDX … #define regCP_RB0_BUFSZ_MASK … #define regCP_RB0_BUFSZ_MASK_BASE_IDX … #define regCP_RB_BUFSZ_MASK … #define regCP_RB_BUFSZ_MASK_BASE_IDX … #define regCP_ME3_INT_STAT_DEBUG … #define regCP_ME3_INT_STAT_DEBUG_BASE_IDX … #define regGC_PRIV_MODE … #define regGC_PRIV_MODE_BASE_IDX … #define regCP_INT_CNTL … #define regCP_INT_CNTL_BASE_IDX … #define regCP_INT_STATUS … #define regCP_INT_STATUS_BASE_IDX … #define regCP_DEVICE_ID … #define regCP_DEVICE_ID_BASE_IDX … #define regCP_ME0_PIPE_PRIORITY_CNTS … #define regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX … #define regCP_RING_PRIORITY_CNTS … #define regCP_RING_PRIORITY_CNTS_BASE_IDX … #define regCP_ME0_PIPE0_PRIORITY … #define regCP_ME0_PIPE0_PRIORITY_BASE_IDX … #define regCP_RING0_PRIORITY … #define regCP_RING0_PRIORITY_BASE_IDX … #define regCP_FATAL_ERROR … #define regCP_FATAL_ERROR_BASE_IDX … #define regCP_RB_VMID … #define regCP_RB_VMID_BASE_IDX … #define regCP_ME0_PIPE0_VMID … #define regCP_ME0_PIPE0_VMID_BASE_IDX … #define regCP_RB0_WPTR … #define regCP_RB0_WPTR_BASE_IDX … #define regCP_RB_WPTR … #define regCP_RB_WPTR_BASE_IDX … #define regCP_RB0_WPTR_HI … #define regCP_RB0_WPTR_HI_BASE_IDX … #define regCP_RB_WPTR_HI … #define regCP_RB_WPTR_HI_BASE_IDX … #define regCP_PROCESS_QUANTUM … #define regCP_PROCESS_QUANTUM_BASE_IDX … #define regCP_RB_DOORBELL_RANGE_LOWER … #define regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX … #define regCP_RB_DOORBELL_RANGE_UPPER … #define regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX … #define regCP_MEC_DOORBELL_RANGE_LOWER … #define regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX … #define regCP_MEC_DOORBELL_RANGE_UPPER … #define regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX … #define regCPG_UTCL1_ERROR … #define regCPG_UTCL1_ERROR_BASE_IDX … #define regCPC_UTCL1_ERROR … #define regCPC_UTCL1_ERROR_BASE_IDX … #define regCP_IB1_BUFFER_COUNT … #define regCP_IB1_BUFFER_COUNT_BASE_IDX … #define regCP_IB2_BUFFER_COUNT … #define regCP_IB2_BUFFER_COUNT_BASE_IDX … #define regCP_INT_CNTL_RING0 … #define regCP_INT_CNTL_RING0_BASE_IDX … #define regCP_DEBUG_2 … #define regCP_DEBUG_2_BASE_IDX … #define regCP_INT_STATUS_RING0 … #define regCP_INT_STATUS_RING0_BASE_IDX … #define regCP_ME_F32_INTERRUPT … #define regCP_ME_F32_INTERRUPT_BASE_IDX … #define regCP_PFP_F32_INTERRUPT … #define regCP_PFP_F32_INTERRUPT_BASE_IDX … #define regCP_MEC1_F32_INTERRUPT … #define regCP_MEC1_F32_INTERRUPT_BASE_IDX … #define regCP_PWR_CNTL … #define regCP_PWR_CNTL_BASE_IDX … #define regCP_ECC_FIRSTOCCURRENCE … #define regCP_ECC_FIRSTOCCURRENCE_BASE_IDX … #define regCP_ECC_FIRSTOCCURRENCE_RING0 … #define regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX … #define regGB_EDC_MODE … #define regGB_EDC_MODE_BASE_IDX … #define regCP_DEBUG … #define regCP_DEBUG_BASE_IDX … #define regCP_CPF_DEBUG … #define regCP_CPF_DEBUG_BASE_IDX … #define regCP_CPC_DEBUG … #define regCP_CPC_DEBUG_BASE_IDX … #define regCP_PQ_WPTR_POLL_CNTL … #define regCP_PQ_WPTR_POLL_CNTL_BASE_IDX … #define regCP_PQ_WPTR_POLL_CNTL1 … #define regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX … #define regCP_ME1_PIPE0_INT_CNTL … #define regCP_ME1_PIPE0_INT_CNTL_BASE_IDX … #define regCP_ME1_PIPE1_INT_CNTL … #define regCP_ME1_PIPE1_INT_CNTL_BASE_IDX … #define regCP_ME1_PIPE0_INT_STATUS … #define regCP_ME1_PIPE0_INT_STATUS_BASE_IDX … #define regCP_ME1_PIPE1_INT_STATUS … #define regCP_ME1_PIPE1_INT_STATUS_BASE_IDX … #define regCP_ME1_INT_STAT_DEBUG … #define regCP_ME1_INT_STAT_DEBUG_BASE_IDX … #define regCP_GFX_QUEUE_INDEX … #define regCP_GFX_QUEUE_INDEX_BASE_IDX … #define regCC_GC_EDC_CONFIG … #define regCC_GC_EDC_CONFIG_BASE_IDX … #define regCP_ME1_PIPE_PRIORITY_CNTS … #define regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX … #define regCP_ME1_PIPE0_PRIORITY … #define regCP_ME1_PIPE0_PRIORITY_BASE_IDX … #define regCP_ME1_PIPE1_PRIORITY … #define regCP_ME1_PIPE1_PRIORITY_BASE_IDX … #define regCP_PFP_PRGRM_CNTR_START … #define regCP_PFP_PRGRM_CNTR_START_BASE_IDX … #define regCP_ME_PRGRM_CNTR_START … #define regCP_ME_PRGRM_CNTR_START_BASE_IDX … #define regCP_MEC1_PRGRM_CNTR_START … #define regCP_MEC1_PRGRM_CNTR_START_BASE_IDX … #define regCP_PFP_INTR_ROUTINE_START … #define regCP_PFP_INTR_ROUTINE_START_BASE_IDX … #define regCP_ME_INTR_ROUTINE_START … #define regCP_ME_INTR_ROUTINE_START_BASE_IDX … #define regCP_MEC1_INTR_ROUTINE_START … #define regCP_MEC1_INTR_ROUTINE_START_BASE_IDX … #define regCP_CONTEXT_CNTL … #define regCP_CONTEXT_CNTL_BASE_IDX … #define regCP_MAX_CONTEXT … #define regCP_MAX_CONTEXT_BASE_IDX … #define regCP_IQ_WAIT_TIME1 … #define regCP_IQ_WAIT_TIME1_BASE_IDX … #define regCP_IQ_WAIT_TIME2 … #define regCP_IQ_WAIT_TIME2_BASE_IDX … #define regCP_RB0_BASE_HI … #define regCP_RB0_BASE_HI_BASE_IDX … #define regCP_VMID_RESET … #define regCP_VMID_RESET_BASE_IDX … #define regCPC_INT_CNTL … #define regCPC_INT_CNTL_BASE_IDX … #define regCPC_INT_STATUS … #define regCPC_INT_STATUS_BASE_IDX … #define regCP_VMID_PREEMPT … #define regCP_VMID_PREEMPT_BASE_IDX … #define regCPC_INT_CNTX_ID … #define regCPC_INT_CNTX_ID_BASE_IDX … #define regCP_PQ_STATUS … #define regCP_PQ_STATUS_BASE_IDX … #define regCP_PFP_PRGRM_CNTR_START_HI … #define regCP_PFP_PRGRM_CNTR_START_HI_BASE_IDX … #define regCP_MAX_DRAW_COUNT … #define regCP_MAX_DRAW_COUNT_BASE_IDX … #define regCP_VMID_STATUS … #define regCP_VMID_STATUS_BASE_IDX … #define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO … #define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX … #define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI … #define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX … #define regCPC_SUSPEND_CTX_SAVE_CONTROL … #define regCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX … #define regCPC_SUSPEND_CNTL_STACK_OFFSET … #define regCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX … #define regCPC_SUSPEND_CNTL_STACK_SIZE … #define regCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX … #define regCPC_SUSPEND_WG_STATE_OFFSET … #define regCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX … #define regCPC_SUSPEND_CTX_SAVE_SIZE … #define regCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX … #define regCPC_OS_PIPES … #define regCPC_OS_PIPES_BASE_IDX … #define regCP_SUSPEND_RESUME_REQ … #define regCP_SUSPEND_RESUME_REQ_BASE_IDX … #define regCP_SUSPEND_CNTL … #define regCP_SUSPEND_CNTL_BASE_IDX … #define regCP_IQ_WAIT_TIME3 … #define regCP_IQ_WAIT_TIME3_BASE_IDX … #define regCPC_DDID_BASE_ADDR_LO … #define regCPC_DDID_BASE_ADDR_LO_BASE_IDX … #define regCP_DDID_BASE_ADDR_LO … #define regCP_DDID_BASE_ADDR_LO_BASE_IDX … #define regCPC_DDID_BASE_ADDR_HI … #define regCPC_DDID_BASE_ADDR_HI_BASE_IDX … #define regCP_DDID_BASE_ADDR_HI … #define regCP_DDID_BASE_ADDR_HI_BASE_IDX … #define regCPC_DDID_CNTL … #define regCPC_DDID_CNTL_BASE_IDX … #define regCP_DDID_CNTL … #define regCP_DDID_CNTL_BASE_IDX … #define regCP_GFX_DDID_INFLIGHT_COUNT … #define regCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX … #define regCP_GFX_DDID_WPTR … #define regCP_GFX_DDID_WPTR_BASE_IDX … #define regCP_GFX_DDID_RPTR … #define regCP_GFX_DDID_RPTR_BASE_IDX … #define regCP_GFX_DDID_DELTA_RPT_COUNT … #define regCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX … #define regCP_GFX_HPD_STATUS0 … #define regCP_GFX_HPD_STATUS0_BASE_IDX … #define regCP_GFX_HPD_CONTROL0 … #define regCP_GFX_HPD_CONTROL0_BASE_IDX … #define regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO … #define regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX … #define regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI … #define regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX … #define regCP_GFX_HPD_OSPRE_FENCE_DATA_LO … #define regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX … #define regCP_GFX_HPD_OSPRE_FENCE_DATA_HI … #define regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX … #define regCP_GFX_INDEX_MUTEX … #define regCP_GFX_INDEX_MUTEX_BASE_IDX … #define regCP_ME_PRGRM_CNTR_START_HI … #define regCP_ME_PRGRM_CNTR_START_HI_BASE_IDX … #define regCP_PFP_INTR_ROUTINE_START_HI … #define regCP_PFP_INTR_ROUTINE_START_HI_BASE_IDX … #define regCP_ME_INTR_ROUTINE_START_HI … #define regCP_ME_INTR_ROUTINE_START_HI_BASE_IDX … #define regCP_GFX_MQD_BASE_ADDR … #define regCP_GFX_MQD_BASE_ADDR_BASE_IDX … #define regCP_GFX_MQD_BASE_ADDR_HI … #define regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX … #define regCP_GFX_HQD_ACTIVE … #define regCP_GFX_HQD_ACTIVE_BASE_IDX … #define regCP_GFX_HQD_VMID … #define regCP_GFX_HQD_VMID_BASE_IDX … #define regCP_GFX_HQD_QUEUE_PRIORITY … #define regCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX … #define regCP_GFX_HQD_QUANTUM … #define regCP_GFX_HQD_QUANTUM_BASE_IDX … #define regCP_GFX_HQD_BASE … #define regCP_GFX_HQD_BASE_BASE_IDX … #define regCP_GFX_HQD_BASE_HI … #define regCP_GFX_HQD_BASE_HI_BASE_IDX … #define regCP_GFX_HQD_RPTR … #define regCP_GFX_HQD_RPTR_BASE_IDX … #define regCP_GFX_HQD_RPTR_ADDR … #define regCP_GFX_HQD_RPTR_ADDR_BASE_IDX … #define regCP_GFX_HQD_RPTR_ADDR_HI … #define regCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX … #define regCP_RB_WPTR_POLL_ADDR_LO … #define regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX … #define regCP_RB_WPTR_POLL_ADDR_HI … #define regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX … #define regCP_RB_DOORBELL_CONTROL … #define regCP_RB_DOORBELL_CONTROL_BASE_IDX … #define regCP_GFX_HQD_OFFSET … #define regCP_GFX_HQD_OFFSET_BASE_IDX … #define regCP_GFX_HQD_CNTL … #define regCP_GFX_HQD_CNTL_BASE_IDX … #define regCP_GFX_HQD_CSMD_RPTR … #define regCP_GFX_HQD_CSMD_RPTR_BASE_IDX … #define regCP_GFX_HQD_WPTR … #define regCP_GFX_HQD_WPTR_BASE_IDX … #define regCP_GFX_HQD_WPTR_HI … #define regCP_GFX_HQD_WPTR_HI_BASE_IDX … #define regCP_GFX_HQD_DEQUEUE_REQUEST … #define regCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX … #define regCP_GFX_HQD_MAPPED … #define regCP_GFX_HQD_MAPPED_BASE_IDX … #define regCP_GFX_HQD_QUE_MGR_CONTROL … #define regCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX … #define regCP_GFX_HQD_IQ_TIMER … #define regCP_GFX_HQD_IQ_TIMER_BASE_IDX … #define regCP_GFX_HQD_HQ_STATUS0 … #define regCP_GFX_HQD_HQ_STATUS0_BASE_IDX … #define regCP_GFX_HQD_HQ_CONTROL0 … #define regCP_GFX_HQD_HQ_CONTROL0_BASE_IDX … #define regCP_GFX_MQD_CONTROL … #define regCP_GFX_MQD_CONTROL_BASE_IDX … #define regCP_HQD_GFX_CONTROL … #define regCP_HQD_GFX_CONTROL_BASE_IDX … #define regCP_HQD_GFX_STATUS … #define regCP_HQD_GFX_STATUS_BASE_IDX … #define regCP_DMA_WATCH0_ADDR_LO … #define regCP_DMA_WATCH0_ADDR_LO_BASE_IDX … #define regCP_DMA_WATCH0_ADDR_HI … #define regCP_DMA_WATCH0_ADDR_HI_BASE_IDX … #define regCP_DMA_WATCH0_MASK … #define regCP_DMA_WATCH0_MASK_BASE_IDX … #define regCP_DMA_WATCH0_CNTL … #define regCP_DMA_WATCH0_CNTL_BASE_IDX … #define regCP_DMA_WATCH1_ADDR_LO … #define regCP_DMA_WATCH1_ADDR_LO_BASE_IDX … #define regCP_DMA_WATCH1_ADDR_HI … #define regCP_DMA_WATCH1_ADDR_HI_BASE_IDX … #define regCP_DMA_WATCH1_MASK … #define regCP_DMA_WATCH1_MASK_BASE_IDX … #define regCP_DMA_WATCH1_CNTL … #define regCP_DMA_WATCH1_CNTL_BASE_IDX … #define regCP_DMA_WATCH2_ADDR_LO … #define regCP_DMA_WATCH2_ADDR_LO_BASE_IDX … #define regCP_DMA_WATCH2_ADDR_HI … #define regCP_DMA_WATCH2_ADDR_HI_BASE_IDX … #define regCP_DMA_WATCH2_MASK … #define regCP_DMA_WATCH2_MASK_BASE_IDX … #define regCP_DMA_WATCH2_CNTL … #define regCP_DMA_WATCH2_CNTL_BASE_IDX … #define regCP_DMA_WATCH3_ADDR_LO … #define regCP_DMA_WATCH3_ADDR_LO_BASE_IDX … #define regCP_DMA_WATCH3_ADDR_HI … #define regCP_DMA_WATCH3_ADDR_HI_BASE_IDX … #define regCP_DMA_WATCH3_MASK … #define regCP_DMA_WATCH3_MASK_BASE_IDX … #define regCP_DMA_WATCH3_CNTL … #define regCP_DMA_WATCH3_CNTL_BASE_IDX … #define regCP_DMA_WATCH_STAT_ADDR_LO … #define regCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX … #define regCP_DMA_WATCH_STAT_ADDR_HI … #define regCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX … #define regCP_DMA_WATCH_STAT … #define regCP_DMA_WATCH_STAT_BASE_IDX … #define regCP_PFP_JT_STAT … #define regCP_PFP_JT_STAT_BASE_IDX … #define regCP_MEC_JT_STAT … #define regCP_MEC_JT_STAT_BASE_IDX … #define regCP_CPC_BUSY_HYSTERESIS … #define regCP_CPC_BUSY_HYSTERESIS_BASE_IDX … #define regCP_CPF_BUSY_HYSTERESIS1 … #define regCP_CPF_BUSY_HYSTERESIS1_BASE_IDX … #define regCP_CPF_BUSY_HYSTERESIS2 … #define regCP_CPF_BUSY_HYSTERESIS2_BASE_IDX … #define regCP_CPG_BUSY_HYSTERESIS1 … #define regCP_CPG_BUSY_HYSTERESIS1_BASE_IDX … #define regCP_CPG_BUSY_HYSTERESIS2 … #define regCP_CPG_BUSY_HYSTERESIS2_BASE_IDX … #define regCP_RB_DOORBELL_CLEAR … #define regCP_RB_DOORBELL_CLEAR_BASE_IDX … #define regCP_RB0_ACTIVE … #define regCP_RB0_ACTIVE_BASE_IDX … #define regCP_RB_ACTIVE … #define regCP_RB_ACTIVE_BASE_IDX … #define regCP_RB_STATUS … #define regCP_RB_STATUS_BASE_IDX … #define regCPG_RCIU_CAM_INDEX … #define regCPG_RCIU_CAM_INDEX_BASE_IDX … #define regCPG_RCIU_CAM_DATA … #define regCPG_RCIU_CAM_DATA_BASE_IDX … #define regCPG_RCIU_CAM_DATA_PHASE0 … #define regCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX … #define regCPG_RCIU_CAM_DATA_PHASE1 … #define regCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX … #define regCPG_RCIU_CAM_DATA_PHASE2 … #define regCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX … #define regCPG_RCIU_CAM_DATA_PHASE3 … #define regCPG_RCIU_CAM_DATA_PHASE3_BASE_IDX … #define regCP_GPU_TIMESTAMP_OFFSET_LO … #define regCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX … #define regCP_GPU_TIMESTAMP_OFFSET_HI … #define regCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX … #define regCP_SDMA_DMA_DONE … #define regCP_SDMA_DMA_DONE_BASE_IDX … #define regCP_PFP_SDMA_CS … #define regCP_PFP_SDMA_CS_BASE_IDX … #define regCP_ME_SDMA_CS … #define regCP_ME_SDMA_CS_BASE_IDX … #define regCPF_GCR_CNTL … #define regCPF_GCR_CNTL_BASE_IDX … #define regCPG_UTCL1_STATUS … #define regCPG_UTCL1_STATUS_BASE_IDX … #define regCPC_UTCL1_STATUS … #define regCPC_UTCL1_STATUS_BASE_IDX … #define regCPF_UTCL1_STATUS … #define regCPF_UTCL1_STATUS_BASE_IDX … #define regCP_SD_CNTL … #define regCP_SD_CNTL_BASE_IDX … #define regCP_SOFT_RESET_CNTL … #define regCP_SOFT_RESET_CNTL_BASE_IDX … #define regCP_CPC_GFX_CNTL … #define regCP_CPC_GFX_CNTL_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_cpphqddec // base address: 0xc800 #define regCP_HPD_UTCL1_CNTL … #define regCP_HPD_UTCL1_CNTL_BASE_IDX … #define regCP_HPD_UTCL1_ERROR … #define regCP_HPD_UTCL1_ERROR_BASE_IDX … #define regCP_HPD_UTCL1_ERROR_ADDR … #define regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX … #define regCP_MQD_BASE_ADDR … #define regCP_MQD_BASE_ADDR_BASE_IDX … #define regCP_MQD_BASE_ADDR_HI … #define regCP_MQD_BASE_ADDR_HI_BASE_IDX … #define regCP_HQD_ACTIVE … #define regCP_HQD_ACTIVE_BASE_IDX … #define regCP_HQD_VMID … #define regCP_HQD_VMID_BASE_IDX … #define regCP_HQD_PERSISTENT_STATE … #define regCP_HQD_PERSISTENT_STATE_BASE_IDX … #define regCP_HQD_PIPE_PRIORITY … #define regCP_HQD_PIPE_PRIORITY_BASE_IDX … #define regCP_HQD_QUEUE_PRIORITY … #define regCP_HQD_QUEUE_PRIORITY_BASE_IDX … #define regCP_HQD_QUANTUM … #define regCP_HQD_QUANTUM_BASE_IDX … #define regCP_HQD_PQ_BASE … #define regCP_HQD_PQ_BASE_BASE_IDX … #define regCP_HQD_PQ_BASE_HI … #define regCP_HQD_PQ_BASE_HI_BASE_IDX … #define regCP_HQD_PQ_RPTR … #define regCP_HQD_PQ_RPTR_BASE_IDX … #define regCP_HQD_PQ_RPTR_REPORT_ADDR … #define regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX … #define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI … #define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX … #define regCP_HQD_PQ_WPTR_POLL_ADDR … #define regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX … #define regCP_HQD_PQ_WPTR_POLL_ADDR_HI … #define regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX … #define regCP_HQD_PQ_DOORBELL_CONTROL … #define regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX … #define regCP_HQD_PQ_CONTROL … #define regCP_HQD_PQ_CONTROL_BASE_IDX … #define regCP_HQD_IB_BASE_ADDR … #define regCP_HQD_IB_BASE_ADDR_BASE_IDX … #define regCP_HQD_IB_BASE_ADDR_HI … #define regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX … #define regCP_HQD_IB_RPTR … #define regCP_HQD_IB_RPTR_BASE_IDX … #define regCP_HQD_IB_CONTROL … #define regCP_HQD_IB_CONTROL_BASE_IDX … #define regCP_HQD_IQ_TIMER … #define regCP_HQD_IQ_TIMER_BASE_IDX … #define regCP_HQD_IQ_RPTR … #define regCP_HQD_IQ_RPTR_BASE_IDX … #define regCP_HQD_DEQUEUE_REQUEST … #define regCP_HQD_DEQUEUE_REQUEST_BASE_IDX … #define regCP_HQD_DMA_OFFLOAD … #define regCP_HQD_DMA_OFFLOAD_BASE_IDX … #define regCP_HQD_OFFLOAD … #define regCP_HQD_OFFLOAD_BASE_IDX … #define regCP_HQD_MSG_TYPE … #define regCP_HQD_MSG_TYPE_BASE_IDX … #define regCP_HQD_ATOMIC0_PREOP_LO … #define regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX … #define regCP_HQD_ATOMIC0_PREOP_HI … #define regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX … #define regCP_HQD_ATOMIC1_PREOP_LO … #define regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX … #define regCP_HQD_ATOMIC1_PREOP_HI … #define regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX … #define regCP_HQD_HQ_SCHEDULER0 … #define regCP_HQD_HQ_SCHEDULER0_BASE_IDX … #define regCP_HQD_HQ_STATUS0 … #define regCP_HQD_HQ_STATUS0_BASE_IDX … #define regCP_HQD_HQ_CONTROL0 … #define regCP_HQD_HQ_CONTROL0_BASE_IDX … #define regCP_HQD_HQ_SCHEDULER1 … #define regCP_HQD_HQ_SCHEDULER1_BASE_IDX … #define regCP_MQD_CONTROL … #define regCP_MQD_CONTROL_BASE_IDX … #define regCP_HQD_HQ_STATUS1 … #define regCP_HQD_HQ_STATUS1_BASE_IDX … #define regCP_HQD_HQ_CONTROL1 … #define regCP_HQD_HQ_CONTROL1_BASE_IDX … #define regCP_HQD_EOP_BASE_ADDR … #define regCP_HQD_EOP_BASE_ADDR_BASE_IDX … #define regCP_HQD_EOP_BASE_ADDR_HI … #define regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX … #define regCP_HQD_EOP_CONTROL … #define regCP_HQD_EOP_CONTROL_BASE_IDX … #define regCP_HQD_EOP_RPTR … #define regCP_HQD_EOP_RPTR_BASE_IDX … #define regCP_HQD_EOP_WPTR … #define regCP_HQD_EOP_WPTR_BASE_IDX … #define regCP_HQD_EOP_EVENTS … #define regCP_HQD_EOP_EVENTS_BASE_IDX … #define regCP_HQD_CTX_SAVE_BASE_ADDR_LO … #define regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX … #define regCP_HQD_CTX_SAVE_BASE_ADDR_HI … #define regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX … #define regCP_HQD_CTX_SAVE_CONTROL … #define regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX … #define regCP_HQD_CNTL_STACK_OFFSET … #define regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX … #define regCP_HQD_CNTL_STACK_SIZE … #define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX … #define regCP_HQD_WG_STATE_OFFSET … #define regCP_HQD_WG_STATE_OFFSET_BASE_IDX … #define regCP_HQD_CTX_SAVE_SIZE … #define regCP_HQD_CTX_SAVE_SIZE_BASE_IDX … #define regCP_HQD_GDS_RESOURCE_STATE … #define regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX … #define regCP_HQD_ERROR … #define regCP_HQD_ERROR_BASE_IDX … #define regCP_HQD_EOP_WPTR_MEM … #define regCP_HQD_EOP_WPTR_MEM_BASE_IDX … #define regCP_HQD_AQL_CONTROL … #define regCP_HQD_AQL_CONTROL_BASE_IDX … #define regCP_HQD_PQ_WPTR_LO … #define regCP_HQD_PQ_WPTR_LO_BASE_IDX … #define regCP_HQD_PQ_WPTR_HI … #define regCP_HQD_PQ_WPTR_HI_BASE_IDX … #define regCP_HQD_SUSPEND_CNTL_STACK_OFFSET … #define regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX … #define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT … #define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX … #define regCP_HQD_SUSPEND_WG_STATE_OFFSET … #define regCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX … #define regCP_HQD_DDID_RPTR … #define regCP_HQD_DDID_RPTR_BASE_IDX … #define regCP_HQD_DDID_WPTR … #define regCP_HQD_DDID_WPTR_BASE_IDX … #define regCP_HQD_DDID_INFLIGHT_COUNT … #define regCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX … #define regCP_HQD_DDID_DELTA_RPT_COUNT … #define regCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX … #define regCP_HQD_DEQUEUE_STATUS … #define regCP_HQD_DEQUEUE_STATUS_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_gfxdec0 // base address: 0x28000 #define regCOHER_DEST_BASE_HI_0 … #define regCOHER_DEST_BASE_HI_0_BASE_IDX … #define regCOHER_DEST_BASE_HI_1 … #define regCOHER_DEST_BASE_HI_1_BASE_IDX … #define regCOHER_DEST_BASE_HI_2 … #define regCOHER_DEST_BASE_HI_2_BASE_IDX … #define regCOHER_DEST_BASE_HI_3 … #define regCOHER_DEST_BASE_HI_3_BASE_IDX … #define regCOHER_DEST_BASE_2 … #define regCOHER_DEST_BASE_2_BASE_IDX … #define regCOHER_DEST_BASE_3 … #define regCOHER_DEST_BASE_3_BASE_IDX … #define regCOHER_DEST_BASE_0 … #define regCOHER_DEST_BASE_0_BASE_IDX … #define regCOHER_DEST_BASE_1 … #define regCOHER_DEST_BASE_1_BASE_IDX … #define regCP_PERFMON_CNTX_CNTL … #define regCP_PERFMON_CNTX_CNTL_BASE_IDX … #define regCP_CP_PIPEID … #define regCP_CP_PIPEID_BASE_IDX … #define regCP_RINGID … #define regCP_RINGID_BASE_IDX … #define regCP_CP_VMID … #define regCP_CP_VMID_BASE_IDX … #define regCONTEXT_RESERVED_REG0 … #define regCONTEXT_RESERVED_REG0_BASE_IDX … #define regCONTEXT_RESERVED_REG1 … #define regCONTEXT_RESERVED_REG1_BASE_IDX … #define regVGT_MULTI_PRIM_IB_RESET_INDX … #define regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX … #define regGFX_COPY_STATE … #define regGFX_COPY_STATE_BASE_IDX … #define regVGT_DMA_BASE_HI … #define regVGT_DMA_BASE_HI_BASE_IDX … #define regVGT_DMA_BASE … #define regVGT_DMA_BASE_BASE_IDX … #define regVGT_DRAW_INITIATOR … #define regVGT_DRAW_INITIATOR_BASE_IDX … #define regVGT_EVENT_ADDRESS_REG … #define regVGT_EVENT_ADDRESS_REG_BASE_IDX … #define regVGT_HOS_MAX_TESS_LEVEL … #define regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX … #define regVGT_HOS_MIN_TESS_LEVEL … #define regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX … #define regGE_IA_ENHANCE … #define regGE_IA_ENHANCE_BASE_IDX … #define regVGT_DMA_SIZE … #define regVGT_DMA_SIZE_BASE_IDX … #define regVGT_DMA_MAX_SIZE … #define regVGT_DMA_MAX_SIZE_BASE_IDX … #define regVGT_DMA_INDEX_TYPE … #define regVGT_DMA_INDEX_TYPE_BASE_IDX … #define regGE_WD_ENHANCE … #define regGE_WD_ENHANCE_BASE_IDX … #define regVGT_DMA_NUM_INSTANCES … #define regVGT_DMA_NUM_INSTANCES_BASE_IDX … #define regVGT_EVENT_INITIATOR … #define regVGT_EVENT_INITIATOR_BASE_IDX … #define regVGT_SHADER_STAGES_EN … #define regVGT_SHADER_STAGES_EN_BASE_IDX … #define regVGT_TF_PARAM … #define regVGT_TF_PARAM_BASE_IDX … #define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET … #define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX … #define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE … #define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX … #define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE … #define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX … #define regVGT_TESS_DISTRIBUTION … #define regVGT_TESS_DISTRIBUTION_BASE_IDX … #define regVGT_LS_HS_CONFIG … #define regVGT_LS_HS_CONFIG_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_pfvf_cpdec // base address: 0x2a000 #define regCONFIG_RESERVED_REG0 … #define regCONFIG_RESERVED_REG0_BASE_IDX … #define regCONFIG_RESERVED_REG1 … #define regCONFIG_RESERVED_REG1_BASE_IDX … #define regCP_MEC_CNTL … #define regCP_MEC_CNTL_BASE_IDX … #define regCP_ME_CNTL … #define regCP_ME_CNTL_BASE_IDX … #define regCP_UNMAPPED_QUEUE0 … #define regCP_UNMAPPED_QUEUE0_BASE_IDX … #define regCP_UNMAPPED_QUEUE1 … #define regCP_UNMAPPED_QUEUE1_BASE_IDX … #define regCP_UNMAPPED_QUEUE2 … #define regCP_UNMAPPED_QUEUE2_BASE_IDX … #define regCP_UNMAPPED_QUEUE3 … #define regCP_UNMAPPED_QUEUE3_BASE_IDX … #define regCP_UNMAPPED_QUEUE4 … #define regCP_UNMAPPED_QUEUE4_BASE_IDX … #define regCP_UNMAPPED_QUEUE5 … #define regCP_UNMAPPED_QUEUE5_BASE_IDX … #define regCP_UNMAPPED_QUEUE6 … #define regCP_UNMAPPED_QUEUE6_BASE_IDX … #define regCP_UNMAPPED_QUEUE7 … #define regCP_UNMAPPED_QUEUE7_BASE_IDX … #define regCP_UNMAPPED_QUEUE8 … #define regCP_UNMAPPED_QUEUE8_BASE_IDX … #define regCP_UNMAPPED_QUEUE9 … #define regCP_UNMAPPED_QUEUE9_BASE_IDX … #define regCP_UNMAPPED_QUEUE10 … #define regCP_UNMAPPED_QUEUE10_BASE_IDX … #define regCP_UNMAPPED_QUEUE11 … #define regCP_UNMAPPED_QUEUE11_BASE_IDX … #define regCP_UNMAPPED_QUEUE12 … #define regCP_UNMAPPED_QUEUE12_BASE_IDX … #define regCP_UNMAPPED_QUEUE13 … #define regCP_UNMAPPED_QUEUE13_BASE_IDX … #define regCP_UNMAPPED_QUEUE14 … #define regCP_UNMAPPED_QUEUE14_BASE_IDX … #define regCP_UNMAPPED_QUEUE15 … #define regCP_UNMAPPED_QUEUE15_BASE_IDX … #define regCP_UNMAPPED_QUEUE16 … #define regCP_UNMAPPED_QUEUE16_BASE_IDX … #define regCP_UNMAPPED_QUEUE17 … #define regCP_UNMAPPED_QUEUE17_BASE_IDX … #define regCP_UNMAPPED_QUEUE18 … #define regCP_UNMAPPED_QUEUE18_BASE_IDX … #define regCP_UNMAPPED_QUEUE19 … #define regCP_UNMAPPED_QUEUE19_BASE_IDX … #define regCP_UNMAPPED_QUEUE20 … #define regCP_UNMAPPED_QUEUE20_BASE_IDX … #define regCP_UNMAPPED_QUEUE21 … #define regCP_UNMAPPED_QUEUE21_BASE_IDX … #define regCP_UNMAPPED_QUEUE22 … #define regCP_UNMAPPED_QUEUE22_BASE_IDX … #define regCP_UNMAPPED_QUEUE23 … #define regCP_UNMAPPED_QUEUE23_BASE_IDX … #define regCP_UNMAPPED_QUEUE24 … #define regCP_UNMAPPED_QUEUE24_BASE_IDX … #define regCP_UNMAPPED_QUEUE25 … #define regCP_UNMAPPED_QUEUE25_BASE_IDX … #define regCP_UNMAPPED_QUEUE26 … #define regCP_UNMAPPED_QUEUE26_BASE_IDX … #define regCP_UNMAPPED_QUEUE27 … #define regCP_UNMAPPED_QUEUE27_BASE_IDX … #define regCP_UNMAPPED_QUEUE28 … #define regCP_UNMAPPED_QUEUE28_BASE_IDX … #define regCP_UNMAPPED_QUEUE29 … #define regCP_UNMAPPED_QUEUE29_BASE_IDX … #define regCP_UNMAPPED_QUEUE30 … #define regCP_UNMAPPED_QUEUE30_BASE_IDX … #define regCP_UNMAPPED_QUEUE31 … #define regCP_UNMAPPED_QUEUE31_BASE_IDX … #define regCP_UNMAPPED_QUEUE32 … #define regCP_UNMAPPED_QUEUE32_BASE_IDX … #define regCP_UNMAPPED_QUEUE33 … #define regCP_UNMAPPED_QUEUE33_BASE_IDX … #define regCP_UNMAPPED_QUEUE34 … #define regCP_UNMAPPED_QUEUE34_BASE_IDX … #define regCP_UNMAPPED_QUEUE35 … #define regCP_UNMAPPED_QUEUE35_BASE_IDX … #define regCP_UNMAPPED_QUEUE36 … #define regCP_UNMAPPED_QUEUE36_BASE_IDX … #define regCP_UNMAPPED_QUEUE37 … #define regCP_UNMAPPED_QUEUE37_BASE_IDX … #define regCP_UNMAPPED_QUEUE38 … #define regCP_UNMAPPED_QUEUE38_BASE_IDX … #define regCP_UNMAPPED_QUEUE39 … #define regCP_UNMAPPED_QUEUE39_BASE_IDX … #define regCP_UNMAPPED_QUEUE40 … #define regCP_UNMAPPED_QUEUE40_BASE_IDX … #define regCP_UNMAPPED_QUEUE41 … #define regCP_UNMAPPED_QUEUE41_BASE_IDX … #define regCP_UNMAPPED_QUEUE42 … #define regCP_UNMAPPED_QUEUE42_BASE_IDX … #define regCP_UNMAPPED_QUEUE43 … #define regCP_UNMAPPED_QUEUE43_BASE_IDX … #define regCP_UNMAPPED_QUEUE44 … #define regCP_UNMAPPED_QUEUE44_BASE_IDX … #define regCP_UNMAPPED_QUEUE45 … #define regCP_UNMAPPED_QUEUE45_BASE_IDX … #define regCP_UNMAPPED_QUEUE46 … #define regCP_UNMAPPED_QUEUE46_BASE_IDX … #define regCP_UNMAPPED_QUEUE47 … #define regCP_UNMAPPED_QUEUE47_BASE_IDX … #define regCP_UNMAPPED_QUEUE48 … #define regCP_UNMAPPED_QUEUE48_BASE_IDX … #define regCP_UNMAPPED_QUEUE49 … #define regCP_UNMAPPED_QUEUE49_BASE_IDX … #define regCP_UNMAPPED_QUEUE50 … #define regCP_UNMAPPED_QUEUE50_BASE_IDX … #define regCP_UNMAPPED_QUEUE51 … #define regCP_UNMAPPED_QUEUE51_BASE_IDX … #define regCP_UNMAPPED_QUEUE52 … #define regCP_UNMAPPED_QUEUE52_BASE_IDX … #define regCP_UNMAPPED_QUEUE53 … #define regCP_UNMAPPED_QUEUE53_BASE_IDX … #define regCP_UNMAPPED_QUEUE54 … #define regCP_UNMAPPED_QUEUE54_BASE_IDX … #define regCP_UNMAPPED_QUEUE55 … #define regCP_UNMAPPED_QUEUE55_BASE_IDX … #define regCP_UNMAPPED_QUEUE56 … #define regCP_UNMAPPED_QUEUE56_BASE_IDX … #define regCP_UNMAPPED_QUEUE57 … #define regCP_UNMAPPED_QUEUE57_BASE_IDX … #define regCP_UNMAPPED_QUEUE58 … #define regCP_UNMAPPED_QUEUE58_BASE_IDX … #define regCP_UNMAPPED_QUEUE59 … #define regCP_UNMAPPED_QUEUE59_BASE_IDX … #define regCP_UNMAPPED_QUEUE60 … #define regCP_UNMAPPED_QUEUE60_BASE_IDX … #define regCP_UNMAPPED_QUEUE61 … #define regCP_UNMAPPED_QUEUE61_BASE_IDX … #define regCP_UNMAPPED_QUEUE62 … #define regCP_UNMAPPED_QUEUE62_BASE_IDX … #define regCP_UNMAPPED_QUEUE63 … #define regCP_UNMAPPED_QUEUE63_BASE_IDX … #define regCP_UNMAPPED_DOORBELL … #define regCP_UNMAPPED_DOORBELL_BASE_IDX … #define regCP_UNMAPPED_QUEUE_BANK0 … #define regCP_UNMAPPED_QUEUE_BANK0_BASE_IDX … #define regCP_UNMAPPED_QUEUE_BANK1 … #define regCP_UNMAPPED_QUEUE_BANK1_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_pfvf_grbmdec // base address: 0x2a400 #define regGRBM_GFX_CNTL … #define regGRBM_GFX_CNTL_BASE_IDX … #define regGRBM_NOWHERE … #define regGRBM_NOWHERE_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_pfonly_cpdec // base address: 0x2e000 #define regCP_FETCHER_SOURCE … #define regCP_FETCHER_SOURCE_BASE_IDX … #define regCP_DFY_CNTL … #define regCP_DFY_CNTL_BASE_IDX … #define regCP_DFY_STAT … #define regCP_DFY_STAT_BASE_IDX … #define regCP_DFY_ADDR_HI … #define regCP_DFY_ADDR_HI_BASE_IDX … #define regCP_DFY_ADDR_LO … #define regCP_DFY_ADDR_LO_BASE_IDX … #define regCP_DFY_DATA_0 … #define regCP_DFY_DATA_0_BASE_IDX … #define regCP_DFY_DATA_1 … #define regCP_DFY_DATA_1_BASE_IDX … #define regCP_DFY_DATA_2 … #define regCP_DFY_DATA_2_BASE_IDX … #define regCP_DFY_DATA_3 … #define regCP_DFY_DATA_3_BASE_IDX … #define regCP_DFY_DATA_4 … #define regCP_DFY_DATA_4_BASE_IDX … #define regCP_DFY_DATA_5 … #define regCP_DFY_DATA_5_BASE_IDX … #define regCP_DFY_DATA_6 … #define regCP_DFY_DATA_6_BASE_IDX … #define regCP_DFY_DATA_7 … #define regCP_DFY_DATA_7_BASE_IDX … #define regCP_DFY_DATA_8 … #define regCP_DFY_DATA_8_BASE_IDX … #define regCP_DFY_DATA_9 … #define regCP_DFY_DATA_9_BASE_IDX … #define regCP_DFY_DATA_10 … #define regCP_DFY_DATA_10_BASE_IDX … #define regCP_DFY_DATA_11 … #define regCP_DFY_DATA_11_BASE_IDX … #define regCP_DFY_DATA_12 … #define regCP_DFY_DATA_12_BASE_IDX … #define regCP_DFY_DATA_13 … #define regCP_DFY_DATA_13_BASE_IDX … #define regCP_DFY_DATA_14 … #define regCP_DFY_DATA_14_BASE_IDX … #define regCP_DFY_DATA_15 … #define regCP_DFY_DATA_15_BASE_IDX … #define regCP_DFY_CMD … #define regCP_DFY_CMD_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_pfonly_cpphqddec // base address: 0x2e080 #define regCP_HPD_MES_ROQ_OFFSETS … #define regCP_HPD_MES_ROQ_OFFSETS_BASE_IDX … #define regCP_HPD_ROQ_OFFSETS … #define regCP_HPD_ROQ_OFFSETS_BASE_IDX … #define regCP_HPD_STATUS0 … #define regCP_HPD_STATUS0_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_pfonly_gcrdec // base address: 0x2e640 #define regGCR_GENERAL_CNTL … #define regGCR_GENERAL_CNTL_BASE_IDX … #define regGCR_TARGET_DISABLE … #define regGCR_TARGET_DISABLE_BASE_IDX … #define regGCR_CMD_STATUS … #define regGCR_CMD_STATUS_BASE_IDX … #define regGCR_SPARE … #define regGCR_SPARE_BASE_IDX … #define regPMM_CNTL2 … #define regPMM_CNTL2_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_gfxudec // base address: 0x30000 #define regCP_EOP_DONE_ADDR_LO … #define regCP_EOP_DONE_ADDR_LO_BASE_IDX … #define regCP_EOP_DONE_ADDR_HI … #define regCP_EOP_DONE_ADDR_HI_BASE_IDX … #define regCP_EOP_DONE_DATA_LO … #define regCP_EOP_DONE_DATA_LO_BASE_IDX … #define regCP_EOP_DONE_DATA_HI … #define regCP_EOP_DONE_DATA_HI_BASE_IDX … #define regCP_EOP_LAST_FENCE_LO … #define regCP_EOP_LAST_FENCE_LO_BASE_IDX … #define regCP_EOP_LAST_FENCE_HI … #define regCP_EOP_LAST_FENCE_HI_BASE_IDX … #define regCP_PIPE_STATS_ADDR_LO … #define regCP_PIPE_STATS_ADDR_LO_BASE_IDX … #define regCP_PIPE_STATS_ADDR_HI … #define regCP_PIPE_STATS_ADDR_HI_BASE_IDX … #define regCP_VGT_IAVERT_COUNT_LO … #define regCP_VGT_IAVERT_COUNT_LO_BASE_IDX … #define regCP_VGT_IAVERT_COUNT_HI … #define regCP_VGT_IAVERT_COUNT_HI_BASE_IDX … #define regCP_VGT_IAPRIM_COUNT_LO … #define regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX … #define regCP_VGT_IAPRIM_COUNT_HI … #define regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX … #define regCP_VGT_GSPRIM_COUNT_LO … #define regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX … #define regCP_VGT_GSPRIM_COUNT_HI … #define regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX … #define regCP_VGT_VSINVOC_COUNT_LO … #define regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX … #define regCP_VGT_VSINVOC_COUNT_HI … #define regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX … #define regCP_VGT_GSINVOC_COUNT_LO … #define regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX … #define regCP_VGT_GSINVOC_COUNT_HI … #define regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX … #define regCP_VGT_HSINVOC_COUNT_LO … #define regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX … #define regCP_VGT_HSINVOC_COUNT_HI … #define regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX … #define regCP_VGT_DSINVOC_COUNT_LO … #define regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX … #define regCP_VGT_DSINVOC_COUNT_HI … #define regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX … #define regCP_PA_CINVOC_COUNT_LO … #define regCP_PA_CINVOC_COUNT_LO_BASE_IDX … #define regCP_PA_CINVOC_COUNT_HI … #define regCP_PA_CINVOC_COUNT_HI_BASE_IDX … #define regCP_PA_CPRIM_COUNT_LO … #define regCP_PA_CPRIM_COUNT_LO_BASE_IDX … #define regCP_PA_CPRIM_COUNT_HI … #define regCP_PA_CPRIM_COUNT_HI_BASE_IDX … #define regCP_SC_PSINVOC_COUNT0_LO … #define regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX … #define regCP_SC_PSINVOC_COUNT0_HI … #define regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX … #define regCP_SC_PSINVOC_COUNT1_LO … #define regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX … #define regCP_SC_PSINVOC_COUNT1_HI … #define regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX … #define regCP_VGT_CSINVOC_COUNT_LO … #define regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX … #define regCP_VGT_CSINVOC_COUNT_HI … #define regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX … #define regCP_VGT_ASINVOC_COUNT_LO … #define regCP_VGT_ASINVOC_COUNT_LO_BASE_IDX … #define regCP_VGT_ASINVOC_COUNT_HI … #define regCP_VGT_ASINVOC_COUNT_HI_BASE_IDX … #define regCP_PIPE_STATS_CONTROL … #define regCP_PIPE_STATS_CONTROL_BASE_IDX … #define regSCRATCH_REG0 … #define regSCRATCH_REG0_BASE_IDX … #define regSCRATCH_REG1 … #define regSCRATCH_REG1_BASE_IDX … #define regSCRATCH_REG2 … #define regSCRATCH_REG2_BASE_IDX … #define regSCRATCH_REG3 … #define regSCRATCH_REG3_BASE_IDX … #define regSCRATCH_REG4 … #define regSCRATCH_REG4_BASE_IDX … #define regSCRATCH_REG5 … #define regSCRATCH_REG5_BASE_IDX … #define regSCRATCH_REG6 … #define regSCRATCH_REG6_BASE_IDX … #define regSCRATCH_REG7 … #define regSCRATCH_REG7_BASE_IDX … #define regSCRATCH_REG_ATOMIC … #define regSCRATCH_REG_ATOMIC_BASE_IDX … #define regSCRATCH_REG_CMPSWAP_ATOMIC … #define regSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX … #define regCP_APPEND_DDID_CNT … #define regCP_APPEND_DDID_CNT_BASE_IDX … #define regCP_APPEND_DATA_HI … #define regCP_APPEND_DATA_HI_BASE_IDX … #define regCP_APPEND_LAST_CS_FENCE_HI … #define regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX … #define regCP_APPEND_LAST_PS_FENCE_HI … #define regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX … #define regCP_PFP_ATOMIC_PREOP_LO … #define regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX … #define regCP_PFP_ATOMIC_PREOP_HI … #define regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX … #define regCP_APPEND_ADDR_LO … #define regCP_APPEND_ADDR_LO_BASE_IDX … #define regCP_APPEND_ADDR_HI … #define regCP_APPEND_ADDR_HI_BASE_IDX … #define regCP_APPEND_DATA … #define regCP_APPEND_DATA_BASE_IDX … #define regCP_APPEND_DATA_LO … #define regCP_APPEND_DATA_LO_BASE_IDX … #define regCP_APPEND_LAST_CS_FENCE … #define regCP_APPEND_LAST_CS_FENCE_BASE_IDX … #define regCP_APPEND_LAST_CS_FENCE_LO … #define regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX … #define regCP_APPEND_LAST_PS_FENCE … #define regCP_APPEND_LAST_PS_FENCE_BASE_IDX … #define regCP_APPEND_LAST_PS_FENCE_LO … #define regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX … #define regCP_ATOMIC_PREOP_LO … #define regCP_ATOMIC_PREOP_LO_BASE_IDX … #define regCP_ME_ATOMIC_PREOP_LO … #define regCP_ME_ATOMIC_PREOP_LO_BASE_IDX … #define regCP_ATOMIC_PREOP_HI … #define regCP_ATOMIC_PREOP_HI_BASE_IDX … #define regCP_ME_ATOMIC_PREOP_HI … #define regCP_ME_ATOMIC_PREOP_HI_BASE_IDX … #define regCP_ME_MC_WADDR_LO … #define regCP_ME_MC_WADDR_LO_BASE_IDX … #define regCP_ME_MC_WADDR_HI … #define regCP_ME_MC_WADDR_HI_BASE_IDX … #define regCP_ME_MC_WDATA_LO … #define regCP_ME_MC_WDATA_LO_BASE_IDX … #define regCP_ME_MC_WDATA_HI … #define regCP_ME_MC_WDATA_HI_BASE_IDX … #define regCP_ME_MC_RADDR_LO … #define regCP_ME_MC_RADDR_LO_BASE_IDX … #define regCP_ME_MC_RADDR_HI … #define regCP_ME_MC_RADDR_HI_BASE_IDX … #define regCP_WAIT_REG_MEM_TIMEOUT … #define regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX … #define regCP_DMA_PFP_CONTROL … #define regCP_DMA_PFP_CONTROL_BASE_IDX … #define regCP_DMA_ME_CONTROL … #define regCP_DMA_ME_CONTROL_BASE_IDX … #define regCP_DMA_ME_SRC_ADDR … #define regCP_DMA_ME_SRC_ADDR_BASE_IDX … #define regCP_DMA_ME_SRC_ADDR_HI … #define regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX … #define regCP_DMA_ME_DST_ADDR … #define regCP_DMA_ME_DST_ADDR_BASE_IDX … #define regCP_DMA_ME_DST_ADDR_HI … #define regCP_DMA_ME_DST_ADDR_HI_BASE_IDX … #define regCP_DMA_ME_COMMAND … #define regCP_DMA_ME_COMMAND_BASE_IDX … #define regCP_DMA_PFP_SRC_ADDR … #define regCP_DMA_PFP_SRC_ADDR_BASE_IDX … #define regCP_DMA_PFP_SRC_ADDR_HI … #define regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX … #define regCP_DMA_PFP_DST_ADDR … #define regCP_DMA_PFP_DST_ADDR_BASE_IDX … #define regCP_DMA_PFP_DST_ADDR_HI … #define regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX … #define regCP_DMA_PFP_COMMAND … #define regCP_DMA_PFP_COMMAND_BASE_IDX … #define regCP_DMA_CNTL … #define regCP_DMA_CNTL_BASE_IDX … #define regCP_DMA_READ_TAGS … #define regCP_DMA_READ_TAGS_BASE_IDX … #define regCP_PFP_IB_CONTROL … #define regCP_PFP_IB_CONTROL_BASE_IDX … #define regCP_PFP_LOAD_CONTROL … #define regCP_PFP_LOAD_CONTROL_BASE_IDX … #define regCP_SCRATCH_INDEX … #define regCP_SCRATCH_INDEX_BASE_IDX … #define regCP_SCRATCH_DATA … #define regCP_SCRATCH_DATA_BASE_IDX … #define regCP_RB_OFFSET … #define regCP_RB_OFFSET_BASE_IDX … #define regCP_IB1_OFFSET … #define regCP_IB1_OFFSET_BASE_IDX … #define regCP_IB2_OFFSET … #define regCP_IB2_OFFSET_BASE_IDX … #define regCP_IB1_PREAMBLE_BEGIN … #define regCP_IB1_PREAMBLE_BEGIN_BASE_IDX … #define regCP_IB1_PREAMBLE_END … #define regCP_IB1_PREAMBLE_END_BASE_IDX … #define regCP_IB2_PREAMBLE_BEGIN … #define regCP_IB2_PREAMBLE_BEGIN_BASE_IDX … #define regCP_IB2_PREAMBLE_END … #define regCP_IB2_PREAMBLE_END_BASE_IDX … #define regCP_DMA_ME_CMD_ADDR_LO … #define regCP_DMA_ME_CMD_ADDR_LO_BASE_IDX … #define regCP_DMA_ME_CMD_ADDR_HI … #define regCP_DMA_ME_CMD_ADDR_HI_BASE_IDX … #define regCP_DMA_PFP_CMD_ADDR_LO … #define regCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX … #define regCP_DMA_PFP_CMD_ADDR_HI … #define regCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX … #define regUCONFIG_RESERVED_REG0 … #define regUCONFIG_RESERVED_REG0_BASE_IDX … #define regUCONFIG_RESERVED_REG1 … #define regUCONFIG_RESERVED_REG1_BASE_IDX … #define regCP_PA_MSPRIM_COUNT_LO … #define regCP_PA_MSPRIM_COUNT_LO_BASE_IDX … #define regCP_PA_MSPRIM_COUNT_HI … #define regCP_PA_MSPRIM_COUNT_HI_BASE_IDX … #define regCP_GE_MSINVOC_COUNT_LO … #define regCP_GE_MSINVOC_COUNT_LO_BASE_IDX … #define regCP_GE_MSINVOC_COUNT_HI … #define regCP_GE_MSINVOC_COUNT_HI_BASE_IDX … #define regCP_IB1_CMD_BUFSZ … #define regCP_IB1_CMD_BUFSZ_BASE_IDX … #define regCP_IB2_CMD_BUFSZ … #define regCP_IB2_CMD_BUFSZ_BASE_IDX … #define regCP_ST_CMD_BUFSZ … #define regCP_ST_CMD_BUFSZ_BASE_IDX … #define regCP_IB1_BASE_LO … #define regCP_IB1_BASE_LO_BASE_IDX … #define regCP_IB1_BASE_HI … #define regCP_IB1_BASE_HI_BASE_IDX … #define regCP_IB1_BUFSZ … #define regCP_IB1_BUFSZ_BASE_IDX … #define regCP_IB2_BASE_LO … #define regCP_IB2_BASE_LO_BASE_IDX … #define regCP_IB2_BASE_HI … #define regCP_IB2_BASE_HI_BASE_IDX … #define regCP_IB2_BUFSZ … #define regCP_IB2_BUFSZ_BASE_IDX … #define regCP_ST_BASE_LO … #define regCP_ST_BASE_LO_BASE_IDX … #define regCP_ST_BASE_HI … #define regCP_ST_BASE_HI_BASE_IDX … #define regCP_ST_BUFSZ … #define regCP_ST_BUFSZ_BASE_IDX … #define regCP_EOP_DONE_EVENT_CNTL … #define regCP_EOP_DONE_EVENT_CNTL_BASE_IDX … #define regCP_EOP_DONE_DATA_CNTL … #define regCP_EOP_DONE_DATA_CNTL_BASE_IDX … #define regCP_EOP_DONE_CNTX_ID … #define regCP_EOP_DONE_CNTX_ID_BASE_IDX … #define regCP_DB_BASE_LO … #define regCP_DB_BASE_LO_BASE_IDX … #define regCP_DB_BASE_HI … #define regCP_DB_BASE_HI_BASE_IDX … #define regCP_DB_BUFSZ … #define regCP_DB_BUFSZ_BASE_IDX … #define regCP_DB_CMD_BUFSZ … #define regCP_DB_CMD_BUFSZ_BASE_IDX … #define regCP_PFP_COMPLETION_STATUS … #define regCP_PFP_COMPLETION_STATUS_BASE_IDX … #define regCP_PRED_NOT_VISIBLE … #define regCP_PRED_NOT_VISIBLE_BASE_IDX … #define regCP_PFP_METADATA_BASE_ADDR … #define regCP_PFP_METADATA_BASE_ADDR_BASE_IDX … #define regCP_PFP_METADATA_BASE_ADDR_HI … #define regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX … #define regCP_DRAW_INDX_INDR_ADDR … #define regCP_DRAW_INDX_INDR_ADDR_BASE_IDX … #define regCP_DRAW_INDX_INDR_ADDR_HI … #define regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX … #define regCP_DISPATCH_INDR_ADDR … #define regCP_DISPATCH_INDR_ADDR_BASE_IDX … #define regCP_DISPATCH_INDR_ADDR_HI … #define regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX … #define regCP_INDEX_BASE_ADDR … #define regCP_INDEX_BASE_ADDR_BASE_IDX … #define regCP_INDEX_BASE_ADDR_HI … #define regCP_INDEX_BASE_ADDR_HI_BASE_IDX … #define regCP_INDEX_TYPE … #define regCP_INDEX_TYPE_BASE_IDX … #define regCP_SAMPLE_STATUS … #define regCP_SAMPLE_STATUS_BASE_IDX … #define regCP_ME_COHER_CNTL … #define regCP_ME_COHER_CNTL_BASE_IDX … #define regCP_ME_COHER_SIZE … #define regCP_ME_COHER_SIZE_BASE_IDX … #define regCP_ME_COHER_SIZE_HI … #define regCP_ME_COHER_SIZE_HI_BASE_IDX … #define regCP_ME_COHER_BASE … #define regCP_ME_COHER_BASE_BASE_IDX … #define regCP_ME_COHER_BASE_HI … #define regCP_ME_COHER_BASE_HI_BASE_IDX … #define regCP_ME_COHER_STATUS … #define regCP_ME_COHER_STATUS_BASE_IDX … #define regRLC_GPM_PERF_COUNT_0 … #define regRLC_GPM_PERF_COUNT_0_BASE_IDX … #define regRLC_GPM_PERF_COUNT_1 … #define regRLC_GPM_PERF_COUNT_1_BASE_IDX … #define regGRBM_GFX_INDEX … #define regGRBM_GFX_INDEX_BASE_IDX … #define regGRBM_NOWHERE_2 … #define regGRBM_NOWHERE_2_BASE_IDX … #define regVGT_PRIMITIVE_TYPE … #define regVGT_PRIMITIVE_TYPE_BASE_IDX … #define regVGT_INDEX_TYPE … #define regVGT_INDEX_TYPE_BASE_IDX … #define regGE_MIN_VTX_INDX … #define regGE_MIN_VTX_INDX_BASE_IDX … #define regGE_INDX_OFFSET … #define regGE_INDX_OFFSET_BASE_IDX … #define regGE_MULTI_PRIM_IB_RESET_EN … #define regGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX … #define regVGT_NUM_INDICES … #define regVGT_NUM_INDICES_BASE_IDX … #define regVGT_NUM_INSTANCES … #define regVGT_NUM_INSTANCES_BASE_IDX … #define regVGT_TF_MEMORY_BASE … #define regVGT_TF_MEMORY_BASE_BASE_IDX … #define regGE_GS_THROTTLE … #define regGE_GS_THROTTLE_BASE_IDX … #define regGE_MAX_VTX_INDX … #define regGE_MAX_VTX_INDX_BASE_IDX … #define regVGT_INSTANCE_BASE_ID … #define regVGT_INSTANCE_BASE_ID_BASE_IDX … #define regGE_CNTL … #define regGE_CNTL_BASE_IDX … #define regGE_USER_VGPR1 … #define regGE_USER_VGPR1_BASE_IDX … #define regGE_USER_VGPR2 … #define regGE_USER_VGPR2_BASE_IDX … #define regGE_USER_VGPR3 … #define regGE_USER_VGPR3_BASE_IDX … #define regGE_STEREO_CNTL … #define regGE_STEREO_CNTL_BASE_IDX … #define regGE_USER_VGPR_EN … #define regGE_USER_VGPR_EN_BASE_IDX … #define regVGT_PRIMITIVEID_EN … #define regVGT_PRIMITIVEID_EN_BASE_IDX … #define regGE_VRS_RATE … #define regGE_VRS_RATE_BASE_IDX … #define regGE_GS_FAST_LAUNCH_WG_DIM … #define regGE_GS_FAST_LAUNCH_WG_DIM_BASE_IDX … #define regGE_GS_FAST_LAUNCH_WG_DIM_1 … #define regGE_GS_FAST_LAUNCH_WG_DIM_1_BASE_IDX … #define regVGT_GS_OUT_PRIM_TYPE … #define regVGT_GS_OUT_PRIM_TYPE_BASE_IDX … #define regVGT_TF_MEMORY_BASE_HI … #define regVGT_TF_MEMORY_BASE_HI_BASE_IDX … #define regGE_GS_ORDERED_ID_BASE … #define regGE_GS_ORDERED_ID_BASE_BASE_IDX … #define regVGT_PRIMITIVEID_RESET … #define regVGT_PRIMITIVEID_RESET_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_cprs64dec // base address: 0x32000 #define regCP_MES_PRGRM_CNTR_START … #define regCP_MES_PRGRM_CNTR_START_BASE_IDX … #define regCP_MES_INTR_ROUTINE_START … #define regCP_MES_INTR_ROUTINE_START_BASE_IDX … #define regCP_MES_MTVEC_LO … #define regCP_MES_MTVEC_LO_BASE_IDX … #define regCP_MES_INTR_ROUTINE_START_HI … #define regCP_MES_INTR_ROUTINE_START_HI_BASE_IDX … #define regCP_MES_MTVEC_HI … #define regCP_MES_MTVEC_HI_BASE_IDX … #define regCP_MES_CNTL … #define regCP_MES_CNTL_BASE_IDX … #define regCP_MES_PIPE_PRIORITY_CNTS … #define regCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX … #define regCP_MES_PIPE0_PRIORITY … #define regCP_MES_PIPE0_PRIORITY_BASE_IDX … #define regCP_MES_PIPE1_PRIORITY … #define regCP_MES_PIPE1_PRIORITY_BASE_IDX … #define regCP_MES_PIPE2_PRIORITY … #define regCP_MES_PIPE2_PRIORITY_BASE_IDX … #define regCP_MES_PIPE3_PRIORITY … #define regCP_MES_PIPE3_PRIORITY_BASE_IDX … #define regCP_MES_HEADER_DUMP … #define regCP_MES_HEADER_DUMP_BASE_IDX … #define regCP_MES_MIE_LO … #define regCP_MES_MIE_LO_BASE_IDX … #define regCP_MES_MIE_HI … #define regCP_MES_MIE_HI_BASE_IDX … #define regCP_MES_INTERRUPT … #define regCP_MES_INTERRUPT_BASE_IDX … #define regCP_MES_SCRATCH_INDEX … #define regCP_MES_SCRATCH_INDEX_BASE_IDX … #define regCP_MES_SCRATCH_DATA … #define regCP_MES_SCRATCH_DATA_BASE_IDX … #define regCP_MES_INSTR_PNTR … #define regCP_MES_INSTR_PNTR_BASE_IDX … #define regCP_MES_MSCRATCH_HI … #define regCP_MES_MSCRATCH_HI_BASE_IDX … #define regCP_MES_MSCRATCH_LO … #define regCP_MES_MSCRATCH_LO_BASE_IDX … #define regCP_MES_MSTATUS_LO … #define regCP_MES_MSTATUS_LO_BASE_IDX … #define regCP_MES_MSTATUS_HI … #define regCP_MES_MSTATUS_HI_BASE_IDX … #define regCP_MES_MEPC_LO … #define regCP_MES_MEPC_LO_BASE_IDX … #define regCP_MES_MEPC_HI … #define regCP_MES_MEPC_HI_BASE_IDX … #define regCP_MES_MCAUSE_LO … #define regCP_MES_MCAUSE_LO_BASE_IDX … #define regCP_MES_MCAUSE_HI … #define regCP_MES_MCAUSE_HI_BASE_IDX … #define regCP_MES_MBADADDR_LO … #define regCP_MES_MBADADDR_LO_BASE_IDX … #define regCP_MES_MBADADDR_HI … #define regCP_MES_MBADADDR_HI_BASE_IDX … #define regCP_MES_MIP_LO … #define regCP_MES_MIP_LO_BASE_IDX … #define regCP_MES_MIP_HI … #define regCP_MES_MIP_HI_BASE_IDX … #define regCP_MES_IC_OP_CNTL … #define regCP_MES_IC_OP_CNTL_BASE_IDX … #define regCP_MES_MCYCLE_LO … #define regCP_MES_MCYCLE_LO_BASE_IDX … #define regCP_MES_MCYCLE_HI … #define regCP_MES_MCYCLE_HI_BASE_IDX … #define regCP_MES_MTIME_LO … #define regCP_MES_MTIME_LO_BASE_IDX … #define regCP_MES_MTIME_HI … #define regCP_MES_MTIME_HI_BASE_IDX … #define regCP_MES_MINSTRET_LO … #define regCP_MES_MINSTRET_LO_BASE_IDX … #define regCP_MES_MINSTRET_HI … #define regCP_MES_MINSTRET_HI_BASE_IDX … #define regCP_MES_MISA_LO … #define regCP_MES_MISA_LO_BASE_IDX … #define regCP_MES_MISA_HI … #define regCP_MES_MISA_HI_BASE_IDX … #define regCP_MES_MVENDORID_LO … #define regCP_MES_MVENDORID_LO_BASE_IDX … #define regCP_MES_MVENDORID_HI … #define regCP_MES_MVENDORID_HI_BASE_IDX … #define regCP_MES_MARCHID_LO … #define regCP_MES_MARCHID_LO_BASE_IDX … #define regCP_MES_MARCHID_HI … #define regCP_MES_MARCHID_HI_BASE_IDX … #define regCP_MES_MIMPID_LO … #define regCP_MES_MIMPID_LO_BASE_IDX … #define regCP_MES_MIMPID_HI … #define regCP_MES_MIMPID_HI_BASE_IDX … #define regCP_MES_MHARTID_LO … #define regCP_MES_MHARTID_LO_BASE_IDX … #define regCP_MES_MHARTID_HI … #define regCP_MES_MHARTID_HI_BASE_IDX … #define regCP_MES_DC_BASE_CNTL … #define regCP_MES_DC_BASE_CNTL_BASE_IDX … #define regCP_MES_DC_OP_CNTL … #define regCP_MES_DC_OP_CNTL_BASE_IDX … #define regCP_MES_MTIMECMP_LO … #define regCP_MES_MTIMECMP_LO_BASE_IDX … #define regCP_MES_MTIMECMP_HI … #define regCP_MES_MTIMECMP_HI_BASE_IDX … #define regCP_MES_PROCESS_QUANTUM_PIPE0 … #define regCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX … #define regCP_MES_PROCESS_QUANTUM_PIPE1 … #define regCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX … #define regCP_MES_DOORBELL_CONTROL1 … #define regCP_MES_DOORBELL_CONTROL1_BASE_IDX … #define regCP_MES_DOORBELL_CONTROL2 … #define regCP_MES_DOORBELL_CONTROL2_BASE_IDX … #define regCP_MES_DOORBELL_CONTROL3 … #define regCP_MES_DOORBELL_CONTROL3_BASE_IDX … #define regCP_MES_DOORBELL_CONTROL4 … #define regCP_MES_DOORBELL_CONTROL4_BASE_IDX … #define regCP_MES_DOORBELL_CONTROL5 … #define regCP_MES_DOORBELL_CONTROL5_BASE_IDX … #define regCP_MES_DOORBELL_CONTROL6 … #define regCP_MES_DOORBELL_CONTROL6_BASE_IDX … #define regCP_MES_GP0_LO … #define regCP_MES_GP0_LO_BASE_IDX … #define regCP_MES_GP0_HI … #define regCP_MES_GP0_HI_BASE_IDX … #define regCP_MES_GP1_LO … #define regCP_MES_GP1_LO_BASE_IDX … #define regCP_MES_GP1_HI … #define regCP_MES_GP1_HI_BASE_IDX … #define regCP_MES_GP2_LO … #define regCP_MES_GP2_LO_BASE_IDX … #define regCP_MES_GP2_HI … #define regCP_MES_GP2_HI_BASE_IDX … #define regCP_MES_GP3_LO … #define regCP_MES_GP3_LO_BASE_IDX … #define regCP_MES_GP3_HI … #define regCP_MES_GP3_HI_BASE_IDX … #define regCP_MES_GP4_LO … #define regCP_MES_GP4_LO_BASE_IDX … #define regCP_MES_GP4_HI … #define regCP_MES_GP4_HI_BASE_IDX … #define regCP_MES_GP5_LO … #define regCP_MES_GP5_LO_BASE_IDX … #define regCP_MES_GP5_HI … #define regCP_MES_GP5_HI_BASE_IDX … #define regCP_MES_GP6_LO … #define regCP_MES_GP6_LO_BASE_IDX … #define regCP_MES_GP6_HI … #define regCP_MES_GP6_HI_BASE_IDX … #define regCP_MES_GP7_LO … #define regCP_MES_GP7_LO_BASE_IDX … #define regCP_MES_GP7_HI … #define regCP_MES_GP7_HI_BASE_IDX … #define regCP_MES_GP8_LO … #define regCP_MES_GP8_LO_BASE_IDX … #define regCP_MES_GP8_HI … #define regCP_MES_GP8_HI_BASE_IDX … #define regCP_MES_GP9_LO … #define regCP_MES_GP9_LO_BASE_IDX … #define regCP_MES_GP9_HI … #define regCP_MES_GP9_HI_BASE_IDX … #define regCP_MES_LOCAL_BASE0_LO … #define regCP_MES_LOCAL_BASE0_LO_BASE_IDX … #define regCP_MES_LOCAL_BASE0_HI … #define regCP_MES_LOCAL_BASE0_HI_BASE_IDX … #define regCP_MES_LOCAL_MASK0_LO … #define regCP_MES_LOCAL_MASK0_LO_BASE_IDX … #define regCP_MES_LOCAL_MASK0_HI … #define regCP_MES_LOCAL_MASK0_HI_BASE_IDX … #define regCP_MES_LOCAL_APERTURE … #define regCP_MES_LOCAL_APERTURE_BASE_IDX … #define regCP_MES_LOCAL_INSTR_BASE_LO … #define regCP_MES_LOCAL_INSTR_BASE_LO_BASE_IDX … #define regCP_MES_LOCAL_INSTR_BASE_HI … #define regCP_MES_LOCAL_INSTR_BASE_HI_BASE_IDX … #define regCP_MES_LOCAL_INSTR_MASK_LO … #define regCP_MES_LOCAL_INSTR_MASK_LO_BASE_IDX … #define regCP_MES_LOCAL_INSTR_MASK_HI … #define regCP_MES_LOCAL_INSTR_MASK_HI_BASE_IDX … #define regCP_MES_LOCAL_INSTR_APERTURE … #define regCP_MES_LOCAL_INSTR_APERTURE_BASE_IDX … #define regCP_MES_LOCAL_SCRATCH_APERTURE … #define regCP_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX … #define regCP_MES_LOCAL_SCRATCH_BASE_LO … #define regCP_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX … #define regCP_MES_LOCAL_SCRATCH_BASE_HI … #define regCP_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX … #define regCP_MES_PERFCOUNT_CNTL … #define regCP_MES_PERFCOUNT_CNTL_BASE_IDX … #define regCP_MES_PENDING_INTERRUPT … #define regCP_MES_PENDING_INTERRUPT_BASE_IDX … #define regCP_MES_RS64_EXCEPTION_STATUS … #define regCP_MES_RS64_EXCEPTION_STATUS_BASE_IDX … #define regCP_MES_PRGRM_CNTR_START_HI … #define regCP_MES_PRGRM_CNTR_START_HI_BASE_IDX … #define regCP_MES_INTERRUPT_DATA_16 … #define regCP_MES_INTERRUPT_DATA_16_BASE_IDX … #define regCP_MES_INTERRUPT_DATA_17 … #define regCP_MES_INTERRUPT_DATA_17_BASE_IDX … #define regCP_MES_INTERRUPT_DATA_18 … #define regCP_MES_INTERRUPT_DATA_18_BASE_IDX … #define regCP_MES_INTERRUPT_DATA_19 … #define regCP_MES_INTERRUPT_DATA_19_BASE_IDX … #define regCP_MES_INTERRUPT_DATA_20 … #define regCP_MES_INTERRUPT_DATA_20_BASE_IDX … #define regCP_MES_INTERRUPT_DATA_21 … #define regCP_MES_INTERRUPT_DATA_21_BASE_IDX … #define regCP_MES_INTERRUPT_DATA_22 … #define regCP_MES_INTERRUPT_DATA_22_BASE_IDX … #define regCP_MES_INTERRUPT_DATA_23 … #define regCP_MES_INTERRUPT_DATA_23_BASE_IDX … #define regCP_MES_INTERRUPT_DATA_24 … #define regCP_MES_INTERRUPT_DATA_24_BASE_IDX … #define regCP_MES_INTERRUPT_DATA_25 … #define regCP_MES_INTERRUPT_DATA_25_BASE_IDX … #define regCP_MES_INTERRUPT_DATA_26 … #define regCP_MES_INTERRUPT_DATA_26_BASE_IDX … #define regCP_MES_INTERRUPT_DATA_27 … #define regCP_MES_INTERRUPT_DATA_27_BASE_IDX … #define regCP_MES_INTERRUPT_DATA_28 … #define regCP_MES_INTERRUPT_DATA_28_BASE_IDX … #define regCP_MES_INTERRUPT_DATA_29 … #define regCP_MES_INTERRUPT_DATA_29_BASE_IDX … #define regCP_MES_INTERRUPT_DATA_30 … #define regCP_MES_INTERRUPT_DATA_30_BASE_IDX … #define regCP_MES_INTERRUPT_DATA_31 … #define regCP_MES_INTERRUPT_DATA_31_BASE_IDX … #define regCP_MES_DC_APERTURE0_BASE … #define regCP_MES_DC_APERTURE0_BASE_BASE_IDX … #define regCP_MES_DC_APERTURE0_MASK … #define regCP_MES_DC_APERTURE0_MASK_BASE_IDX … #define regCP_MES_DC_APERTURE0_CNTL … #define regCP_MES_DC_APERTURE0_CNTL_BASE_IDX … #define regCP_MES_DC_APERTURE1_BASE … #define regCP_MES_DC_APERTURE1_BASE_BASE_IDX … #define regCP_MES_DC_APERTURE1_MASK … #define regCP_MES_DC_APERTURE1_MASK_BASE_IDX … #define regCP_MES_DC_APERTURE1_CNTL … #define regCP_MES_DC_APERTURE1_CNTL_BASE_IDX … #define regCP_MES_DC_APERTURE2_BASE … #define regCP_MES_DC_APERTURE2_BASE_BASE_IDX … #define regCP_MES_DC_APERTURE2_MASK … #define regCP_MES_DC_APERTURE2_MASK_BASE_IDX … #define regCP_MES_DC_APERTURE2_CNTL … #define regCP_MES_DC_APERTURE2_CNTL_BASE_IDX … #define regCP_MES_DC_APERTURE3_BASE … #define regCP_MES_DC_APERTURE3_BASE_BASE_IDX … #define regCP_MES_DC_APERTURE3_MASK … #define regCP_MES_DC_APERTURE3_MASK_BASE_IDX … #define regCP_MES_DC_APERTURE3_CNTL … #define regCP_MES_DC_APERTURE3_CNTL_BASE_IDX … #define regCP_MES_DC_APERTURE4_BASE … #define regCP_MES_DC_APERTURE4_BASE_BASE_IDX … #define regCP_MES_DC_APERTURE4_MASK … #define regCP_MES_DC_APERTURE4_MASK_BASE_IDX … #define regCP_MES_DC_APERTURE4_CNTL … #define regCP_MES_DC_APERTURE4_CNTL_BASE_IDX … #define regCP_MES_DC_APERTURE5_BASE … #define regCP_MES_DC_APERTURE5_BASE_BASE_IDX … #define regCP_MES_DC_APERTURE5_MASK … #define regCP_MES_DC_APERTURE5_MASK_BASE_IDX … #define regCP_MES_DC_APERTURE5_CNTL … #define regCP_MES_DC_APERTURE5_CNTL_BASE_IDX … #define regCP_MES_DC_APERTURE6_BASE … #define regCP_MES_DC_APERTURE6_BASE_BASE_IDX … #define regCP_MES_DC_APERTURE6_MASK … #define regCP_MES_DC_APERTURE6_MASK_BASE_IDX … #define regCP_MES_DC_APERTURE6_CNTL … #define regCP_MES_DC_APERTURE6_CNTL_BASE_IDX … #define regCP_MES_DC_APERTURE7_BASE … #define regCP_MES_DC_APERTURE7_BASE_BASE_IDX … #define regCP_MES_DC_APERTURE7_MASK … #define regCP_MES_DC_APERTURE7_MASK_BASE_IDX … #define regCP_MES_DC_APERTURE7_CNTL … #define regCP_MES_DC_APERTURE7_CNTL_BASE_IDX … #define regCP_MES_DC_APERTURE8_BASE … #define regCP_MES_DC_APERTURE8_BASE_BASE_IDX … #define regCP_MES_DC_APERTURE8_MASK … #define regCP_MES_DC_APERTURE8_MASK_BASE_IDX … #define regCP_MES_DC_APERTURE8_CNTL … #define regCP_MES_DC_APERTURE8_CNTL_BASE_IDX … #define regCP_MES_DC_APERTURE9_BASE … #define regCP_MES_DC_APERTURE9_BASE_BASE_IDX … #define regCP_MES_DC_APERTURE9_MASK … #define regCP_MES_DC_APERTURE9_MASK_BASE_IDX … #define regCP_MES_DC_APERTURE9_CNTL … #define regCP_MES_DC_APERTURE9_CNTL_BASE_IDX … #define regCP_MES_DC_APERTURE10_BASE … #define regCP_MES_DC_APERTURE10_BASE_BASE_IDX … #define regCP_MES_DC_APERTURE10_MASK … #define regCP_MES_DC_APERTURE10_MASK_BASE_IDX … #define regCP_MES_DC_APERTURE10_CNTL … #define regCP_MES_DC_APERTURE10_CNTL_BASE_IDX … #define regCP_MES_DC_APERTURE11_BASE … #define regCP_MES_DC_APERTURE11_BASE_BASE_IDX … #define regCP_MES_DC_APERTURE11_MASK … #define regCP_MES_DC_APERTURE11_MASK_BASE_IDX … #define regCP_MES_DC_APERTURE11_CNTL … #define regCP_MES_DC_APERTURE11_CNTL_BASE_IDX … #define regCP_MES_DC_APERTURE12_BASE … #define regCP_MES_DC_APERTURE12_BASE_BASE_IDX … #define regCP_MES_DC_APERTURE12_MASK … #define regCP_MES_DC_APERTURE12_MASK_BASE_IDX … #define regCP_MES_DC_APERTURE12_CNTL … #define regCP_MES_DC_APERTURE12_CNTL_BASE_IDX … #define regCP_MES_DC_APERTURE13_BASE … #define regCP_MES_DC_APERTURE13_BASE_BASE_IDX … #define regCP_MES_DC_APERTURE13_MASK … #define regCP_MES_DC_APERTURE13_MASK_BASE_IDX … #define regCP_MES_DC_APERTURE13_CNTL … #define regCP_MES_DC_APERTURE13_CNTL_BASE_IDX … #define regCP_MES_DC_APERTURE14_BASE … #define regCP_MES_DC_APERTURE14_BASE_BASE_IDX … #define regCP_MES_DC_APERTURE14_MASK … #define regCP_MES_DC_APERTURE14_MASK_BASE_IDX … #define regCP_MES_DC_APERTURE14_CNTL … #define regCP_MES_DC_APERTURE14_CNTL_BASE_IDX … #define regCP_MES_DC_APERTURE15_BASE … #define regCP_MES_DC_APERTURE15_BASE_BASE_IDX … #define regCP_MES_DC_APERTURE15_MASK … #define regCP_MES_DC_APERTURE15_MASK_BASE_IDX … #define regCP_MES_DC_APERTURE15_CNTL … #define regCP_MES_DC_APERTURE15_CNTL_BASE_IDX … #define regCP_MES_METADATA_CNTL … #define regCP_MES_METADATA_CNTL_BASE_IDX … #define regCP_MEC_RS64_PRGRM_CNTR_START … #define regCP_MEC_RS64_PRGRM_CNTR_START_BASE_IDX … #define regCP_MEC_MTVEC_LO … #define regCP_MEC_MTVEC_LO_BASE_IDX … #define regCP_MEC_MTVEC_HI … #define regCP_MEC_MTVEC_HI_BASE_IDX … #define regCP_MEC_RS64_CNTL … #define regCP_MEC_RS64_CNTL_BASE_IDX … #define regCP_MEC_MIE_LO … #define regCP_MEC_MIE_LO_BASE_IDX … #define regCP_MEC_MIE_HI … #define regCP_MEC_MIE_HI_BASE_IDX … #define regCP_MEC_RS64_INTERRUPT … #define regCP_MEC_RS64_INTERRUPT_BASE_IDX … #define regCP_MEC_RS64_INSTR_PNTR … #define regCP_MEC_RS64_INSTR_PNTR_BASE_IDX … #define regCP_MEC_MIP_LO … #define regCP_MEC_MIP_LO_BASE_IDX … #define regCP_MEC_MIP_HI … #define regCP_MEC_MIP_HI_BASE_IDX … #define regCP_MEC_DC_BASE_CNTL … #define regCP_MEC_DC_BASE_CNTL_BASE_IDX … #define regCP_MEC_DC_OP_CNTL … #define regCP_MEC_DC_OP_CNTL_BASE_IDX … #define regCP_MEC_MTIMECMP_LO … #define regCP_MEC_MTIMECMP_LO_BASE_IDX … #define regCP_MEC_MTIMECMP_HI … #define regCP_MEC_MTIMECMP_HI_BASE_IDX … #define regCP_MEC_GP0_LO … #define regCP_MEC_GP0_LO_BASE_IDX … #define regCP_MEC_GP0_HI … #define regCP_MEC_GP0_HI_BASE_IDX … #define regCP_MEC_GP1_LO … #define regCP_MEC_GP1_LO_BASE_IDX … #define regCP_MEC_GP1_HI … #define regCP_MEC_GP1_HI_BASE_IDX … #define regCP_MEC_GP2_LO … #define regCP_MEC_GP2_LO_BASE_IDX … #define regCP_MEC_GP2_HI … #define regCP_MEC_GP2_HI_BASE_IDX … #define regCP_MEC_GP3_LO … #define regCP_MEC_GP3_LO_BASE_IDX … #define regCP_MEC_GP3_HI … #define regCP_MEC_GP3_HI_BASE_IDX … #define regCP_MEC_GP4_LO … #define regCP_MEC_GP4_LO_BASE_IDX … #define regCP_MEC_GP4_HI … #define regCP_MEC_GP4_HI_BASE_IDX … #define regCP_MEC_GP5_LO … #define regCP_MEC_GP5_LO_BASE_IDX … #define regCP_MEC_GP5_HI … #define regCP_MEC_GP5_HI_BASE_IDX … #define regCP_MEC_GP6_LO … #define regCP_MEC_GP6_LO_BASE_IDX … #define regCP_MEC_GP6_HI … #define regCP_MEC_GP6_HI_BASE_IDX … #define regCP_MEC_GP7_LO … #define regCP_MEC_GP7_LO_BASE_IDX … #define regCP_MEC_GP7_HI … #define regCP_MEC_GP7_HI_BASE_IDX … #define regCP_MEC_GP8_LO … #define regCP_MEC_GP8_LO_BASE_IDX … #define regCP_MEC_GP8_HI … #define regCP_MEC_GP8_HI_BASE_IDX … #define regCP_MEC_GP9_LO … #define regCP_MEC_GP9_LO_BASE_IDX … #define regCP_MEC_GP9_HI … #define regCP_MEC_GP9_HI_BASE_IDX … #define regCP_MEC_LOCAL_BASE0_LO … #define regCP_MEC_LOCAL_BASE0_LO_BASE_IDX … #define regCP_MEC_LOCAL_BASE0_HI … #define regCP_MEC_LOCAL_BASE0_HI_BASE_IDX … #define regCP_MEC_LOCAL_MASK0_LO … #define regCP_MEC_LOCAL_MASK0_LO_BASE_IDX … #define regCP_MEC_LOCAL_MASK0_HI … #define regCP_MEC_LOCAL_MASK0_HI_BASE_IDX … #define regCP_MEC_LOCAL_APERTURE … #define regCP_MEC_LOCAL_APERTURE_BASE_IDX … #define regCP_MEC_LOCAL_INSTR_BASE_LO … #define regCP_MEC_LOCAL_INSTR_BASE_LO_BASE_IDX … #define regCP_MEC_LOCAL_INSTR_BASE_HI … #define regCP_MEC_LOCAL_INSTR_BASE_HI_BASE_IDX … #define regCP_MEC_LOCAL_INSTR_MASK_LO … #define regCP_MEC_LOCAL_INSTR_MASK_LO_BASE_IDX … #define regCP_MEC_LOCAL_INSTR_MASK_HI … #define regCP_MEC_LOCAL_INSTR_MASK_HI_BASE_IDX … #define regCP_MEC_LOCAL_INSTR_APERTURE … #define regCP_MEC_LOCAL_INSTR_APERTURE_BASE_IDX … #define regCP_MEC_LOCAL_SCRATCH_APERTURE … #define regCP_MEC_LOCAL_SCRATCH_APERTURE_BASE_IDX … #define regCP_MEC_LOCAL_SCRATCH_BASE_LO … #define regCP_MEC_LOCAL_SCRATCH_BASE_LO_BASE_IDX … #define regCP_MEC_LOCAL_SCRATCH_BASE_HI … #define regCP_MEC_LOCAL_SCRATCH_BASE_HI_BASE_IDX … #define regCP_MEC_RS64_PERFCOUNT_CNTL … #define regCP_MEC_RS64_PERFCOUNT_CNTL_BASE_IDX … #define regCP_MEC_RS64_PENDING_INTERRUPT … #define regCP_MEC_RS64_PENDING_INTERRUPT_BASE_IDX … #define regCP_MEC_RS64_EXCEPTION_STATUS … #define regCP_MEC_RS64_EXCEPTION_STATUS_BASE_IDX … #define regCP_MEC_RS64_PRGRM_CNTR_START_HI … #define regCP_MEC_RS64_PRGRM_CNTR_START_HI_BASE_IDX … #define regCP_MEC_RS64_INTERRUPT_DATA_16 … #define regCP_MEC_RS64_INTERRUPT_DATA_16_BASE_IDX … #define regCP_MEC_RS64_INTERRUPT_DATA_17 … #define regCP_MEC_RS64_INTERRUPT_DATA_17_BASE_IDX … #define regCP_MEC_RS64_INTERRUPT_DATA_18 … #define regCP_MEC_RS64_INTERRUPT_DATA_18_BASE_IDX … #define regCP_MEC_RS64_INTERRUPT_DATA_19 … #define regCP_MEC_RS64_INTERRUPT_DATA_19_BASE_IDX … #define regCP_MEC_RS64_INTERRUPT_DATA_20 … #define regCP_MEC_RS64_INTERRUPT_DATA_20_BASE_IDX … #define regCP_MEC_RS64_INTERRUPT_DATA_21 … #define regCP_MEC_RS64_INTERRUPT_DATA_21_BASE_IDX … #define regCP_MEC_RS64_INTERRUPT_DATA_22 … #define regCP_MEC_RS64_INTERRUPT_DATA_22_BASE_IDX … #define regCP_MEC_RS64_INTERRUPT_DATA_23 … #define regCP_MEC_RS64_INTERRUPT_DATA_23_BASE_IDX … #define regCP_MEC_RS64_INTERRUPT_DATA_24 … #define regCP_MEC_RS64_INTERRUPT_DATA_24_BASE_IDX … #define regCP_MEC_RS64_INTERRUPT_DATA_25 … #define regCP_MEC_RS64_INTERRUPT_DATA_25_BASE_IDX … #define regCP_MEC_RS64_INTERRUPT_DATA_26 … #define regCP_MEC_RS64_INTERRUPT_DATA_26_BASE_IDX … #define regCP_MEC_RS64_INTERRUPT_DATA_27 … #define regCP_MEC_RS64_INTERRUPT_DATA_27_BASE_IDX … #define regCP_MEC_RS64_INTERRUPT_DATA_28 … #define regCP_MEC_RS64_INTERRUPT_DATA_28_BASE_IDX … #define regCP_MEC_RS64_INTERRUPT_DATA_29 … #define regCP_MEC_RS64_INTERRUPT_DATA_29_BASE_IDX … #define regCP_MEC_RS64_INTERRUPT_DATA_30 … #define regCP_MEC_RS64_INTERRUPT_DATA_30_BASE_IDX … #define regCP_MEC_RS64_INTERRUPT_DATA_31 … #define regCP_MEC_RS64_INTERRUPT_DATA_31_BASE_IDX … #define regCP_MEC_DC_APERTURE0_BASE … #define regCP_MEC_DC_APERTURE0_BASE_BASE_IDX … #define regCP_MEC_DC_APERTURE0_MASK … #define regCP_MEC_DC_APERTURE0_MASK_BASE_IDX … #define regCP_MEC_DC_APERTURE0_CNTL … #define regCP_MEC_DC_APERTURE0_CNTL_BASE_IDX … #define regCP_MEC_DC_APERTURE1_BASE … #define regCP_MEC_DC_APERTURE1_BASE_BASE_IDX … #define regCP_MEC_DC_APERTURE1_MASK … #define regCP_MEC_DC_APERTURE1_MASK_BASE_IDX … #define regCP_MEC_DC_APERTURE1_CNTL … #define regCP_MEC_DC_APERTURE1_CNTL_BASE_IDX … #define regCP_MEC_DC_APERTURE2_BASE … #define regCP_MEC_DC_APERTURE2_BASE_BASE_IDX … #define regCP_MEC_DC_APERTURE2_MASK … #define regCP_MEC_DC_APERTURE2_MASK_BASE_IDX … #define regCP_MEC_DC_APERTURE2_CNTL … #define regCP_MEC_DC_APERTURE2_CNTL_BASE_IDX … #define regCP_MEC_DC_APERTURE3_BASE … #define regCP_MEC_DC_APERTURE3_BASE_BASE_IDX … #define regCP_MEC_DC_APERTURE3_MASK … #define regCP_MEC_DC_APERTURE3_MASK_BASE_IDX … #define regCP_MEC_DC_APERTURE3_CNTL … #define regCP_MEC_DC_APERTURE3_CNTL_BASE_IDX … #define regCP_MEC_DC_APERTURE4_BASE … #define regCP_MEC_DC_APERTURE4_BASE_BASE_IDX … #define regCP_MEC_DC_APERTURE4_MASK … #define regCP_MEC_DC_APERTURE4_MASK_BASE_IDX … #define regCP_MEC_DC_APERTURE4_CNTL … #define regCP_MEC_DC_APERTURE4_CNTL_BASE_IDX … #define regCP_MEC_DC_APERTURE5_BASE … #define regCP_MEC_DC_APERTURE5_BASE_BASE_IDX … #define regCP_MEC_DC_APERTURE5_MASK … #define regCP_MEC_DC_APERTURE5_MASK_BASE_IDX … #define regCP_MEC_DC_APERTURE5_CNTL … #define regCP_MEC_DC_APERTURE5_CNTL_BASE_IDX … #define regCP_MEC_DC_APERTURE6_BASE … #define regCP_MEC_DC_APERTURE6_BASE_BASE_IDX … #define regCP_MEC_DC_APERTURE6_MASK … #define regCP_MEC_DC_APERTURE6_MASK_BASE_IDX … #define regCP_MEC_DC_APERTURE6_CNTL … #define regCP_MEC_DC_APERTURE6_CNTL_BASE_IDX … #define regCP_MEC_DC_APERTURE7_BASE … #define regCP_MEC_DC_APERTURE7_BASE_BASE_IDX … #define regCP_MEC_DC_APERTURE7_MASK … #define regCP_MEC_DC_APERTURE7_MASK_BASE_IDX … #define regCP_MEC_DC_APERTURE7_CNTL … #define regCP_MEC_DC_APERTURE7_CNTL_BASE_IDX … #define regCP_MEC_DC_APERTURE8_BASE … #define regCP_MEC_DC_APERTURE8_BASE_BASE_IDX … #define regCP_MEC_DC_APERTURE8_MASK … #define regCP_MEC_DC_APERTURE8_MASK_BASE_IDX … #define regCP_MEC_DC_APERTURE8_CNTL … #define regCP_MEC_DC_APERTURE8_CNTL_BASE_IDX … #define regCP_MEC_DC_APERTURE9_BASE … #define regCP_MEC_DC_APERTURE9_BASE_BASE_IDX … #define regCP_MEC_DC_APERTURE9_MASK … #define regCP_MEC_DC_APERTURE9_MASK_BASE_IDX … #define regCP_MEC_DC_APERTURE9_CNTL … #define regCP_MEC_DC_APERTURE9_CNTL_BASE_IDX … #define regCP_MEC_DC_APERTURE10_BASE … #define regCP_MEC_DC_APERTURE10_BASE_BASE_IDX … #define regCP_MEC_DC_APERTURE10_MASK … #define regCP_MEC_DC_APERTURE10_MASK_BASE_IDX … #define regCP_MEC_DC_APERTURE10_CNTL … #define regCP_MEC_DC_APERTURE10_CNTL_BASE_IDX … #define regCP_MEC_DC_APERTURE11_BASE … #define regCP_MEC_DC_APERTURE11_BASE_BASE_IDX … #define regCP_MEC_DC_APERTURE11_MASK … #define regCP_MEC_DC_APERTURE11_MASK_BASE_IDX … #define regCP_MEC_DC_APERTURE11_CNTL … #define regCP_MEC_DC_APERTURE11_CNTL_BASE_IDX … #define regCP_MEC_DC_APERTURE12_BASE … #define regCP_MEC_DC_APERTURE12_BASE_BASE_IDX … #define regCP_MEC_DC_APERTURE12_MASK … #define regCP_MEC_DC_APERTURE12_MASK_BASE_IDX … #define regCP_MEC_DC_APERTURE12_CNTL … #define regCP_MEC_DC_APERTURE12_CNTL_BASE_IDX … #define regCP_MEC_DC_APERTURE13_BASE … #define regCP_MEC_DC_APERTURE13_BASE_BASE_IDX … #define regCP_MEC_DC_APERTURE13_MASK … #define regCP_MEC_DC_APERTURE13_MASK_BASE_IDX … #define regCP_MEC_DC_APERTURE13_CNTL … #define regCP_MEC_DC_APERTURE13_CNTL_BASE_IDX … #define regCP_MEC_DC_APERTURE14_BASE … #define regCP_MEC_DC_APERTURE14_BASE_BASE_IDX … #define regCP_MEC_DC_APERTURE14_MASK … #define regCP_MEC_DC_APERTURE14_MASK_BASE_IDX … #define regCP_MEC_DC_APERTURE14_CNTL … #define regCP_MEC_DC_APERTURE14_CNTL_BASE_IDX … #define regCP_MEC_DC_APERTURE15_BASE … #define regCP_MEC_DC_APERTURE15_BASE_BASE_IDX … #define regCP_MEC_DC_APERTURE15_MASK … #define regCP_MEC_DC_APERTURE15_MASK_BASE_IDX … #define regCP_MEC_DC_APERTURE15_CNTL … #define regCP_MEC_DC_APERTURE15_CNTL_BASE_IDX … #define regCP_CPC_IC_OP_CNTL … #define regCP_CPC_IC_OP_CNTL_BASE_IDX … #define regCP_GFX_RS64_INTERRUPT0 … #define regCP_GFX_RS64_INTERRUPT0_BASE_IDX … #define regCP_GFX_RS64_INTR_EN0 … #define regCP_GFX_RS64_INTR_EN0_BASE_IDX … #define regCP_GFX_RS64_INTR_EN1 … #define regCP_GFX_RS64_INTR_EN1_BASE_IDX … #define regCP_GFX_RS64_DC_BASE_CNTL … #define regCP_GFX_RS64_DC_BASE_CNTL_BASE_IDX … #define regCP_GFX_RS64_DC_OP_CNTL … #define regCP_GFX_RS64_DC_OP_CNTL_BASE_IDX … #define regCP_GFX_RS64_LOCAL_BASE0_LO … #define regCP_GFX_RS64_LOCAL_BASE0_LO_BASE_IDX … #define regCP_GFX_RS64_LOCAL_BASE0_HI … #define regCP_GFX_RS64_LOCAL_BASE0_HI_BASE_IDX … #define regCP_GFX_RS64_LOCAL_MASK0_LO … #define regCP_GFX_RS64_LOCAL_MASK0_LO_BASE_IDX … #define regCP_GFX_RS64_LOCAL_MASK0_HI … #define regCP_GFX_RS64_LOCAL_MASK0_HI_BASE_IDX … #define regCP_GFX_RS64_LOCAL_APERTURE … #define regCP_GFX_RS64_LOCAL_APERTURE_BASE_IDX … #define regCP_GFX_RS64_LOCAL_INSTR_BASE_LO … #define regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_BASE_IDX … #define regCP_GFX_RS64_LOCAL_INSTR_BASE_HI … #define regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_BASE_IDX … #define regCP_GFX_RS64_LOCAL_INSTR_MASK_LO … #define regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_BASE_IDX … #define regCP_GFX_RS64_LOCAL_INSTR_MASK_HI … #define regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_BASE_IDX … #define regCP_GFX_RS64_LOCAL_INSTR_APERTURE … #define regCP_GFX_RS64_LOCAL_INSTR_APERTURE_BASE_IDX … #define regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE … #define regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_BASE_IDX … #define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO … #define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_BASE_IDX … #define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI … #define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_BASE_IDX … #define regCP_PFP_RS64_EXCEPTION_STATUS … #define regCP_PFP_RS64_EXCEPTION_STATUS_BASE_IDX … #define regCP_GFX_RS64_PERFCOUNT_CNTL0 … #define regCP_GFX_RS64_PERFCOUNT_CNTL0_BASE_IDX … #define regCP_GFX_RS64_PERFCOUNT_CNTL1 … #define regCP_GFX_RS64_PERFCOUNT_CNTL1_BASE_IDX … #define regCP_GFX_RS64_MIP_LO0 … #define regCP_GFX_RS64_MIP_LO0_BASE_IDX … #define regCP_GFX_RS64_MIP_LO1 … #define regCP_GFX_RS64_MIP_LO1_BASE_IDX … #define regCP_GFX_RS64_MIP_HI0 … #define regCP_GFX_RS64_MIP_HI0_BASE_IDX … #define regCP_GFX_RS64_MIP_HI1 … #define regCP_GFX_RS64_MIP_HI1_BASE_IDX … #define regCP_GFX_RS64_MTIMECMP_LO0 … #define regCP_GFX_RS64_MTIMECMP_LO0_BASE_IDX … #define regCP_GFX_RS64_MTIMECMP_LO1 … #define regCP_GFX_RS64_MTIMECMP_LO1_BASE_IDX … #define regCP_GFX_RS64_MTIMECMP_HI0 … #define regCP_GFX_RS64_MTIMECMP_HI0_BASE_IDX … #define regCP_GFX_RS64_MTIMECMP_HI1 … #define regCP_GFX_RS64_MTIMECMP_HI1_BASE_IDX … #define regCP_GFX_RS64_GP0_LO0 … #define regCP_GFX_RS64_GP0_LO0_BASE_IDX … #define regCP_GFX_RS64_GP0_LO1 … #define regCP_GFX_RS64_GP0_LO1_BASE_IDX … #define regCP_GFX_RS64_GP0_HI0 … #define regCP_GFX_RS64_GP0_HI0_BASE_IDX … #define regCP_GFX_RS64_GP0_HI1 … #define regCP_GFX_RS64_GP0_HI1_BASE_IDX … #define regCP_GFX_RS64_GP1_LO0 … #define regCP_GFX_RS64_GP1_LO0_BASE_IDX … #define regCP_GFX_RS64_GP1_LO1 … #define regCP_GFX_RS64_GP1_LO1_BASE_IDX … #define regCP_GFX_RS64_GP1_HI0 … #define regCP_GFX_RS64_GP1_HI0_BASE_IDX … #define regCP_GFX_RS64_GP1_HI1 … #define regCP_GFX_RS64_GP1_HI1_BASE_IDX … #define regCP_GFX_RS64_GP2_LO0 … #define regCP_GFX_RS64_GP2_LO0_BASE_IDX … #define regCP_GFX_RS64_GP2_LO1 … #define regCP_GFX_RS64_GP2_LO1_BASE_IDX … #define regCP_GFX_RS64_GP2_HI0 … #define regCP_GFX_RS64_GP2_HI0_BASE_IDX … #define regCP_GFX_RS64_GP2_HI1 … #define regCP_GFX_RS64_GP2_HI1_BASE_IDX … #define regCP_GFX_RS64_GP3_LO0 … #define regCP_GFX_RS64_GP3_LO0_BASE_IDX … #define regCP_GFX_RS64_GP3_LO1 … #define regCP_GFX_RS64_GP3_LO1_BASE_IDX … #define regCP_GFX_RS64_GP3_HI0 … #define regCP_GFX_RS64_GP3_HI0_BASE_IDX … #define regCP_GFX_RS64_GP3_HI1 … #define regCP_GFX_RS64_GP3_HI1_BASE_IDX … #define regCP_GFX_RS64_GP4_LO0 … #define regCP_GFX_RS64_GP4_LO0_BASE_IDX … #define regCP_GFX_RS64_GP4_LO1 … #define regCP_GFX_RS64_GP4_LO1_BASE_IDX … #define regCP_GFX_RS64_GP4_HI0 … #define regCP_GFX_RS64_GP4_HI0_BASE_IDX … #define regCP_GFX_RS64_GP4_HI1 … #define regCP_GFX_RS64_GP4_HI1_BASE_IDX … #define regCP_GFX_RS64_GP5_LO0 … #define regCP_GFX_RS64_GP5_LO0_BASE_IDX … #define regCP_GFX_RS64_GP5_LO1 … #define regCP_GFX_RS64_GP5_LO1_BASE_IDX … #define regCP_GFX_RS64_GP5_HI0 … #define regCP_GFX_RS64_GP5_HI0_BASE_IDX … #define regCP_GFX_RS64_GP5_HI1 … #define regCP_GFX_RS64_GP5_HI1_BASE_IDX … #define regCP_GFX_RS64_GP6_LO … #define regCP_GFX_RS64_GP6_LO_BASE_IDX … #define regCP_GFX_RS64_GP6_HI … #define regCP_GFX_RS64_GP6_HI_BASE_IDX … #define regCP_GFX_RS64_GP7_LO … #define regCP_GFX_RS64_GP7_LO_BASE_IDX … #define regCP_GFX_RS64_GP7_HI … #define regCP_GFX_RS64_GP7_HI_BASE_IDX … #define regCP_GFX_RS64_GP8_LO … #define regCP_GFX_RS64_GP8_LO_BASE_IDX … #define regCP_GFX_RS64_GP8_HI … #define regCP_GFX_RS64_GP8_HI_BASE_IDX … #define regCP_GFX_RS64_GP9_LO … #define regCP_GFX_RS64_GP9_LO_BASE_IDX … #define regCP_GFX_RS64_GP9_HI … #define regCP_GFX_RS64_GP9_HI_BASE_IDX … #define regCP_GFX_RS64_INSTR_PNTR0 … #define regCP_GFX_RS64_INSTR_PNTR0_BASE_IDX … #define regCP_GFX_RS64_INSTR_PNTR1 … #define regCP_GFX_RS64_INSTR_PNTR1_BASE_IDX … #define regCP_GFX_RS64_PENDING_INTERRUPT0 … #define regCP_GFX_RS64_PENDING_INTERRUPT0_BASE_IDX … #define regCP_GFX_RS64_PENDING_INTERRUPT1 … #define regCP_GFX_RS64_PENDING_INTERRUPT1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE0_BASE0 … #define regCP_GFX_RS64_DC_APERTURE0_BASE0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE0_MASK0 … #define regCP_GFX_RS64_DC_APERTURE0_MASK0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE0_CNTL0 … #define regCP_GFX_RS64_DC_APERTURE0_CNTL0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE1_BASE0 … #define regCP_GFX_RS64_DC_APERTURE1_BASE0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE1_MASK0 … #define regCP_GFX_RS64_DC_APERTURE1_MASK0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE1_CNTL0 … #define regCP_GFX_RS64_DC_APERTURE1_CNTL0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE2_BASE0 … #define regCP_GFX_RS64_DC_APERTURE2_BASE0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE2_MASK0 … #define regCP_GFX_RS64_DC_APERTURE2_MASK0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE2_CNTL0 … #define regCP_GFX_RS64_DC_APERTURE2_CNTL0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE3_BASE0 … #define regCP_GFX_RS64_DC_APERTURE3_BASE0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE3_MASK0 … #define regCP_GFX_RS64_DC_APERTURE3_MASK0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE3_CNTL0 … #define regCP_GFX_RS64_DC_APERTURE3_CNTL0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE4_BASE0 … #define regCP_GFX_RS64_DC_APERTURE4_BASE0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE4_MASK0 … #define regCP_GFX_RS64_DC_APERTURE4_MASK0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE4_CNTL0 … #define regCP_GFX_RS64_DC_APERTURE4_CNTL0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE5_BASE0 … #define regCP_GFX_RS64_DC_APERTURE5_BASE0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE5_MASK0 … #define regCP_GFX_RS64_DC_APERTURE5_MASK0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE5_CNTL0 … #define regCP_GFX_RS64_DC_APERTURE5_CNTL0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE6_BASE0 … #define regCP_GFX_RS64_DC_APERTURE6_BASE0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE6_MASK0 … #define regCP_GFX_RS64_DC_APERTURE6_MASK0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE6_CNTL0 … #define regCP_GFX_RS64_DC_APERTURE6_CNTL0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE7_BASE0 … #define regCP_GFX_RS64_DC_APERTURE7_BASE0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE7_MASK0 … #define regCP_GFX_RS64_DC_APERTURE7_MASK0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE7_CNTL0 … #define regCP_GFX_RS64_DC_APERTURE7_CNTL0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE8_BASE0 … #define regCP_GFX_RS64_DC_APERTURE8_BASE0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE8_MASK0 … #define regCP_GFX_RS64_DC_APERTURE8_MASK0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE8_CNTL0 … #define regCP_GFX_RS64_DC_APERTURE8_CNTL0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE9_BASE0 … #define regCP_GFX_RS64_DC_APERTURE9_BASE0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE9_MASK0 … #define regCP_GFX_RS64_DC_APERTURE9_MASK0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE9_CNTL0 … #define regCP_GFX_RS64_DC_APERTURE9_CNTL0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE10_BASE0 … #define regCP_GFX_RS64_DC_APERTURE10_BASE0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE10_MASK0 … #define regCP_GFX_RS64_DC_APERTURE10_MASK0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE10_CNTL0 … #define regCP_GFX_RS64_DC_APERTURE10_CNTL0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE11_BASE0 … #define regCP_GFX_RS64_DC_APERTURE11_BASE0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE11_MASK0 … #define regCP_GFX_RS64_DC_APERTURE11_MASK0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE11_CNTL0 … #define regCP_GFX_RS64_DC_APERTURE11_CNTL0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE12_BASE0 … #define regCP_GFX_RS64_DC_APERTURE12_BASE0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE12_MASK0 … #define regCP_GFX_RS64_DC_APERTURE12_MASK0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE12_CNTL0 … #define regCP_GFX_RS64_DC_APERTURE12_CNTL0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE13_BASE0 … #define regCP_GFX_RS64_DC_APERTURE13_BASE0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE13_MASK0 … #define regCP_GFX_RS64_DC_APERTURE13_MASK0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE13_CNTL0 … #define regCP_GFX_RS64_DC_APERTURE13_CNTL0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE14_BASE0 … #define regCP_GFX_RS64_DC_APERTURE14_BASE0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE14_MASK0 … #define regCP_GFX_RS64_DC_APERTURE14_MASK0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE14_CNTL0 … #define regCP_GFX_RS64_DC_APERTURE14_CNTL0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE15_BASE0 … #define regCP_GFX_RS64_DC_APERTURE15_BASE0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE15_MASK0 … #define regCP_GFX_RS64_DC_APERTURE15_MASK0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE15_CNTL0 … #define regCP_GFX_RS64_DC_APERTURE15_CNTL0_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE0_BASE1 … #define regCP_GFX_RS64_DC_APERTURE0_BASE1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE0_MASK1 … #define regCP_GFX_RS64_DC_APERTURE0_MASK1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE0_CNTL1 … #define regCP_GFX_RS64_DC_APERTURE0_CNTL1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE1_BASE1 … #define regCP_GFX_RS64_DC_APERTURE1_BASE1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE1_MASK1 … #define regCP_GFX_RS64_DC_APERTURE1_MASK1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE1_CNTL1 … #define regCP_GFX_RS64_DC_APERTURE1_CNTL1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE2_BASE1 … #define regCP_GFX_RS64_DC_APERTURE2_BASE1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE2_MASK1 … #define regCP_GFX_RS64_DC_APERTURE2_MASK1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE2_CNTL1 … #define regCP_GFX_RS64_DC_APERTURE2_CNTL1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE3_BASE1 … #define regCP_GFX_RS64_DC_APERTURE3_BASE1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE3_MASK1 … #define regCP_GFX_RS64_DC_APERTURE3_MASK1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE3_CNTL1 … #define regCP_GFX_RS64_DC_APERTURE3_CNTL1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE4_BASE1 … #define regCP_GFX_RS64_DC_APERTURE4_BASE1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE4_MASK1 … #define regCP_GFX_RS64_DC_APERTURE4_MASK1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE4_CNTL1 … #define regCP_GFX_RS64_DC_APERTURE4_CNTL1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE5_BASE1 … #define regCP_GFX_RS64_DC_APERTURE5_BASE1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE5_MASK1 … #define regCP_GFX_RS64_DC_APERTURE5_MASK1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE5_CNTL1 … #define regCP_GFX_RS64_DC_APERTURE5_CNTL1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE6_BASE1 … #define regCP_GFX_RS64_DC_APERTURE6_BASE1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE6_MASK1 … #define regCP_GFX_RS64_DC_APERTURE6_MASK1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE6_CNTL1 … #define regCP_GFX_RS64_DC_APERTURE6_CNTL1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE7_BASE1 … #define regCP_GFX_RS64_DC_APERTURE7_BASE1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE7_MASK1 … #define regCP_GFX_RS64_DC_APERTURE7_MASK1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE7_CNTL1 … #define regCP_GFX_RS64_DC_APERTURE7_CNTL1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE8_BASE1 … #define regCP_GFX_RS64_DC_APERTURE8_BASE1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE8_MASK1 … #define regCP_GFX_RS64_DC_APERTURE8_MASK1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE8_CNTL1 … #define regCP_GFX_RS64_DC_APERTURE8_CNTL1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE9_BASE1 … #define regCP_GFX_RS64_DC_APERTURE9_BASE1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE9_MASK1 … #define regCP_GFX_RS64_DC_APERTURE9_MASK1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE9_CNTL1 … #define regCP_GFX_RS64_DC_APERTURE9_CNTL1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE10_BASE1 … #define regCP_GFX_RS64_DC_APERTURE10_BASE1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE10_MASK1 … #define regCP_GFX_RS64_DC_APERTURE10_MASK1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE10_CNTL1 … #define regCP_GFX_RS64_DC_APERTURE10_CNTL1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE11_BASE1 … #define regCP_GFX_RS64_DC_APERTURE11_BASE1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE11_MASK1 … #define regCP_GFX_RS64_DC_APERTURE11_MASK1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE11_CNTL1 … #define regCP_GFX_RS64_DC_APERTURE11_CNTL1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE12_BASE1 … #define regCP_GFX_RS64_DC_APERTURE12_BASE1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE12_MASK1 … #define regCP_GFX_RS64_DC_APERTURE12_MASK1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE12_CNTL1 … #define regCP_GFX_RS64_DC_APERTURE12_CNTL1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE13_BASE1 … #define regCP_GFX_RS64_DC_APERTURE13_BASE1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE13_MASK1 … #define regCP_GFX_RS64_DC_APERTURE13_MASK1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE13_CNTL1 … #define regCP_GFX_RS64_DC_APERTURE13_CNTL1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE14_BASE1 … #define regCP_GFX_RS64_DC_APERTURE14_BASE1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE14_MASK1 … #define regCP_GFX_RS64_DC_APERTURE14_MASK1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE14_CNTL1 … #define regCP_GFX_RS64_DC_APERTURE14_CNTL1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE15_BASE1 … #define regCP_GFX_RS64_DC_APERTURE15_BASE1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE15_MASK1 … #define regCP_GFX_RS64_DC_APERTURE15_MASK1_BASE_IDX … #define regCP_GFX_RS64_DC_APERTURE15_CNTL1 … #define regCP_GFX_RS64_DC_APERTURE15_CNTL1_BASE_IDX … #define regCP_ME_RS64_EXCEPTION_STATUS … #define regCP_ME_RS64_EXCEPTION_STATUS_BASE_IDX … #define regCP_GFX_RS64_INTERRUPT1 … #define regCP_GFX_RS64_INTERRUPT1_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_chdec // base address: 0x33600 #define regCH_ARB_CTRL … #define regCH_ARB_CTRL_BASE_IDX … #define regCH_DRAM_BURST_MASK … #define regCH_DRAM_BURST_MASK_BASE_IDX … #define regCH_ARB_STATUS … #define regCH_ARB_STATUS_BASE_IDX … #define regCH_DRAM_BURST_CTRL … #define regCH_DRAM_BURST_CTRL_BASE_IDX … #define regCHA_CHC_CREDITS … #define regCHA_CHC_CREDITS_BASE_IDX … #define regCHA_CLIENT_FREE_DELAY … #define regCHA_CLIENT_FREE_DELAY_BASE_IDX … #define regCHA_COMPRESSION_MODE … #define regCHA_COMPRESSION_MODE_BASE_IDX … #define regCHA_COMPRESSOR_OVERRIDE … #define regCHA_COMPRESSOR_OVERRIDE_BASE_IDX … #define regCHI_CHR_REP_FGCG_OVERRIDE … #define regCHI_CHR_REP_FGCG_OVERRIDE_BASE_IDX … #define regCHC_CTRL … #define regCHC_CTRL_BASE_IDX … #define regCHC_STATUS … #define regCHC_STATUS_BASE_IDX … #define regCHC_CTRL2 … #define regCHC_CTRL2_BASE_IDX … #define regCHC_STATUS2 … #define regCHC_STATUS2_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_gl2dec // base address: 0x33800 #define regGL2C_CTRL … #define regGL2C_CTRL_BASE_IDX … #define regGL2C_CTRL2 … #define regGL2C_CTRL2_BASE_IDX … #define regGL2C_STATUS … #define regGL2C_STATUS_BASE_IDX … #define regGL2C_ADDR_MATCH_MASK … #define regGL2C_ADDR_MATCH_MASK_BASE_IDX … #define regGL2C_ADDR_MATCH_SIZE … #define regGL2C_ADDR_MATCH_SIZE_BASE_IDX … #define regGL2C_WBINVL2 … #define regGL2C_WBINVL2_BASE_IDX … #define regGL2C_SOFT_RESET … #define regGL2C_SOFT_RESET_BASE_IDX … #define regGL2C_CTRL3 … #define regGL2C_CTRL3_BASE_IDX … #define regGL2C_EA_CREDITS_CTRL … #define regGL2C_EA_CREDITS_CTRL_BASE_IDX … #define regGL2C_CTRL4 … #define regGL2C_CTRL4_BASE_IDX … #define regGL2C_DISCARD_STALL_CTRL … #define regGL2C_DISCARD_STALL_CTRL_BASE_IDX … #define regGL2C_CTRL5 … #define regGL2C_CTRL5_BASE_IDX … #define regGL2A_ADDR_MATCH_CTRL … #define regGL2A_ADDR_MATCH_CTRL_BASE_IDX … #define regGL2A_ADDR_MATCH_MASK … #define regGL2A_ADDR_MATCH_MASK_BASE_IDX … #define regGL2A_ADDR_MATCH_SIZE … #define regGL2A_ADDR_MATCH_SIZE_BASE_IDX … #define regGL2A_CTRL … #define regGL2A_CTRL_BASE_IDX … #define regGL2A_CTRL2 … #define regGL2A_CTRL2_BASE_IDX … #define regGL2A_CHANNEL_HASH_CTRL … #define regGL2A_CHANNEL_HASH_CTRL_BASE_IDX … #define regGL2A_DISABLE … #define regGL2A_DISABLE_BASE_IDX … #define regGL2A_RESP_THROTTLE_CTRL … #define regGL2A_RESP_THROTTLE_CTRL_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_perfddec // base address: 0x34000 #define regCPG_PERFCOUNTER1_LO … #define regCPG_PERFCOUNTER1_LO_BASE_IDX … #define regCPG_PERFCOUNTER1_HI … #define regCPG_PERFCOUNTER1_HI_BASE_IDX … #define regCPG_PERFCOUNTER0_LO … #define regCPG_PERFCOUNTER0_LO_BASE_IDX … #define regCPG_PERFCOUNTER0_HI … #define regCPG_PERFCOUNTER0_HI_BASE_IDX … #define regCPC_PERFCOUNTER1_LO … #define regCPC_PERFCOUNTER1_LO_BASE_IDX … #define regCPC_PERFCOUNTER1_HI … #define regCPC_PERFCOUNTER1_HI_BASE_IDX … #define regCPC_PERFCOUNTER0_LO … #define regCPC_PERFCOUNTER0_LO_BASE_IDX … #define regCPC_PERFCOUNTER0_HI … #define regCPC_PERFCOUNTER0_HI_BASE_IDX … #define regCPF_PERFCOUNTER1_LO … #define regCPF_PERFCOUNTER1_LO_BASE_IDX … #define regCPF_PERFCOUNTER1_HI … #define regCPF_PERFCOUNTER1_HI_BASE_IDX … #define regCPF_PERFCOUNTER0_LO … #define regCPF_PERFCOUNTER0_LO_BASE_IDX … #define regCPF_PERFCOUNTER0_HI … #define regCPF_PERFCOUNTER0_HI_BASE_IDX … #define regCPF_LATENCY_STATS_DATA … #define regCPF_LATENCY_STATS_DATA_BASE_IDX … #define regCPG_LATENCY_STATS_DATA … #define regCPG_LATENCY_STATS_DATA_BASE_IDX … #define regCPC_LATENCY_STATS_DATA … #define regCPC_LATENCY_STATS_DATA_BASE_IDX … #define regGRBM_PERFCOUNTER0_LO … #define regGRBM_PERFCOUNTER0_LO_BASE_IDX … #define regGRBM_PERFCOUNTER0_HI … #define regGRBM_PERFCOUNTER0_HI_BASE_IDX … #define regGRBM_PERFCOUNTER1_LO … #define regGRBM_PERFCOUNTER1_LO_BASE_IDX … #define regGRBM_PERFCOUNTER1_HI … #define regGRBM_PERFCOUNTER1_HI_BASE_IDX … #define regGE1_PERFCOUNTER0_LO … #define regGE1_PERFCOUNTER0_LO_BASE_IDX … #define regGE1_PERFCOUNTER0_HI … #define regGE1_PERFCOUNTER0_HI_BASE_IDX … #define regGE1_PERFCOUNTER1_LO … #define regGE1_PERFCOUNTER1_LO_BASE_IDX … #define regGE1_PERFCOUNTER1_HI … #define regGE1_PERFCOUNTER1_HI_BASE_IDX … #define regGE1_PERFCOUNTER2_LO … #define regGE1_PERFCOUNTER2_LO_BASE_IDX … #define regGE1_PERFCOUNTER2_HI … #define regGE1_PERFCOUNTER2_HI_BASE_IDX … #define regGE1_PERFCOUNTER3_LO … #define regGE1_PERFCOUNTER3_LO_BASE_IDX … #define regGE1_PERFCOUNTER3_HI … #define regGE1_PERFCOUNTER3_HI_BASE_IDX … #define regGE2_DIST_PERFCOUNTER0_LO … #define regGE2_DIST_PERFCOUNTER0_LO_BASE_IDX … #define regGE2_DIST_PERFCOUNTER0_HI … #define regGE2_DIST_PERFCOUNTER0_HI_BASE_IDX … #define regGE2_DIST_PERFCOUNTER1_LO … #define regGE2_DIST_PERFCOUNTER1_LO_BASE_IDX … #define regGE2_DIST_PERFCOUNTER1_HI … #define regGE2_DIST_PERFCOUNTER1_HI_BASE_IDX … #define regGE2_DIST_PERFCOUNTER2_LO … #define regGE2_DIST_PERFCOUNTER2_LO_BASE_IDX … #define regGE2_DIST_PERFCOUNTER2_HI … #define regGE2_DIST_PERFCOUNTER2_HI_BASE_IDX … #define regGE2_DIST_PERFCOUNTER3_LO … #define regGE2_DIST_PERFCOUNTER3_LO_BASE_IDX … #define regGE2_DIST_PERFCOUNTER3_HI … #define regGE2_DIST_PERFCOUNTER3_HI_BASE_IDX … #define regGC_EA_CPWD_PERFCOUNTER0_LO … #define regGC_EA_CPWD_PERFCOUNTER0_LO_BASE_IDX … #define regGC_EA_CPWD_PERFCOUNTER0_HI … #define regGC_EA_CPWD_PERFCOUNTER0_HI_BASE_IDX … #define regGC_EA_CPWD_PERFCOUNTER1_LO … #define regGC_EA_CPWD_PERFCOUNTER1_LO_BASE_IDX … #define regGC_EA_CPWD_PERFCOUNTER1_HI … #define regGC_EA_CPWD_PERFCOUNTER1_HI_BASE_IDX … #define regGC_EA_SE_PERFCOUNTER0_LO … #define regGC_EA_SE_PERFCOUNTER0_LO_BASE_IDX … #define regGC_EA_SE_PERFCOUNTER0_HI … #define regGC_EA_SE_PERFCOUNTER0_HI_BASE_IDX … #define regGC_EA_SE_PERFCOUNTER1_LO … #define regGC_EA_SE_PERFCOUNTER1_LO_BASE_IDX … #define regGC_EA_SE_PERFCOUNTER1_HI … #define regGC_EA_SE_PERFCOUNTER1_HI_BASE_IDX … #define regGL2C_PERFCOUNTER0_LO … #define regGL2C_PERFCOUNTER0_LO_BASE_IDX … #define regGL2C_PERFCOUNTER0_HI … #define regGL2C_PERFCOUNTER0_HI_BASE_IDX … #define regGL2C_PERFCOUNTER1_LO … #define regGL2C_PERFCOUNTER1_LO_BASE_IDX … #define regGL2C_PERFCOUNTER1_HI … #define regGL2C_PERFCOUNTER1_HI_BASE_IDX … #define regGL2C_PERFCOUNTER2_LO … #define regGL2C_PERFCOUNTER2_LO_BASE_IDX … #define regGL2C_PERFCOUNTER2_HI … #define regGL2C_PERFCOUNTER2_HI_BASE_IDX … #define regGL2C_PERFCOUNTER3_LO … #define regGL2C_PERFCOUNTER3_LO_BASE_IDX … #define regGL2C_PERFCOUNTER3_HI … #define regGL2C_PERFCOUNTER3_HI_BASE_IDX … #define regGL2A_PERFCOUNTER0_LO … #define regGL2A_PERFCOUNTER0_LO_BASE_IDX … #define regGL2A_PERFCOUNTER0_HI … #define regGL2A_PERFCOUNTER0_HI_BASE_IDX … #define regGL2A_PERFCOUNTER1_LO … #define regGL2A_PERFCOUNTER1_LO_BASE_IDX … #define regGL2A_PERFCOUNTER1_HI … #define regGL2A_PERFCOUNTER1_HI_BASE_IDX … #define regGL2A_PERFCOUNTER2_LO … #define regGL2A_PERFCOUNTER2_LO_BASE_IDX … #define regGL2A_PERFCOUNTER2_HI … #define regGL2A_PERFCOUNTER2_HI_BASE_IDX … #define regGL2A_PERFCOUNTER3_LO … #define regGL2A_PERFCOUNTER3_LO_BASE_IDX … #define regGL2A_PERFCOUNTER3_HI … #define regGL2A_PERFCOUNTER3_HI_BASE_IDX … #define regCHC_PERFCOUNTER0_LO … #define regCHC_PERFCOUNTER0_LO_BASE_IDX … #define regCHC_PERFCOUNTER0_HI … #define regCHC_PERFCOUNTER0_HI_BASE_IDX … #define regCHC_PERFCOUNTER1_LO … #define regCHC_PERFCOUNTER1_LO_BASE_IDX … #define regCHC_PERFCOUNTER1_HI … #define regCHC_PERFCOUNTER1_HI_BASE_IDX … #define regCHC_PERFCOUNTER2_LO … #define regCHC_PERFCOUNTER2_LO_BASE_IDX … #define regCHC_PERFCOUNTER2_HI … #define regCHC_PERFCOUNTER2_HI_BASE_IDX … #define regCHC_PERFCOUNTER3_LO … #define regCHC_PERFCOUNTER3_LO_BASE_IDX … #define regCHC_PERFCOUNTER3_HI … #define regCHC_PERFCOUNTER3_HI_BASE_IDX … #define regRLC_PERFCOUNTER0_LO … #define regRLC_PERFCOUNTER0_LO_BASE_IDX … #define regRLC_PERFCOUNTER0_HI … #define regRLC_PERFCOUNTER0_HI_BASE_IDX … #define regRLC_PERFCOUNTER1_LO … #define regRLC_PERFCOUNTER1_LO_BASE_IDX … #define regRLC_PERFCOUNTER1_HI … #define regRLC_PERFCOUNTER1_HI_BASE_IDX … #define regGCR_PERFCOUNTER0_LO … #define regGCR_PERFCOUNTER0_LO_BASE_IDX … #define regGCR_PERFCOUNTER0_HI … #define regGCR_PERFCOUNTER0_HI_BASE_IDX … #define regGCR_PERFCOUNTER1_LO … #define regGCR_PERFCOUNTER1_LO_BASE_IDX … #define regGCR_PERFCOUNTER1_HI … #define regGCR_PERFCOUNTER1_HI_BASE_IDX … #define regCHA_PERFCOUNTER0_LO … #define regCHA_PERFCOUNTER0_LO_BASE_IDX … #define regCHA_PERFCOUNTER0_HI … #define regCHA_PERFCOUNTER0_HI_BASE_IDX … #define regCHA_PERFCOUNTER1_LO … #define regCHA_PERFCOUNTER1_LO_BASE_IDX … #define regCHA_PERFCOUNTER1_HI … #define regCHA_PERFCOUNTER1_HI_BASE_IDX … #define regCHA_PERFCOUNTER2_LO … #define regCHA_PERFCOUNTER2_LO_BASE_IDX … #define regCHA_PERFCOUNTER2_HI … #define regCHA_PERFCOUNTER2_HI_BASE_IDX … #define regCHA_PERFCOUNTER3_LO … #define regCHA_PERFCOUNTER3_LO_BASE_IDX … #define regCHA_PERFCOUNTER3_HI … #define regCHA_PERFCOUNTER3_HI_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_perfsdec // base address: 0x36000 #define regCPG_PERFCOUNTER1_SELECT … #define regCPG_PERFCOUNTER1_SELECT_BASE_IDX … #define regCPG_PERFCOUNTER0_SELECT1 … #define regCPG_PERFCOUNTER0_SELECT1_BASE_IDX … #define regCPG_PERFCOUNTER0_SELECT … #define regCPG_PERFCOUNTER0_SELECT_BASE_IDX … #define regCPC_PERFCOUNTER1_SELECT … #define regCPC_PERFCOUNTER1_SELECT_BASE_IDX … #define regCPC_PERFCOUNTER0_SELECT1 … #define regCPC_PERFCOUNTER0_SELECT1_BASE_IDX … #define regCPF_PERFCOUNTER1_SELECT … #define regCPF_PERFCOUNTER1_SELECT_BASE_IDX … #define regCPF_PERFCOUNTER0_SELECT1 … #define regCPF_PERFCOUNTER0_SELECT1_BASE_IDX … #define regCPF_PERFCOUNTER0_SELECT … #define regCPF_PERFCOUNTER0_SELECT_BASE_IDX … #define regCP_CP_PERFMON_CNTL … #define regCP_CP_PERFMON_CNTL_BASE_IDX … #define regCPC_PERFCOUNTER0_SELECT … #define regCPC_PERFCOUNTER0_SELECT_BASE_IDX … #define regCPF_TC_PERF_COUNTER_WINDOW_SELECT … #define regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX … #define regCPG_TC_PERF_COUNTER_WINDOW_SELECT … #define regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX … #define regCPF_LATENCY_STATS_SELECT … #define regCPF_LATENCY_STATS_SELECT_BASE_IDX … #define regCPG_LATENCY_STATS_SELECT … #define regCPG_LATENCY_STATS_SELECT_BASE_IDX … #define regCPC_LATENCY_STATS_SELECT … #define regCPC_LATENCY_STATS_SELECT_BASE_IDX … #define regCPC_TC_PERF_COUNTER_WINDOW_SELECT … #define regCPC_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX … #define regCP_DRAW_OBJECT … #define regCP_DRAW_OBJECT_BASE_IDX … #define regCP_DRAW_OBJECT_COUNTER … #define regCP_DRAW_OBJECT_COUNTER_BASE_IDX … #define regCP_DRAW_WINDOW_MASK_HI … #define regCP_DRAW_WINDOW_MASK_HI_BASE_IDX … #define regCP_DRAW_WINDOW_HI … #define regCP_DRAW_WINDOW_HI_BASE_IDX … #define regCP_DRAW_WINDOW_LO … #define regCP_DRAW_WINDOW_LO_BASE_IDX … #define regCP_DRAW_WINDOW_CNTL … #define regCP_DRAW_WINDOW_CNTL_BASE_IDX … #define regGRBM_PERFCOUNTER0_SELECT … #define regGRBM_PERFCOUNTER0_SELECT_BASE_IDX … #define regGRBM_PERFCOUNTER1_SELECT … #define regGRBM_PERFCOUNTER1_SELECT_BASE_IDX … #define regGRBM_PERFCOUNTER0_SELECT_HI … #define regGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX … #define regGRBM_PERFCOUNTER1_SELECT_HI … #define regGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX … #define regGE1_PERFCOUNTER0_SELECT … #define regGE1_PERFCOUNTER0_SELECT_BASE_IDX … #define regGE1_PERFCOUNTER0_SELECT1 … #define regGE1_PERFCOUNTER0_SELECT1_BASE_IDX … #define regGE1_PERFCOUNTER1_SELECT … #define regGE1_PERFCOUNTER1_SELECT_BASE_IDX … #define regGE1_PERFCOUNTER1_SELECT1 … #define regGE1_PERFCOUNTER1_SELECT1_BASE_IDX … #define regGE1_PERFCOUNTER2_SELECT … #define regGE1_PERFCOUNTER2_SELECT_BASE_IDX … #define regGE1_PERFCOUNTER2_SELECT1 … #define regGE1_PERFCOUNTER2_SELECT1_BASE_IDX … #define regGE1_PERFCOUNTER3_SELECT … #define regGE1_PERFCOUNTER3_SELECT_BASE_IDX … #define regGE1_PERFCOUNTER3_SELECT1 … #define regGE1_PERFCOUNTER3_SELECT1_BASE_IDX … #define regGE2_DIST_PERFCOUNTER0_SELECT … #define regGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX … #define regGE2_DIST_PERFCOUNTER0_SELECT1 … #define regGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX … #define regGE2_DIST_PERFCOUNTER1_SELECT … #define regGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX … #define regGE2_DIST_PERFCOUNTER1_SELECT1 … #define regGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX … #define regGE2_DIST_PERFCOUNTER2_SELECT … #define regGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX … #define regGE2_DIST_PERFCOUNTER2_SELECT1 … #define regGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX … #define regGE2_DIST_PERFCOUNTER3_SELECT … #define regGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX … #define regGE2_DIST_PERFCOUNTER3_SELECT1 … #define regGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX … #define regGC_EA_CPWD_PERFCOUNTER0_SELECT … #define regGC_EA_CPWD_PERFCOUNTER0_SELECT_BASE_IDX … #define regGC_EA_CPWD_PERFCOUNTER0_SELECT1 … #define regGC_EA_CPWD_PERFCOUNTER0_SELECT1_BASE_IDX … #define regGC_EA_CPWD_PERFCOUNTER1_SELECT … #define regGC_EA_CPWD_PERFCOUNTER1_SELECT_BASE_IDX … #define regGC_EA_SE_PERFCOUNTER0_SELECT … #define regGC_EA_SE_PERFCOUNTER0_SELECT_BASE_IDX … #define regGC_EA_SE_PERFCOUNTER0_SELECT1 … #define regGC_EA_SE_PERFCOUNTER0_SELECT1_BASE_IDX … #define regGC_EA_SE_PERFCOUNTER1_SELECT … #define regGC_EA_SE_PERFCOUNTER1_SELECT_BASE_IDX … #define regGL2C_PERFCOUNTER0_SELECT … #define regGL2C_PERFCOUNTER0_SELECT_BASE_IDX … #define regGL2C_PERFCOUNTER0_SELECT1 … #define regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX … #define regGL2C_PERFCOUNTER1_SELECT … #define regGL2C_PERFCOUNTER1_SELECT_BASE_IDX … #define regGL2C_PERFCOUNTER1_SELECT1 … #define regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX … #define regGL2C_PERFCOUNTER2_SELECT … #define regGL2C_PERFCOUNTER2_SELECT_BASE_IDX … #define regGL2C_PERFCOUNTER2_SELECT1 … #define regGL2C_PERFCOUNTER2_SELECT1_BASE_IDX … #define regGL2C_PERFCOUNTER3_SELECT … #define regGL2C_PERFCOUNTER3_SELECT_BASE_IDX … #define regGL2C_PERFCOUNTER3_SELECT1 … #define regGL2C_PERFCOUNTER3_SELECT1_BASE_IDX … #define regGL2A_PERFCOUNTER0_SELECT … #define regGL2A_PERFCOUNTER0_SELECT_BASE_IDX … #define regGL2A_PERFCOUNTER0_SELECT1 … #define regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX … #define regGL2A_PERFCOUNTER1_SELECT … #define regGL2A_PERFCOUNTER1_SELECT_BASE_IDX … #define regGL2A_PERFCOUNTER1_SELECT1 … #define regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX … #define regGL2A_PERFCOUNTER2_SELECT … #define regGL2A_PERFCOUNTER2_SELECT_BASE_IDX … #define regGL2A_PERFCOUNTER2_SELECT1 … #define regGL2A_PERFCOUNTER2_SELECT1_BASE_IDX … #define regGL2A_PERFCOUNTER3_SELECT … #define regGL2A_PERFCOUNTER3_SELECT_BASE_IDX … #define regGL2A_PERFCOUNTER3_SELECT1 … #define regGL2A_PERFCOUNTER3_SELECT1_BASE_IDX … #define regCHC_PERFCOUNTER0_SELECT … #define regCHC_PERFCOUNTER0_SELECT_BASE_IDX … #define regCHC_PERFCOUNTER0_SELECT1 … #define regCHC_PERFCOUNTER0_SELECT1_BASE_IDX … #define regCHC_PERFCOUNTER1_SELECT … #define regCHC_PERFCOUNTER1_SELECT_BASE_IDX … #define regCHC_PERFCOUNTER1_SELECT1 … #define regCHC_PERFCOUNTER1_SELECT1_BASE_IDX … #define regCHC_PERFCOUNTER2_SELECT … #define regCHC_PERFCOUNTER2_SELECT_BASE_IDX … #define regCHC_PERFCOUNTER2_SELECT1 … #define regCHC_PERFCOUNTER2_SELECT1_BASE_IDX … #define regCHC_PERFCOUNTER3_SELECT … #define regCHC_PERFCOUNTER3_SELECT_BASE_IDX … #define regCHC_PERFCOUNTER3_SELECT1 … #define regCHC_PERFCOUNTER3_SELECT1_BASE_IDX … #define regRLC_SPM_PERFMON_CNTL … #define regRLC_SPM_PERFMON_CNTL_BASE_IDX … #define regRLC_SPM_PERFMON_RING_BASE_LO … #define regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX … #define regRLC_SPM_PERFMON_RING_BASE_HI … #define regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX … #define regRLC_SPM_PERFMON_RING_SIZE … #define regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX … #define regRLC_SPM_RING_WRPTR … #define regRLC_SPM_RING_WRPTR_BASE_IDX … #define regRLC_SPM_RING_RDPTR … #define regRLC_SPM_RING_RDPTR_BASE_IDX … #define regRLC_SPM_SEGMENT_THRESHOLD … #define regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX … #define regRLC_SPM_PERFMON_SEGMENT_SIZE … #define regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX … #define regRLC_SPM_GLOBAL_MUXSEL_ADDR … #define regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX … #define regRLC_SPM_GLOBAL_MUXSEL_DATA … #define regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX … #define regRLC_SPM_SE_MUXSEL_ADDR … #define regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX … #define regRLC_SPM_SE_MUXSEL_DATA … #define regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX … #define regRLC_SPM_ACCUM_DATARAM_ADDR … #define regRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX … #define regRLC_SPM_ACCUM_DATARAM_DATA … #define regRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX … #define regRLC_SPM_ACCUM_SWA_DATARAM_ADDR … #define regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX … #define regRLC_SPM_ACCUM_SWA_DATARAM_DATA … #define regRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX … #define regRLC_SPM_ACCUM_CTRLRAM_ADDR … #define regRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX … #define regRLC_SPM_ACCUM_CTRLRAM_DATA … #define regRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX … #define regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET … #define regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX … #define regRLC_SPM_ACCUM_STATUS … #define regRLC_SPM_ACCUM_STATUS_BASE_IDX … #define regRLC_SPM_ACCUM_CTRL … #define regRLC_SPM_ACCUM_CTRL_BASE_IDX … #define regRLC_SPM_ACCUM_MODE … #define regRLC_SPM_ACCUM_MODE_BASE_IDX … #define regRLC_SPM_ACCUM_THRESHOLD … #define regRLC_SPM_ACCUM_THRESHOLD_BASE_IDX … #define regRLC_SPM_ACCUM_SAMPLES_REQUESTED … #define regRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX … #define regRLC_SPM_ACCUM_DATARAM_WRCOUNT … #define regRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX … #define regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS … #define regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX … #define regRLC_SPM_PAUSE … #define regRLC_SPM_PAUSE_BASE_IDX … #define regRLC_SPM_STATUS … #define regRLC_SPM_STATUS_BASE_IDX … #define regRLC_SPM_GFXCLOCK_LOWCOUNT … #define regRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX … #define regRLC_SPM_GFXCLOCK_HIGHCOUNT … #define regRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX … #define regRLC_SPM_GTS_TRIGGER_VALUE_LO … #define regRLC_SPM_GTS_TRIGGER_VALUE_LO_BASE_IDX … #define regRLC_SPM_GTS_TRIGGER_VALUE_HI … #define regRLC_SPM_GTS_TRIGGER_VALUE_HI_BASE_IDX … #define regRLC_SPM_MODE … #define regRLC_SPM_MODE_BASE_IDX … #define regRLC_SPM_RSPM_REQ_DATA … #define regRLC_SPM_RSPM_REQ_DATA_BASE_IDX … #define regRLC_SPM_RSPM_REQ_OP … #define regRLC_SPM_RSPM_REQ_OP_BASE_IDX … #define regRLC_SPM_RSPM_RET_DATA … #define regRLC_SPM_RSPM_RET_DATA_BASE_IDX … #define regRLC_SPM_RSPM_RET_OP … #define regRLC_SPM_RSPM_RET_OP_BASE_IDX … #define regRLC_SPM_SE_RSPM_REQ_DATA … #define regRLC_SPM_SE_RSPM_REQ_DATA_BASE_IDX … #define regRLC_SPM_SE_RSPM_REQ_OP … #define regRLC_SPM_SE_RSPM_REQ_OP_BASE_IDX … #define regRLC_SPM_SE_RSPM_RET_DATA … #define regRLC_SPM_SE_RSPM_RET_DATA_BASE_IDX … #define regRLC_SPM_SE_RSPM_RET_OP … #define regRLC_SPM_SE_RSPM_RET_OP_BASE_IDX … #define regRLC_SPM_RSPM_CMD … #define regRLC_SPM_RSPM_CMD_BASE_IDX … #define regRLC_SPM_RSPM_CMD_ACK … #define regRLC_SPM_RSPM_CMD_ACK_BASE_IDX … #define regRLC_SPM_SPARE … #define regRLC_SPM_SPARE_BASE_IDX … #define regRLC_PERFMON_CNTL … #define regRLC_PERFMON_CNTL_BASE_IDX … #define regRLC_PERFCOUNTER0_SELECT … #define regRLC_PERFCOUNTER0_SELECT_BASE_IDX … #define regRLC_PERFCOUNTER1_SELECT … #define regRLC_PERFCOUNTER1_SELECT_BASE_IDX … #define regGCR_PERFCOUNTER0_SELECT … #define regGCR_PERFCOUNTER0_SELECT_BASE_IDX … #define regGCR_PERFCOUNTER0_SELECT1 … #define regGCR_PERFCOUNTER0_SELECT1_BASE_IDX … #define regGCR_PERFCOUNTER1_SELECT … #define regGCR_PERFCOUNTER1_SELECT_BASE_IDX … #define regGCR_PERFCOUNTER1_SELECT1 … #define regGCR_PERFCOUNTER1_SELECT1_BASE_IDX … #define regCHA_PERFCOUNTER0_SELECT … #define regCHA_PERFCOUNTER0_SELECT_BASE_IDX … #define regCHA_PERFCOUNTER0_SELECT1 … #define regCHA_PERFCOUNTER0_SELECT1_BASE_IDX … #define regCHA_PERFCOUNTER1_SELECT … #define regCHA_PERFCOUNTER1_SELECT_BASE_IDX … #define regCHA_PERFCOUNTER1_SELECT1 … #define regCHA_PERFCOUNTER1_SELECT1_BASE_IDX … #define regCHA_PERFCOUNTER2_SELECT … #define regCHA_PERFCOUNTER2_SELECT_BASE_IDX … #define regCHA_PERFCOUNTER2_SELECT1 … #define regCHA_PERFCOUNTER2_SELECT1_BASE_IDX … #define regCHA_PERFCOUNTER3_SELECT … #define regCHA_PERFCOUNTER3_SELECT_BASE_IDX … #define regCHA_PERFCOUNTER3_SELECT1 … #define regCHA_PERFCOUNTER3_SELECT1_BASE_IDX … // addressBlock: gc_gfx_cpwd_gdfll_gdfll_gdfll_reg_blk // base address: 0x3a000 #define regGDFLL_EDC_HYSTERESIS_CNTL … #define regGDFLL_EDC_HYSTERESIS_CNTL_BASE_IDX … #define regGDFLL_EDC_HYSTERESIS_STAT … #define regGDFLL_EDC_HYSTERESIS_STAT_BASE_IDX … // addressBlock: gc_gfx_cpwd_gdfll_xvmin_xvmin_xvmin_reg_blk // base address: 0x3a014 #define regXVMIN_XVMIN_WR_DATA … #define regXVMIN_XVMIN_WR_DATA_BASE_IDX … // addressBlock: gc_gfx_cpwd_grtavfs_grtavfs_grtavfs_reg_blk // base address: 0x3a600 #define regGRTAVFS_RTAVFS_REG_ADDR … #define regGRTAVFS_RTAVFS_REG_ADDR_BASE_IDX … #define regGRTAVFS_RTAVFS_WR_DATA … #define regGRTAVFS_RTAVFS_WR_DATA_BASE_IDX … #define regGRTAVFS_GENERAL_0 … #define regGRTAVFS_GENERAL_0_BASE_IDX … #define regGRTAVFS_RTAVFS_RD_DATA … #define regGRTAVFS_RTAVFS_RD_DATA_BASE_IDX … #define regGRTAVFS_RTAVFS_REG_CTRL … #define regGRTAVFS_RTAVFS_REG_CTRL_BASE_IDX … #define regGRTAVFS_RTAVFS_REG_STATUS … #define regGRTAVFS_RTAVFS_REG_STATUS_BASE_IDX … #define regGRTAVFS_TARG_FREQ … #define regGRTAVFS_TARG_FREQ_BASE_IDX … #define regGRTAVFS_TARG_VOLT … #define regGRTAVFS_TARG_VOLT_BASE_IDX … #define regGRTAVFS_SOFT_RESET … #define regGRTAVFS_SOFT_RESET_BASE_IDX … #define regGRTAVFS_PSM_CNTL … #define regGRTAVFS_PSM_CNTL_BASE_IDX … #define regGRTAVFS_CLK_CNTL … #define regGRTAVFS_CLK_CNTL_BASE_IDX … #define regGFX_ICG_GRTAVFS_CTRL … #define regGFX_ICG_GRTAVFS_CTRL_BASE_IDX … // addressBlock: gc_gfx_cpwd_grtavfs_rtavfs_rtavfs_rtavfs_reg_blk // base address: 0x3a600 #define regRTAVFS_RTAVFS_REG_ADDR … #define regRTAVFS_RTAVFS_REG_ADDR_BASE_IDX … #define regRTAVFS_RTAVFS_WR_DATA … #define regRTAVFS_RTAVFS_WR_DATA_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_hypdec // base address: 0x3e000 #define regRLC_SDMA0_STATUS … #define regRLC_SDMA0_STATUS_BASE_IDX … #define regRLC_SDMA1_STATUS … #define regRLC_SDMA1_STATUS_BASE_IDX … #define regRLC_SDMA2_STATUS … #define regRLC_SDMA2_STATUS_BASE_IDX … #define regRLC_SDMA3_STATUS … #define regRLC_SDMA3_STATUS_BASE_IDX … #define regRLC_SDMA0_BUSY_STATUS … #define regRLC_SDMA0_BUSY_STATUS_BASE_IDX … #define regRLC_SDMA1_BUSY_STATUS … #define regRLC_SDMA1_BUSY_STATUS_BASE_IDX … #define regRLC_SDMA2_BUSY_STATUS … #define regRLC_SDMA2_BUSY_STATUS_BASE_IDX … #define regRLC_SDMA3_BUSY_STATUS … #define regRLC_SDMA3_BUSY_STATUS_BASE_IDX … #define regRLC_HYP_SEMAPHORE_0 … #define regRLC_HYP_SEMAPHORE_0_BASE_IDX … #define regRLC_HYP_SEMAPHORE_1 … #define regRLC_HYP_SEMAPHORE_1_BASE_IDX … #define regRLC_BUSY_CLK_CNTL … #define regRLC_BUSY_CLK_CNTL_BASE_IDX … #define regRLC_CLK_CNTL … #define regRLC_CLK_CNTL_BASE_IDX … #define regRLC_IH_COOKIE … #define regRLC_IH_COOKIE_BASE_IDX … #define regRLC_IH_COOKIE_CNTL … #define regRLC_IH_COOKIE_CNTL_BASE_IDX … #define regRLC_HYP_RLCG_UCODE_CHKSUM … #define regRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX … #define regRLC_HYP_SEMAPHORE_2 … #define regRLC_HYP_SEMAPHORE_2_BASE_IDX … #define regRLC_HYP_SEMAPHORE_3 … #define regRLC_HYP_SEMAPHORE_3_BASE_IDX … #define regRLC_GPM_UCODE_ADDR … #define regRLC_GPM_UCODE_ADDR_BASE_IDX … #define regRLC_GPM_UCODE_DATA … #define regRLC_GPM_UCODE_DATA_BASE_IDX … #define regRLC_GPM_IRAM_ADDR … #define regRLC_GPM_IRAM_ADDR_BASE_IDX … #define regRLC_GPM_IRAM_DATA … #define regRLC_GPM_IRAM_DATA_BASE_IDX … #define regRLC_LX6_DRAM_ADDR … #define regRLC_LX6_DRAM_ADDR_BASE_IDX … #define regRLC_LX6_DRAM_DATA … #define regRLC_LX6_DRAM_DATA_BASE_IDX … #define regRLC_LX6_IRAM_ADDR … #define regRLC_LX6_IRAM_ADDR_BASE_IDX … #define regRLC_LX6_IRAM_DATA … #define regRLC_LX6_IRAM_DATA_BASE_IDX … #define regRLC_GPM_SCRATCH_ADDR … #define regRLC_GPM_SCRATCH_ADDR_BASE_IDX … #define regRLC_GPM_SCRATCH_DATA … #define regRLC_GPM_SCRATCH_DATA_BASE_IDX … #define regRLC_SRM_DRAM_ADDR … #define regRLC_SRM_DRAM_ADDR_BASE_IDX … #define regRLC_SRM_DRAM_DATA … #define regRLC_SRM_DRAM_DATA_BASE_IDX … #define regRLC_SRM_ARAM_ADDR … #define regRLC_SRM_ARAM_ADDR_BASE_IDX … #define regRLC_SRM_ARAM_DATA … #define regRLC_SRM_ARAM_DATA_BASE_IDX … #define regRLC_GTS_OFFSET_LSB … #define regRLC_GTS_OFFSET_LSB_BASE_IDX … #define regRLC_GTS_OFFSET_MSB … #define regRLC_GTS_OFFSET_MSB_BASE_IDX … #define regRLC_GTS_OFFSET_SNAP_LSB … #define regRLC_GTS_OFFSET_SNAP_LSB_BASE_IDX … #define regRLC_GTS_OFFSET_SNAP_MSB … #define regRLC_GTS_OFFSET_SNAP_MSB_BASE_IDX … #define regGL2_PIPE_STEER_0 … #define regGL2_PIPE_STEER_0_BASE_IDX … #define regGL2_PIPE_STEER_1 … #define regGL2_PIPE_STEER_1_BASE_IDX … #define regGL2_PIPE_STEER_2 … #define regGL2_PIPE_STEER_2_BASE_IDX … #define regGL2_PIPE_STEER_3 … #define regGL2_PIPE_STEER_3_BASE_IDX … #define regCH_PIPE_STEER … #define regCH_PIPE_STEER_BASE_IDX … #define regGC_USER_FULL_SA_UNIT_DISABLE … #define regGC_USER_FULL_SA_UNIT_DISABLE_BASE_IDX … #define regGRBM_GC_USER_SA_UNIT_DISABLE … #define regGRBM_GC_USER_SA_UNIT_DISABLE_BASE_IDX … #define regGC_USER_GL2C_DISABLE_0 … #define regGC_USER_GL2C_DISABLE_0_BASE_IDX … #define regGC_USER_GL2C_DISABLE_1 … #define regGC_USER_GL2C_DISABLE_1_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_cphypdec // base address: 0x3e000 #define regCP_HYP_CONTEXT_RANGE_BASE … #define regCP_HYP_CONTEXT_RANGE_BASE_BASE_IDX … #define regCP_HYP_CONTEXT_RANGE_END … #define regCP_HYP_CONTEXT_RANGE_END_BASE_IDX … #define regCP_HYP_PFP_UCODE_ADDR … #define regCP_HYP_PFP_UCODE_ADDR_BASE_IDX … #define regCP_PFP_UCODE_ADDR … #define regCP_PFP_UCODE_ADDR_BASE_IDX … #define regCP_HYP_PFP_UCODE_DATA … #define regCP_HYP_PFP_UCODE_DATA_BASE_IDX … #define regCP_PFP_UCODE_DATA … #define regCP_PFP_UCODE_DATA_BASE_IDX … #define regCP_HYP_ME_UCODE_ADDR … #define regCP_HYP_ME_UCODE_ADDR_BASE_IDX … #define regCP_ME_RAM_RADDR … #define regCP_ME_RAM_RADDR_BASE_IDX … #define regCP_ME_RAM_WADDR … #define regCP_ME_RAM_WADDR_BASE_IDX … #define regCP_HYP_ME_UCODE_DATA … #define regCP_HYP_ME_UCODE_DATA_BASE_IDX … #define regCP_ME_RAM_DATA … #define regCP_ME_RAM_DATA_BASE_IDX … #define regCP_HYP_MEC1_UCODE_ADDR … #define regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX … #define regCP_MEC_ME1_UCODE_ADDR … #define regCP_MEC_ME1_UCODE_ADDR_BASE_IDX … #define regCP_HYP_MEC1_UCODE_DATA … #define regCP_HYP_MEC1_UCODE_DATA_BASE_IDX … #define regCP_MEC_ME1_UCODE_DATA … #define regCP_MEC_ME1_UCODE_DATA_BASE_IDX … #define regCP_HYP_PFP_UCODE_CHKSUM … #define regCP_HYP_PFP_UCODE_CHKSUM_BASE_IDX … #define regCP_HYP_ME_UCODE_CHKSUM … #define regCP_HYP_ME_UCODE_CHKSUM_BASE_IDX … #define regCP_HYP_MEC_ME1_UCODE_CHKSUM … #define regCP_HYP_MEC_ME1_UCODE_CHKSUM_BASE_IDX … #define regCP_PFP_IC_BASE_LO … #define regCP_PFP_IC_BASE_LO_BASE_IDX … #define regCP_PFP_IC_BASE_HI … #define regCP_PFP_IC_BASE_HI_BASE_IDX … #define regCP_PFP_IC_BASE_CNTL … #define regCP_PFP_IC_BASE_CNTL_BASE_IDX … #define regCP_PFP_IC_OP_CNTL … #define regCP_PFP_IC_OP_CNTL_BASE_IDX … #define regCP_ME_IC_BASE_LO … #define regCP_ME_IC_BASE_LO_BASE_IDX … #define regCP_ME_IC_BASE_HI … #define regCP_ME_IC_BASE_HI_BASE_IDX … #define regCP_ME_IC_BASE_CNTL … #define regCP_ME_IC_BASE_CNTL_BASE_IDX … #define regCP_ME_IC_OP_CNTL … #define regCP_ME_IC_OP_CNTL_BASE_IDX … #define regCP_CPC_IC_BASE_LO … #define regCP_CPC_IC_BASE_LO_BASE_IDX … #define regCP_CPC_IC_BASE_HI … #define regCP_CPC_IC_BASE_HI_BASE_IDX … #define regCP_CPC_IC_BASE_CNTL … #define regCP_CPC_IC_BASE_CNTL_BASE_IDX … #define regCP_MES_IC_BASE_LO … #define regCP_MES_IC_BASE_LO_BASE_IDX … #define regCP_MES_MIBASE_LO … #define regCP_MES_MIBASE_LO_BASE_IDX … #define regCP_MES_IC_BASE_HI … #define regCP_MES_IC_BASE_HI_BASE_IDX … #define regCP_MES_MIBASE_HI … #define regCP_MES_MIBASE_HI_BASE_IDX … #define regCP_MES_IC_BASE_CNTL … #define regCP_MES_IC_BASE_CNTL_BASE_IDX … #define regCP_MES_DC_BASE_LO … #define regCP_MES_DC_BASE_LO_BASE_IDX … #define regCP_MES_MDBASE_LO … #define regCP_MES_MDBASE_LO_BASE_IDX … #define regCP_MES_DC_BASE_HI … #define regCP_MES_DC_BASE_HI_BASE_IDX … #define regCP_MES_MDBASE_HI … #define regCP_MES_MDBASE_HI_BASE_IDX … #define regCP_MES_MIBOUND_LO … #define regCP_MES_MIBOUND_LO_BASE_IDX … #define regCP_MES_MIBOUND_HI … #define regCP_MES_MIBOUND_HI_BASE_IDX … #define regCP_MES_MDBOUND_LO … #define regCP_MES_MDBOUND_LO_BASE_IDX … #define regCP_MES_MDBOUND_HI … #define regCP_MES_MDBOUND_HI_BASE_IDX … #define regCP_HYP_PFP_UCODE_VERS … #define regCP_HYP_PFP_UCODE_VERS_BASE_IDX … #define regCP_HYP_ME_UCODE_VERS … #define regCP_HYP_ME_UCODE_VERS_BASE_IDX … #define regCP_GFX_RS64_DC_BASE0_LO … #define regCP_GFX_RS64_DC_BASE0_LO_BASE_IDX … #define regCP_GFX_RS64_DC_BASE1_LO … #define regCP_GFX_RS64_DC_BASE1_LO_BASE_IDX … #define regCP_GFX_RS64_DC_BASE0_HI … #define regCP_GFX_RS64_DC_BASE0_HI_BASE_IDX … #define regCP_GFX_RS64_DC_BASE1_HI … #define regCP_GFX_RS64_DC_BASE1_HI_BASE_IDX … #define regCP_GFX_RS64_MIBOUND_LO … #define regCP_GFX_RS64_MIBOUND_LO_BASE_IDX … #define regCP_GFX_RS64_MIBOUND_HI … #define regCP_GFX_RS64_MIBOUND_HI_BASE_IDX … #define regCP_MEC_DC_BASE_LO … #define regCP_MEC_DC_BASE_LO_BASE_IDX … #define regCP_MEC_MDBASE_LO … #define regCP_MEC_MDBASE_LO_BASE_IDX … #define regCP_MEC_DC_BASE_HI … #define regCP_MEC_DC_BASE_HI_BASE_IDX … #define regCP_MEC_MDBASE_HI … #define regCP_MEC_MDBASE_HI_BASE_IDX … #define regCP_MEC_MIBOUND_LO … #define regCP_MEC_MIBOUND_LO_BASE_IDX … #define regCP_MEC_MIBOUND_HI … #define regCP_MEC_MIBOUND_HI_BASE_IDX … #define regCP_MEC_MDBOUND_LO … #define regCP_MEC_MDBOUND_LO_BASE_IDX … #define regCP_MEC_MDBOUND_HI … #define regCP_MEC_MDBOUND_HI_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_grbm_hypdec // base address: 0x3e800 #define regGRBM_GFX_INDEX_SR_SELECT … #define regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX … #define regGRBM_GFX_INDEX_SR_DATA … #define regGRBM_GFX_INDEX_SR_DATA_BASE_IDX … #define regGRBM_GFX_CNTL_SR_SELECT … #define regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX … #define regGRBM_GFX_CNTL_SR_DATA … #define regGRBM_GFX_CNTL_SR_DATA_BASE_IDX … #define regGC_IH_COOKIE_0_PTR … #define regGC_IH_COOKIE_0_PTR_BASE_IDX … #define regGRBM_SE_REMAP_CNTL … #define regGRBM_SE_REMAP_CNTL_BASE_IDX … #define regGRBM_GRBM_SA_REMAP_CNTL … #define regGRBM_GRBM_SA_REMAP_CNTL_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_rlcdec // base address: 0x3b000 #define regRLC_CNTL … #define regRLC_CNTL_BASE_IDX … #define regRLC_F32_UCODE_VERSION … #define regRLC_F32_UCODE_VERSION_BASE_IDX … #define regRLC_STAT … #define regRLC_STAT_BASE_IDX … #define regRLC_ACTIVE_MASK … #define regRLC_ACTIVE_MASK_BASE_IDX … #define regRLC_GFX_SE_STATUS … #define regRLC_GFX_SE_STATUS_BASE_IDX … #define regRLC_REFCLOCK_TIMESTAMP_LSB … #define regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX … #define regRLC_REFCLOCK_TIMESTAMP_MSB … #define regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX … #define regRLC_GPM_TIMER_INT_0 … #define regRLC_GPM_TIMER_INT_0_BASE_IDX … #define regRLC_GPM_TIMER_INT_1 … #define regRLC_GPM_TIMER_INT_1_BASE_IDX … #define regRLC_GPM_TIMER_INT_2 … #define regRLC_GPM_TIMER_INT_2_BASE_IDX … #define regRLC_GPM_TIMER_INT_3 … #define regRLC_GPM_TIMER_INT_3_BASE_IDX … #define regRLC_GPM_TIMER_INT_4 … #define regRLC_GPM_TIMER_INT_4_BASE_IDX … #define regRLC_GPM_TIMER_CTRL … #define regRLC_GPM_TIMER_CTRL_BASE_IDX … #define regRLC_GPM_TIMER_STAT … #define regRLC_GPM_TIMER_STAT_BASE_IDX … #define regRLC_GPM_LEGACY_INT_STAT … #define regRLC_GPM_LEGACY_INT_STAT_BASE_IDX … #define regRLC_GPM_LEGACY_INT_CLEAR … #define regRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX … #define regRLC_INT_STAT … #define regRLC_INT_STAT_BASE_IDX … #define regRLC_MGCG_CTRL … #define regRLC_MGCG_CTRL_BASE_IDX … #define regRLC_JUMP_TABLE_RESTORE … #define regRLC_JUMP_TABLE_RESTORE_BASE_IDX … #define regRLC_PG_DELAY_2 … #define regRLC_PG_DELAY_2_BASE_IDX … #define regRLC_GPU_CLOCK_COUNT_LSB … #define regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX … #define regRLC_GPU_CLOCK_COUNT_MSB … #define regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX … #define regRLC_CAPTURE_GPU_CLOCK_COUNT … #define regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX … #define regRLC_UCODE_CNTL … #define regRLC_UCODE_CNTL_BASE_IDX … #define regRLC_GPM_THREAD_RESET … #define regRLC_GPM_THREAD_RESET_BASE_IDX … #define regRLC_GPM_CP_DMA_COMPLETE_T0 … #define regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX … #define regRLC_GPM_CP_DMA_COMPLETE_T1 … #define regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX … #define regRLC_GPM_THREAD_INVALIDATE_CACHE … #define regRLC_GPM_THREAD_INVALIDATE_CACHE_BASE_IDX … #define regRLC_CLK_COUNT_GFXCLK_LSB … #define regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX … #define regRLC_CLK_COUNT_GFXCLK_MSB … #define regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX … #define regRLC_CLK_COUNT_REFCLK_LSB … #define regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX … #define regRLC_CLK_COUNT_REFCLK_MSB … #define regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX … #define regRLC_CLK_COUNT_CTRL … #define regRLC_CLK_COUNT_CTRL_BASE_IDX … #define regRLC_CLK_COUNT_STAT … #define regRLC_CLK_COUNT_STAT_BASE_IDX … #define regRLC_RLCG_DOORBELL_CNTL … #define regRLC_RLCG_DOORBELL_CNTL_BASE_IDX … #define regRLC_RLCG_DOORBELL_STAT … #define regRLC_RLCG_DOORBELL_STAT_BASE_IDX … #define regRLC_RLCG_DOORBELL_0_DATA_LO … #define regRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX … #define regRLC_RLCG_DOORBELL_0_DATA_HI … #define regRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX … #define regRLC_RLCG_DOORBELL_1_DATA_LO … #define regRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX … #define regRLC_RLCG_DOORBELL_1_DATA_HI … #define regRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX … #define regRLC_RLCG_DOORBELL_2_DATA_LO … #define regRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX … #define regRLC_RLCG_DOORBELL_2_DATA_HI … #define regRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX … #define regRLC_RLCG_DOORBELL_3_DATA_LO … #define regRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX … #define regRLC_RLCG_DOORBELL_3_DATA_HI … #define regRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX … #define regRLC_GPU_CLOCK_32_RES_SEL … #define regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX … #define regRLC_GPU_CLOCK_32 … #define regRLC_GPU_CLOCK_32_BASE_IDX … #define regRLC_PG_CNTL … #define regRLC_PG_CNTL_BASE_IDX … #define regRLC_GPM_THREAD_PRIORITY … #define regRLC_GPM_THREAD_PRIORITY_BASE_IDX … #define regRLC_GPM_THREAD_ENABLE … #define regRLC_GPM_THREAD_ENABLE_BASE_IDX … #define regRLC_RLCG_DOORBELL_RANGE … #define regRLC_RLCG_DOORBELL_RANGE_BASE_IDX … #define regRLC_CGTT_MGCG_OVERRIDE … #define regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX … #define regRLC_CGCG_CGLS_CTRL … #define regRLC_CGCG_CGLS_CTRL_BASE_IDX … #define regRLC_CGCG_RAMP_CTRL … #define regRLC_CGCG_RAMP_CTRL_BASE_IDX … #define regRLC_DYN_PG_STATUS … #define regRLC_DYN_PG_STATUS_BASE_IDX … #define regRLC_DYN_PG_REQUEST … #define regRLC_DYN_PG_REQUEST_BASE_IDX … #define regRLC_PG_DELAY … #define regRLC_PG_DELAY_BASE_IDX … #define regRLC_PG_ALWAYS_ON_WGP_MASK … #define regRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX … #define regRLC_MAX_PG_WGP … #define regRLC_MAX_PG_WGP_BASE_IDX … #define regRLC_AUTO_PG_CTRL … #define regRLC_AUTO_PG_CTRL_BASE_IDX … #define regRLC_SERDES_RD_INDEX … #define regRLC_SERDES_RD_INDEX_BASE_IDX … #define regRLC_SERDES_RD_DATA_0 … #define regRLC_SERDES_RD_DATA_0_BASE_IDX … #define regRLC_SERDES_RD_DATA_1 … #define regRLC_SERDES_RD_DATA_1_BASE_IDX … #define regRLC_SERDES_RD_DATA_2 … #define regRLC_SERDES_RD_DATA_2_BASE_IDX … #define regRLC_SERDES_RD_DATA_3 … #define regRLC_SERDES_RD_DATA_3_BASE_IDX … #define regRLC_SERDES_MASK … #define regRLC_SERDES_MASK_BASE_IDX … #define regRLC_SERDES_CTRL … #define regRLC_SERDES_CTRL_BASE_IDX … #define regRLC_SERDES_DATA … #define regRLC_SERDES_DATA_BASE_IDX … #define regRLC_SERDES_BUSY … #define regRLC_SERDES_BUSY_BASE_IDX … #define regRLC_GPM_GENERAL_0 … #define regRLC_GPM_GENERAL_0_BASE_IDX … #define regRLC_GPM_GENERAL_1 … #define regRLC_GPM_GENERAL_1_BASE_IDX … #define regRLC_GPM_GENERAL_2 … #define regRLC_GPM_GENERAL_2_BASE_IDX … #define regRLC_GPM_GENERAL_3 … #define regRLC_GPM_GENERAL_3_BASE_IDX … #define regRLC_GPM_GENERAL_4 … #define regRLC_GPM_GENERAL_4_BASE_IDX … #define regRLC_GPM_GENERAL_5 … #define regRLC_GPM_GENERAL_5_BASE_IDX … #define regRLC_GPM_GENERAL_6 … #define regRLC_GPM_GENERAL_6_BASE_IDX … #define regRLC_GPM_GENERAL_7 … #define regRLC_GPM_GENERAL_7_BASE_IDX … #define regRLC_STATIC_PG_STATUS … #define regRLC_STATIC_PG_STATUS_BASE_IDX … #define regRLC_GPM_GENERAL_16 … #define regRLC_GPM_GENERAL_16_BASE_IDX … #define regRLC_PG_DELAY_3 … #define regRLC_PG_DELAY_3_BASE_IDX … #define regRLC_GPR_REG1 … #define regRLC_GPR_REG1_BASE_IDX … #define regRLC_GPR_REG2 … #define regRLC_GPR_REG2_BASE_IDX … #define regRLC_GPM_INT_DISABLE_TH0 … #define regRLC_GPM_INT_DISABLE_TH0_BASE_IDX … #define regRLC_GPM_LEGACY_INT_DISABLE … #define regRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX … #define regRLC_GPM_INT_FORCE_TH0 … #define regRLC_GPM_INT_FORCE_TH0_BASE_IDX … #define regRLC_SRM_CNTL … #define regRLC_SRM_CNTL_BASE_IDX … #define regRLC_SRM_GPM_COMMAND_STATUS … #define regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_ADDR_0 … #define regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_ADDR_1 … #define regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_ADDR_2 … #define regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_ADDR_3 … #define regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_ADDR_4 … #define regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_ADDR_5 … #define regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_ADDR_6 … #define regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_ADDR_7 … #define regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_DATA_0 … #define regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_DATA_1 … #define regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_DATA_2 … #define regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_DATA_3 … #define regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_DATA_4 … #define regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_DATA_5 … #define regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_DATA_6 … #define regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX … #define regRLC_SRM_INDEX_CNTL_DATA_7 … #define regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX … #define regRLC_SRM_STAT … #define regRLC_SRM_STAT_BASE_IDX … #define regRLC_LX6_UTCL1_ERROR_2 … #define regRLC_LX6_UTCL1_ERROR_2_BASE_IDX … #define regRLC_GPM_GENERAL_8 … #define regRLC_GPM_GENERAL_8_BASE_IDX … #define regRLC_GPM_GENERAL_9 … #define regRLC_GPM_GENERAL_9_BASE_IDX … #define regRLC_GPM_GENERAL_10 … #define regRLC_GPM_GENERAL_10_BASE_IDX … #define regRLC_GPM_GENERAL_11 … #define regRLC_GPM_GENERAL_11_BASE_IDX … #define regRLC_GPM_GENERAL_12 … #define regRLC_GPM_GENERAL_12_BASE_IDX … #define regRLC_GPM_UTCL1_CNTL_0 … #define regRLC_GPM_UTCL1_CNTL_0_BASE_IDX … #define regRLC_SPM_UTCL1_CNTL … #define regRLC_SPM_UTCL1_CNTL_BASE_IDX … #define regRLC_UTCL1_STATUS_2 … #define regRLC_UTCL1_STATUS_2_BASE_IDX … #define regRLC_SPM_UTCL1_ERROR_1 … #define regRLC_SPM_UTCL1_ERROR_1_BASE_IDX … #define regRLC_SPM_UTCL1_ERROR_2 … #define regRLC_SPM_UTCL1_ERROR_2_BASE_IDX … #define regRLC_GPM_UTCL1_TH0_ERROR_1 … #define regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX … #define regRLC_GPM_UTCL1_TH0_ERROR_2 … #define regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX … #define regRLC_CGCG_CGLS_CTRL_3D … #define regRLC_CGCG_CGLS_CTRL_3D_BASE_IDX … #define regRLC_CGCG_RAMP_CTRL_3D … #define regRLC_CGCG_RAMP_CTRL_3D_BASE_IDX … #define regRLC_SEMAPHORE_0 … #define regRLC_SEMAPHORE_0_BASE_IDX … #define regRLC_SEMAPHORE_1 … #define regRLC_SEMAPHORE_1_BASE_IDX … #define regRLC_SEMAPHORE_2 … #define regRLC_SEMAPHORE_2_BASE_IDX … #define regRLC_SEMAPHORE_3 … #define regRLC_SEMAPHORE_3_BASE_IDX … #define regRLC_SRM_UTCL1_CNTL … #define regRLC_SRM_UTCL1_CNTL_BASE_IDX … #define regRLC_SRM_UTCL1_ERROR_1 … #define regRLC_SRM_UTCL1_ERROR_1_BASE_IDX … #define regRLC_SRM_UTCL1_ERROR_2 … #define regRLC_SRM_UTCL1_ERROR_2_BASE_IDX … #define regRLC_UTCL1_STATUS … #define regRLC_UTCL1_STATUS_BASE_IDX … #define regRLC_R2I_CNTL_0 … #define regRLC_R2I_CNTL_0_BASE_IDX … #define regRLC_R2I_CNTL_1 … #define regRLC_R2I_CNTL_1_BASE_IDX … #define regRLC_R2I_CNTL_2 … #define regRLC_R2I_CNTL_2_BASE_IDX … #define regRLC_R2I_CNTL_3 … #define regRLC_R2I_CNTL_3_BASE_IDX … #define regRLC_GPM_INT_STAT_TH0 … #define regRLC_GPM_INT_STAT_TH0_BASE_IDX … #define regRLC_GPM_GENERAL_13 … #define regRLC_GPM_GENERAL_13_BASE_IDX … #define regRLC_GPM_GENERAL_14 … #define regRLC_GPM_GENERAL_14_BASE_IDX … #define regRLC_GPM_GENERAL_15 … #define regRLC_GPM_GENERAL_15_BASE_IDX … #define regRLC_LX6_UTCL1_ERROR_1 … #define regRLC_LX6_UTCL1_ERROR_1_BASE_IDX … #define regRLC_LX6_UTCL1_CNTL … #define regRLC_LX6_UTCL1_CNTL_BASE_IDX … #define regRLC_CAPTURE_GPU_CLOCK_COUNT_1 … #define regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX … #define regRLC_GPU_CLOCK_COUNT_LSB_2 … #define regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX … #define regRLC_GPU_CLOCK_COUNT_MSB_2 … #define regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX … #define regRLC_CAPTURE_GPU_CLOCK_COUNT_2 … #define regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX … #define regRLC_GPU_CLOCK_COUNT_LSB_1 … #define regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX … #define regRLC_GPU_CLOCK_COUNT_MSB_1 … #define regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX … #define regRLC_RLCV_SPARE_INT … #define regRLC_RLCV_SPARE_INT_BASE_IDX … #define regRLC_SMU_CLK_REQ … #define regRLC_SMU_CLK_REQ_BASE_IDX … #define regRLC_SPARE … #define regRLC_SPARE_BASE_IDX … #define regRLC_SPP_CTRL … #define regRLC_SPP_CTRL_BASE_IDX … #define regRLC_SPP_SHADER_PROFILE_EN … #define regRLC_SPP_SHADER_PROFILE_EN_BASE_IDX … #define regRLC_SPP_SSF_CAPTURE_EN … #define regRLC_SPP_SSF_CAPTURE_EN_BASE_IDX … #define regRLC_SPP_SSF_THRESHOLD_0 … #define regRLC_SPP_SSF_THRESHOLD_0_BASE_IDX … #define regRLC_SPP_SSF_THRESHOLD_1 … #define regRLC_SPP_SSF_THRESHOLD_1_BASE_IDX … #define regRLC_SPP_SSF_THRESHOLD_2 … #define regRLC_SPP_SSF_THRESHOLD_2_BASE_IDX … #define regRLC_SPP_INFLIGHT_RD_ADDR … #define regRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX … #define regRLC_SPP_INFLIGHT_RD_DATA … #define regRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX … #define regRLC_SPP_PROF_INFO_1 … #define regRLC_SPP_PROF_INFO_1_BASE_IDX … #define regRLC_SPP_PROF_INFO_2 … #define regRLC_SPP_PROF_INFO_2_BASE_IDX … #define regRLC_SPP_GLOBAL_SH_ID … #define regRLC_SPP_GLOBAL_SH_ID_BASE_IDX … #define regRLC_SPP_GLOBAL_SH_ID_VALID … #define regRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX … #define regRLC_SPP_STATUS … #define regRLC_SPP_STATUS_BASE_IDX … #define regRLC_SPP_PVT_STAT_0 … #define regRLC_SPP_PVT_STAT_0_BASE_IDX … #define regRLC_SPP_PVT_STAT_1 … #define regRLC_SPP_PVT_STAT_1_BASE_IDX … #define regRLC_SPP_PVT_STAT_2 … #define regRLC_SPP_PVT_STAT_2_BASE_IDX … #define regRLC_SPP_PVT_STAT_3 … #define regRLC_SPP_PVT_STAT_3_BASE_IDX … #define regRLC_SPP_PVT_LEVEL_MAX … #define regRLC_SPP_PVT_LEVEL_MAX_BASE_IDX … #define regRLC_SPP_STALL_STATE_UPDATE … #define regRLC_SPP_STALL_STATE_UPDATE_BASE_IDX … #define regRLC_SPP_PBB_INFO … #define regRLC_SPP_PBB_INFO_BASE_IDX … #define regRLC_SPP_RESET … #define regRLC_SPP_RESET_BASE_IDX … #define regRLC_CAC_MASK_CNTL … #define regRLC_CAC_MASK_CNTL_BASE_IDX … #define regRLC_POWER_RESIDENCY_CNTR_CTRL … #define regRLC_POWER_RESIDENCY_CNTR_CTRL_BASE_IDX … #define regRLC_CLK_RESIDENCY_CNTR_CTRL … #define regRLC_CLK_RESIDENCY_CNTR_CTRL_BASE_IDX … #define regRLC_DS_RESIDENCY_CNTR_CTRL … #define regRLC_DS_RESIDENCY_CNTR_CTRL_BASE_IDX … #define regRLC_ULV_RESIDENCY_CNTR_CTRL … #define regRLC_ULV_RESIDENCY_CNTR_CTRL_BASE_IDX … #define regRLC_PCC_RESIDENCY_CNTR_CTRL … #define regRLC_PCC_RESIDENCY_CNTR_CTRL_BASE_IDX … #define regRLC_GENERAL_RESIDENCY_CNTR_CTRL … #define regRLC_GENERAL_RESIDENCY_CNTR_CTRL_BASE_IDX … #define regRLC_POWER_RESIDENCY_EVENT_CNTR … #define regRLC_POWER_RESIDENCY_EVENT_CNTR_BASE_IDX … #define regRLC_CLK_RESIDENCY_EVENT_CNTR … #define regRLC_CLK_RESIDENCY_EVENT_CNTR_BASE_IDX … #define regRLC_DS_RESIDENCY_EVENT_CNTR … #define regRLC_DS_RESIDENCY_EVENT_CNTR_BASE_IDX … #define regRLC_ULV_RESIDENCY_EVENT_CNTR … #define regRLC_ULV_RESIDENCY_EVENT_CNTR_BASE_IDX … #define regRLC_PCC_RESIDENCY_EVENT_CNTR … #define regRLC_PCC_RESIDENCY_EVENT_CNTR_BASE_IDX … #define regRLC_GENERAL_RESIDENCY_EVENT_CNTR … #define regRLC_GENERAL_RESIDENCY_EVENT_CNTR_BASE_IDX … #define regRLC_POWER_RESIDENCY_REF_CNTR … #define regRLC_POWER_RESIDENCY_REF_CNTR_BASE_IDX … #define regRLC_CLK_RESIDENCY_REF_CNTR … #define regRLC_CLK_RESIDENCY_REF_CNTR_BASE_IDX … #define regRLC_DS_RESIDENCY_REF_CNTR … #define regRLC_DS_RESIDENCY_REF_CNTR_BASE_IDX … #define regRLC_ULV_RESIDENCY_REF_CNTR … #define regRLC_ULV_RESIDENCY_REF_CNTR_BASE_IDX … #define regRLC_PCC_RESIDENCY_REF_CNTR … #define regRLC_PCC_RESIDENCY_REF_CNTR_BASE_IDX … #define regRLC_GENERAL_RESIDENCY_REF_CNTR … #define regRLC_GENERAL_RESIDENCY_REF_CNTR_BASE_IDX … #define regRLC_GFX_IH_CLIENT_CTRL … #define regRLC_GFX_IH_CLIENT_CTRL_BASE_IDX … #define regRLC_GFX_IH_ARBITER_STAT … #define regRLC_GFX_IH_ARBITER_STAT_BASE_IDX … #define regRLC_GFX_IH_CLIENT_SE_STAT_L … #define regRLC_GFX_IH_CLIENT_SE_STAT_L_BASE_IDX … #define regRLC_GFX_IH_CLIENT_SE_STAT_H … #define regRLC_GFX_IH_CLIENT_SE_STAT_H_BASE_IDX … #define regRLC_GFX_IH_CLIENT_SDMA_STAT … #define regRLC_GFX_IH_CLIENT_SDMA_STAT_BASE_IDX … #define regRLC_GFX_IH_CLIENT_OTHER_STAT … #define regRLC_GFX_IH_CLIENT_OTHER_STAT_BASE_IDX … #define regRLC_SPM_GLOBAL_DELAY_IND_ADDR … #define regRLC_SPM_GLOBAL_DELAY_IND_ADDR_BASE_IDX … #define regRLC_SPM_GLOBAL_DELAY_IND_DATA … #define regRLC_SPM_GLOBAL_DELAY_IND_DATA_BASE_IDX … #define regRLC_SPM_SE_DELAY_IND_ADDR … #define regRLC_SPM_SE_DELAY_IND_ADDR_BASE_IDX … #define regRLC_SPM_SE_DELAY_IND_DATA … #define regRLC_SPM_SE_DELAY_IND_DATA_BASE_IDX … #define regRLC_SPM_SE_BLK_EN_MASK_IND_ADDR … #define regRLC_SPM_SE_BLK_EN_MASK_IND_ADDR_BASE_IDX … #define regRLC_SPM_SE_BLK_EN_MASK_IND_DATA … #define regRLC_SPM_SE_BLK_EN_MASK_IND_DATA_BASE_IDX … #define regRLC_LX6_CNTL … #define regRLC_LX6_CNTL_BASE_IDX … #define regRLC_LX6_STATUS … #define regRLC_LX6_STATUS_BASE_IDX … #define regRLC_LX6_FW_STATUS … #define regRLC_LX6_FW_STATUS_BASE_IDX … #define regRLC_LX6_FW_VERSION … #define regRLC_LX6_FW_VERSION_BASE_IDX … #define regRLC_XT_CORE_STATUS … #define regRLC_XT_CORE_STATUS_BASE_IDX … #define regRLC_XT_CORE_INTERRUPT … #define regRLC_XT_CORE_INTERRUPT_BASE_IDX … #define regRLC_XT_CORE_FAULT_INFO … #define regRLC_XT_CORE_FAULT_INFO_BASE_IDX … #define regRLC_XT_CORE_ALT_RESET_VEC … #define regRLC_XT_CORE_ALT_RESET_VEC_BASE_IDX … #define regRLC_XT_CORE_RESERVED … #define regRLC_XT_CORE_RESERVED_BASE_IDX … #define regRLC_XT_INT_VEC_FORCE … #define regRLC_XT_INT_VEC_FORCE_BASE_IDX … #define regRLC_XT_INT_VEC_CLEAR … #define regRLC_XT_INT_VEC_CLEAR_BASE_IDX … #define regRLC_XT_INT_VEC_MUX_SEL … #define regRLC_XT_INT_VEC_MUX_SEL_BASE_IDX … #define regRLC_XT_INT_VEC_MUX_INT_SEL … #define regRLC_XT_INT_VEC_MUX_INT_SEL_BASE_IDX … #define regRLC_GPU_CLOCK_COUNT_SPM_LSB … #define regRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX … #define regRLC_GPU_CLOCK_COUNT_SPM_MSB … #define regRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX … #define regRLC_SPM_THREAD_TRACE_CTRL … #define regRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX … #define regRLC_SPP_CAM_ADDR … #define regRLC_SPP_CAM_ADDR_BASE_IDX … #define regRLC_SPP_CAM_DATA … #define regRLC_SPP_CAM_DATA_BASE_IDX … #define regRLC_SPP_CAM_EXT_ADDR … #define regRLC_SPP_CAM_EXT_ADDR_BASE_IDX … #define regRLC_SPP_CAM_EXT_DATA … #define regRLC_SPP_CAM_EXT_DATA_BASE_IDX … #define regRLC_CPAXI_DOORBELL_MON_CTRL … #define regRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX … #define regRLC_CPAXI_DOORBELL_MON_STAT … #define regRLC_CPAXI_DOORBELL_MON_STAT_BASE_IDX … #define regRLC_CPAXI_DOORBELL_MON_DATA_LSB … #define regRLC_CPAXI_DOORBELL_MON_DATA_LSB_BASE_IDX … #define regRLC_CPAXI_DOORBELL_MON_DATA_MSB … #define regRLC_CPAXI_DOORBELL_MON_DATA_MSB_BASE_IDX … #define regRLC_XT_DOORBELL_RANGE … #define regRLC_XT_DOORBELL_RANGE_BASE_IDX … #define regRLC_XT_DOORBELL_CNTL … #define regRLC_XT_DOORBELL_CNTL_BASE_IDX … #define regRLC_XT_DOORBELL_STAT … #define regRLC_XT_DOORBELL_STAT_BASE_IDX … #define regRLC_XT_DOORBELL_0_DATA_LO … #define regRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX … #define regRLC_XT_DOORBELL_0_DATA_HI … #define regRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX … #define regRLC_XT_DOORBELL_1_DATA_LO … #define regRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX … #define regRLC_XT_DOORBELL_1_DATA_HI … #define regRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX … #define regRLC_XT_DOORBELL_2_DATA_LO … #define regRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX … #define regRLC_XT_DOORBELL_2_DATA_HI … #define regRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX … #define regRLC_XT_DOORBELL_3_DATA_LO … #define regRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX … #define regRLC_XT_DOORBELL_3_DATA_HI … #define regRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX … #define regRLC_MEM_SLP_CNTL … #define regRLC_MEM_SLP_CNTL_BASE_IDX … #define regRLC_RLCV_SAFE_MODE … #define regRLC_RLCV_SAFE_MODE_BASE_IDX … #define regRLC_SMU_SAFE_MODE … #define regRLC_SMU_SAFE_MODE_BASE_IDX … #define regRLC_RLCV_COMMAND … #define regRLC_RLCV_COMMAND_BASE_IDX … #define regRLC_SMU_MESSAGE … #define regRLC_SMU_MESSAGE_BASE_IDX … #define regRLC_SMU_MESSAGE_1 … #define regRLC_SMU_MESSAGE_1_BASE_IDX … #define regRLC_SMU_MESSAGE_2 … #define regRLC_SMU_MESSAGE_2_BASE_IDX … #define regRLC_SRM_GPM_COMMAND … #define regRLC_SRM_GPM_COMMAND_BASE_IDX … #define regRLC_SRM_GPM_ABORT … #define regRLC_SRM_GPM_ABORT_BASE_IDX … #define regRLC_SMU_COMMAND … #define regRLC_SMU_COMMAND_BASE_IDX … #define regRLC_SMU_ARGUMENT_1 … #define regRLC_SMU_ARGUMENT_1_BASE_IDX … #define regRLC_SMU_ARGUMENT_2 … #define regRLC_SMU_ARGUMENT_2_BASE_IDX … #define regRLC_SMU_ARGUMENT_3 … #define regRLC_SMU_ARGUMENT_3_BASE_IDX … #define regRLC_SMU_ARGUMENT_4 … #define regRLC_SMU_ARGUMENT_4_BASE_IDX … #define regRLC_SMU_ARGUMENT_5 … #define regRLC_SMU_ARGUMENT_5_BASE_IDX … #define regRLC_IMU_BOOTLOAD_ADDR_HI … #define regRLC_IMU_BOOTLOAD_ADDR_HI_BASE_IDX … #define regRLC_IMU_BOOTLOAD_ADDR_LO … #define regRLC_IMU_BOOTLOAD_ADDR_LO_BASE_IDX … #define regRLC_IMU_BOOTLOAD_SIZE … #define regRLC_IMU_BOOTLOAD_SIZE_BASE_IDX … #define regRLC_IMU_MISC … #define regRLC_IMU_MISC_BASE_IDX … #define regRLC_IMU_RESET_VECTOR … #define regRLC_IMU_RESET_VECTOR_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_rlcsdec // base address: 0x3b980 #define regRLC_RLCS_DEC_START … #define regRLC_RLCS_DEC_START_BASE_IDX … #define regRLC_RLCS_DEC_DUMP_ADDR … #define regRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX … #define regRLC_RLCS_EXCEPTION_REG_1 … #define regRLC_RLCS_EXCEPTION_REG_1_BASE_IDX … #define regRLC_RLCS_EXCEPTION_REG_2 … #define regRLC_RLCS_EXCEPTION_REG_2_BASE_IDX … #define regRLC_RLCS_EXCEPTION_REG_3 … #define regRLC_RLCS_EXCEPTION_REG_3_BASE_IDX … #define regRLC_RLCS_EXCEPTION_REG_4 … #define regRLC_RLCS_EXCEPTION_REG_4_BASE_IDX … #define regRLC_RLCS_CGCG_REQUEST … #define regRLC_RLCS_CGCG_REQUEST_BASE_IDX … #define regRLC_RLCS_CGCG_STATUS … #define regRLC_RLCS_CGCG_STATUS_BASE_IDX … #define regRLC_RLCS_SOC_DS_CNTL … #define regRLC_RLCS_SOC_DS_CNTL_BASE_IDX … #define regRLC_RLCS_GFX_DS_CNTL … #define regRLC_RLCS_GFX_DS_CNTL_BASE_IDX … #define regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL … #define regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_BASE_IDX … #define regRLC_GPM_STAT … #define regRLC_GPM_STAT_BASE_IDX … #define regRLC_RLCS_GPM_STAT … #define regRLC_RLCS_GPM_STAT_BASE_IDX … #define regRLC_RLCS_ABORTED_PD_SEQUENCE … #define regRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX … #define regRLC_RLCS_GPM_STAT_2 … #define regRLC_RLCS_GPM_STAT_2_BASE_IDX … #define regRLC_RLCS_GRBM_SOFT_RESET … #define regRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX … #define regRLC_RLCS_PG_CHANGE_STATUS … #define regRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX … #define regRLC_RLCS_PG_CHANGE_READ … #define regRLC_RLCS_PG_CHANGE_READ_BASE_IDX … #define regRLC_RLCS_IH_SEMAPHORE … #define regRLC_RLCS_IH_SEMAPHORE_BASE_IDX … #define regRLC_RLCS_IH_COOKIE_SEMAPHORE … #define regRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX … #define regRLC_RLCS_CP_INT_CTRL_1 … #define regRLC_RLCS_CP_INT_CTRL_1_BASE_IDX … #define regRLC_RLCS_CP_INT_CTRL_2 … #define regRLC_RLCS_CP_INT_CTRL_2_BASE_IDX … #define regRLC_RLCS_CP_INT_INFO_1 … #define regRLC_RLCS_CP_INT_INFO_1_BASE_IDX … #define regRLC_RLCS_CP_INT_INFO_2 … #define regRLC_RLCS_CP_INT_INFO_2_BASE_IDX … #define regRLC_RLCS_SPM_INT_CTRL … #define regRLC_RLCS_SPM_INT_CTRL_BASE_IDX … #define regRLC_RLCS_SPM_INT_INFO_1 … #define regRLC_RLCS_SPM_INT_INFO_1_BASE_IDX … #define regRLC_RLCS_SPM_INT_INFO_2 … #define regRLC_RLCS_SPM_INT_INFO_2_BASE_IDX … #define regRLC_RLCS_DSM_TRIG … #define regRLC_RLCS_BOOTLOAD_STATUS … #define regRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX … #define regRLC_RLCS_GRBM_IDLE_BUSY_STAT … #define regRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX … #define regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL … #define regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX … #define regRLC_RLCS_CMP_IDLE_CNTL … #define regRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX … #define regRLC_RLCS_GENERAL_0 … #define regRLC_RLCS_GENERAL_0_BASE_IDX … #define regRLC_RLCS_GENERAL_1 … #define regRLC_RLCS_GENERAL_1_BASE_IDX … #define regRLC_RLCS_GENERAL_2 … #define regRLC_RLCS_GENERAL_2_BASE_IDX … #define regRLC_RLCS_GENERAL_3 … #define regRLC_RLCS_GENERAL_3_BASE_IDX … #define regRLC_RLCS_GENERAL_4 … #define regRLC_RLCS_GENERAL_4_BASE_IDX … #define regRLC_RLCS_GENERAL_5 … #define regRLC_RLCS_GENERAL_5_BASE_IDX … #define regRLC_RLCS_GENERAL_6 … #define regRLC_RLCS_GENERAL_6_BASE_IDX … #define regRLC_RLCS_GENERAL_7 … #define regRLC_RLCS_GENERAL_7_BASE_IDX … #define regRLC_RLCS_GENERAL_8 … #define regRLC_RLCS_GENERAL_8_BASE_IDX … #define regRLC_RLCS_GENERAL_9 … #define regRLC_RLCS_GENERAL_9_BASE_IDX … #define regRLC_RLCS_GENERAL_10 … #define regRLC_RLCS_GENERAL_10_BASE_IDX … #define regRLC_RLCS_GENERAL_11 … #define regRLC_RLCS_GENERAL_11_BASE_IDX … #define regRLC_RLCS_GENERAL_12 … #define regRLC_RLCS_GENERAL_12_BASE_IDX … #define regRLC_RLCS_GENERAL_13 … #define regRLC_RLCS_GENERAL_13_BASE_IDX … #define regRLC_RLCS_GENERAL_14 … #define regRLC_RLCS_GENERAL_14_BASE_IDX … #define regRLC_RLCS_GENERAL_15 … #define regRLC_RLCS_GENERAL_15_BASE_IDX … #define regRLC_RLCS_GENERAL_16 … #define regRLC_RLCS_GENERAL_16_BASE_IDX … #define regRLC_RLCS_AUXILIARY_REG_1 … #define regRLC_RLCS_AUXILIARY_REG_1_BASE_IDX … #define regRLC_RLCS_AUXILIARY_REG_2 … #define regRLC_RLCS_AUXILIARY_REG_2_BASE_IDX … #define regRLC_RLCS_AUXILIARY_REG_3 … #define regRLC_RLCS_AUXILIARY_REG_3_BASE_IDX … #define regRLC_RLCS_AUXILIARY_REG_4 … #define regRLC_RLCS_AUXILIARY_REG_4_BASE_IDX … #define regRLC_RLCS_SPM_SQTT_MODE … #define regRLC_RLCS_SPM_SQTT_MODE_BASE_IDX … #define regRLC_RLCS_CP_DMA_SRCID_OVER … #define regRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX … #define regRLC_RLCS_BOOTLOAD_ID_STATUS1 … #define regRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX … #define regRLC_RLCS_BOOTLOAD_ID_STATUS2 … #define regRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX … #define regRLC_RLCS_IMU_VIDCHG_CNTL … #define regRLC_RLCS_IMU_VIDCHG_CNTL_BASE_IDX … #define regRLC_RLCS_KMD_LOG_CNTL1 … #define regRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX … #define regRLC_RLCS_KMD_LOG_CNTL2 … #define regRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX … #define regRLC_RLCS_GPM_LEGACY_INT_STAT … #define regRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX … #define regRLC_RLCS_GPM_LEGACY_INT_DISABLE … #define regRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX … #define regRLC_RLCS_GCR_DATA_0 … #define regRLC_RLCS_GCR_DATA_0_BASE_IDX … #define regRLC_RLCS_GCR_DATA_1 … #define regRLC_RLCS_GCR_DATA_1_BASE_IDX … #define regRLC_RLCS_GCR_DATA_2 … #define regRLC_RLCS_GCR_DATA_2_BASE_IDX … #define regRLC_RLCS_GCR_DATA_3 … #define regRLC_RLCS_GCR_DATA_3_BASE_IDX … #define regRLC_RLCS_GCR_STATUS … #define regRLC_RLCS_GCR_STATUS_BASE_IDX … #define regRLC_RLCS_PERFMON_CLK_CNTL_UCODE … #define regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX … #define regRLC_RLCS_UTCL2_CNTL … #define regRLC_RLCS_UTCL2_CNTL_BASE_IDX … #define regRLC_RLCS_IMU_RLC_MSG_DATA0 … #define regRLC_RLCS_IMU_RLC_MSG_DATA0_BASE_IDX … #define regRLC_RLCS_IMU_RLC_MSG_DATA1 … #define regRLC_RLCS_IMU_RLC_MSG_DATA1_BASE_IDX … #define regRLC_RLCS_IMU_RLC_MSG_DATA2 … #define regRLC_RLCS_IMU_RLC_MSG_DATA2_BASE_IDX … #define regRLC_RLCS_IMU_RLC_MSG_DATA3 … #define regRLC_RLCS_IMU_RLC_MSG_DATA3_BASE_IDX … #define regRLC_RLCS_IMU_RLC_MSG_DATA4 … #define regRLC_RLCS_IMU_RLC_MSG_DATA4_BASE_IDX … #define regRLC_RLCS_IMU_RLC_MSG_CONTROL … #define regRLC_RLCS_IMU_RLC_MSG_CONTROL_BASE_IDX … #define regRLC_RLCS_IMU_RLC_MSG_CNTL … #define regRLC_RLCS_IMU_RLC_MSG_CNTL_BASE_IDX … #define regRLC_RLCS_RLC_IMU_MSG_DATA0 … #define regRLC_RLCS_RLC_IMU_MSG_DATA0_BASE_IDX … #define regRLC_RLCS_RLC_IMU_MSG_CONTROL … #define regRLC_RLCS_RLC_IMU_MSG_CONTROL_BASE_IDX … #define regRLC_RLCS_RLC_IMU_MSG_CNTL … #define regRLC_RLCS_RLC_IMU_MSG_CNTL_BASE_IDX … #define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0 … #define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_0_BASE_IDX … #define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1 … #define regRLC_RLCS_IMU_RLC_TELEMETRY_DATA_1_BASE_IDX … #define regRLC_RLCS_IMU_RLC_MUTEX_CNTL … #define regRLC_RLCS_IMU_RLC_MUTEX_CNTL_BASE_IDX … #define regRLC_RLCS_IMU_RLC_STATUS … #define regRLC_RLCS_IMU_RLC_STATUS_BASE_IDX … #define regRLC_RLCS_RLC_IMU_STATUS … #define regRLC_RLCS_RLC_IMU_STATUS_BASE_IDX … #define regRLC_RLCS_IMU_RAM_DATA_1 … #define regRLC_RLCS_IMU_RAM_DATA_1_BASE_IDX … #define regRLC_RLCS_IMU_RAM_ADDR_1_LSB … #define regRLC_RLCS_IMU_RAM_ADDR_1_LSB_BASE_IDX … #define regRLC_RLCS_IMU_RAM_ADDR_1_MSB … #define regRLC_RLCS_IMU_RAM_ADDR_1_MSB_BASE_IDX … #define regRLC_RLCS_IMU_RAM_DATA_0 … #define regRLC_RLCS_IMU_RAM_DATA_0_BASE_IDX … #define regRLC_RLCS_IMU_RAM_ADDR_0_LSB … #define regRLC_RLCS_IMU_RAM_ADDR_0_LSB_BASE_IDX … #define regRLC_RLCS_IMU_RAM_ADDR_0_MSB … #define regRLC_RLCS_IMU_RAM_ADDR_0_MSB_BASE_IDX … #define regRLC_RLCS_IMU_RAM_CNTL … #define regRLC_RLCS_IMU_RAM_CNTL_BASE_IDX … #define regRLC_RLCS_IMU_GFX_DOORBELL_FENCE … #define regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_BASE_IDX … #define regRLC_RLCS_SDMA_INT_CNTL_1 … #define regRLC_RLCS_SDMA_INT_CNTL_1_BASE_IDX … #define regRLC_RLCS_SDMA_INT_CNTL_2 … #define regRLC_RLCS_SDMA_INT_CNTL_2_BASE_IDX … #define regRLC_RLCS_SDMA_INT_STAT … #define regRLC_RLCS_SDMA_INT_STAT_BASE_IDX … #define regRLC_RLCS_SDMA_INT_INFO … #define regRLC_RLCS_SDMA_INT_INFO_BASE_IDX … #define regRLC_RLCS_GFX_MEM_POWER_CTRL_0 … #define regRLC_RLCS_GFX_MEM_POWER_CTRL_0_BASE_IDX … #define regRLC_RLCS_GFX_MEM_POWER_CTRL_1 … #define regRLC_RLCS_GFX_MEM_POWER_CTRL_1_BASE_IDX … #define regRLC_RLCS_GFX_MEM_POWER_CTRL_2 … #define regRLC_RLCS_GFX_MEM_POWER_CTRL_2_BASE_IDX … #define regRLC_RLCS_SE_PWR_CTRL … #define regRLC_RLCS_SE_PWR_CTRL_BASE_IDX … #define regRLC_RLCS_UTCL2_BUSY_CNTL … #define regRLC_RLCS_UTCL2_BUSY_CNTL_BASE_IDX … #define regRLC_RLCS_UTCL2_BUSY_STAT … #define regRLC_RLCS_UTCL2_BUSY_STAT_BASE_IDX … #define regRLC_RLCS_DEC_END … #define regRLC_RLCS_DEC_END_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_pfvfdec_rlc // base address: 0x2a600 #define regRLC_SAFE_MODE … #define regRLC_SAFE_MODE_BASE_IDX … #define regRLC_SPM_SAMPLE_CNT … #define regRLC_SPM_SAMPLE_CNT_BASE_IDX … #define regRLC_SPM_MC_CNTL … #define regRLC_SPM_MC_CNTL_BASE_IDX … #define regRLC_SPM_INT_CNTL … #define regRLC_SPM_INT_CNTL_BASE_IDX … #define regRLC_SPM_INT_STATUS … #define regRLC_SPM_INT_STATUS_BASE_IDX … #define regRLC_SPM_INT_INFO_1 … #define regRLC_SPM_INT_INFO_1_BASE_IDX … #define regRLC_SPM_INT_INFO_2 … #define regRLC_SPM_INT_INFO_2_BASE_IDX … #define regRLC_CSIB_ADDR_LO … #define regRLC_CSIB_ADDR_LO_BASE_IDX … #define regRLC_CSIB_ADDR_HI … #define regRLC_CSIB_ADDR_HI_BASE_IDX … #define regRLC_CSIB_LENGTH … #define regRLC_CSIB_LENGTH_BASE_IDX … #define regRLC_CP_SCHEDULERS … #define regRLC_CP_SCHEDULERS_BASE_IDX … #define regRLC_CP_EOF_INT … #define regRLC_CP_EOF_INT_BASE_IDX … #define regRLC_CP_EOF_INT_CNTL … #define regRLC_CP_EOF_INT_CNTL_BASE_IDX … #define regRLC_SPARE_INT_0 … #define regRLC_SPARE_INT_0_BASE_IDX … #define regRLC_SPARE_INT_1 … #define regRLC_SPARE_INT_1_BASE_IDX … #define regRLC_SPARE_INT_2 … #define regRLC_SPARE_INT_2_BASE_IDX … #define regRLC_RLCV_SPARE_INT_1 … #define regRLC_RLCV_SPARE_INT_1_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_pwrdec // base address: 0x3c000 #define regCC_GC_GL2C_DISABLE_0 … #define regCC_GC_GL2C_DISABLE_0_BASE_IDX … #define regCC_GC_GL2C_DISABLE_1 … #define regCC_GC_GL2C_DISABLE_1_BASE_IDX … #define regCGTT_IA_CLK_CTRL … #define regCGTT_IA_CLK_CTRL_BASE_IDX … #define regCGTT_WD_CLK_CTRL … #define regCGTT_WD_CLK_CTRL_BASE_IDX … #define regGFX_ICG_GL2A_CTRL … #define regGFX_ICG_GL2A_CTRL_BASE_IDX … #define regCGTT_CP_CLK_CTRL … #define regCGTT_CP_CLK_CTRL_BASE_IDX … #define regCGTT_CPF_CLK_CTRL … #define regCGTT_CPF_CLK_CTRL_BASE_IDX … #define regCGTT_CPC_CLK_CTRL … #define regCGTT_CPC_CLK_CTRL_BASE_IDX … #define regCGTT_RLC_CLK_CTRL … #define regCGTT_RLC_CLK_CTRL_BASE_IDX … #define regGFX_ICG_GCR_CTRL … #define regGFX_ICG_GCR_CTRL_BASE_IDX … #define regGC_EA_CPWD_ICG_CTRL … #define regGC_EA_CPWD_ICG_CTRL_BASE_IDX … #define regGFX_ICG_GC_CAC_CLK_CTRL … #define regGFX_ICG_GC_CAC_CLK_CTRL_BASE_IDX … #define regGFX_ICG_GRBM_CTRL … #define regGFX_ICG_GRBM_CTRL_BASE_IDX … #define regGFX_ICG_GL2C_CTRL … #define regGFX_ICG_GL2C_CTRL_BASE_IDX … #define regGFX_ICG_GL2C_CTRL1 … #define regGFX_ICG_GL2C_CTRL1_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_pspdec // base address: 0x3f000 #define regCP_MES_DM_INDEX_ADDR … #define regCP_MES_DM_INDEX_ADDR_BASE_IDX … #define regCP_MES_DM_INDEX_DATA … #define regCP_MES_DM_INDEX_DATA_BASE_IDX … #define regCP_MEC_DM_INDEX_ADDR … #define regCP_MEC_DM_INDEX_ADDR_BASE_IDX … #define regCP_MEC_DM_INDEX_DATA … #define regCP_MEC_DM_INDEX_DATA_BASE_IDX … #define regCP_GFX_RS64_DM_INDEX_ADDR … #define regCP_GFX_RS64_DM_INDEX_ADDR_BASE_IDX … #define regCP_GFX_RS64_DM_INDEX_DATA … #define regCP_GFX_RS64_DM_INDEX_DATA_BASE_IDX … #define regCPG_PSP_DEBUG … #define regCPG_PSP_DEBUG_BASE_IDX … #define regCPC_PSP_DEBUG … #define regCPC_PSP_DEBUG_BASE_IDX … #define regGC_EA_CPWD_SECURE_CTRL … #define regGC_EA_CPWD_SECURE_CTRL_BASE_IDX … #define regGC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0 … #define regGC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0_BASE_IDX … #define regGC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1 … #define regGC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1_BASE_IDX … #define regGC_EA_CPWD_SDP_SECLEVEL_IO_MAP0 … #define regGC_EA_CPWD_SDP_SECLEVEL_IO_MAP0_BASE_IDX … #define regGC_EA_CPWD_SDP_SECLEVEL_IO_MAP1 … #define regGC_EA_CPWD_SDP_SECLEVEL_IO_MAP1_BASE_IDX … #define regGRBM_SEC_CNTL … #define regGRBM_SEC_CNTL_BASE_IDX … #define regGRBM_CAM_INDEX … #define regGRBM_CAM_INDEX_BASE_IDX … #define regGRBM_CAM_DATA … #define regGRBM_CAM_DATA_BASE_IDX … #define regGRBM_CAM_DATA_UPPER … #define regGRBM_CAM_DATA_UPPER_BASE_IDX … #define regRLC_REG_SEC_INT_STATUS … #define regRLC_REG_SEC_INT_STATUS_BASE_IDX … #define regRLC_UTC_BYPASS_CNTL … #define regRLC_UTC_BYPASS_CNTL_BASE_IDX … // addressBlock: gc_gfx_cpwd_cpwd_ch_pwrdec // base address: 0x3c3b0 #define regCHI_CHR_MGCG_OVERRIDE … #define regCHI_CHR_MGCG_OVERRIDE_BASE_IDX … #define regICG_CHA_CTRL … #define regICG_CHA_CTRL_BASE_IDX … #define regICG_CHC_CLK_CTRL … #define regICG_CHC_CLK_CTRL_BASE_IDX … // addressBlock: gc_gfx_cpwd_gfx_imu_cpwd_gfx_imudec // base address: 0x38000 #define regGFX_IMU_C2PMSG_16 … #define regGFX_IMU_C2PMSG_16_BASE_IDX … #define regGFX_IMU_C2PMSG_ACCESS_CTRL0 … #define regGFX_IMU_C2PMSG_ACCESS_CTRL0_BASE_IDX … #define regGFX_IMU_C2PMSG_ACCESS_CTRL1 … #define regGFX_IMU_C2PMSG_ACCESS_CTRL1_BASE_IDX … #define regGFX_IMU_SCRATCH_10 … #define regGFX_IMU_SCRATCH_10_BASE_IDX … #define regGFX_IMU_RLC_RAM_INDEX … #define regGFX_IMU_RLC_RAM_INDEX_BASE_IDX … #define regGFX_IMU_RLC_RAM_ADDR_HIGH … #define regGFX_IMU_RLC_RAM_ADDR_HIGH_BASE_IDX … #define regGFX_IMU_RLC_RAM_ADDR_LOW … #define regGFX_IMU_RLC_RAM_ADDR_LOW_BASE_IDX … #define regGFX_IMU_RLC_RAM_DATA … #define regGFX_IMU_RLC_RAM_DATA_BASE_IDX … #define regGFX_IMU_CORE_CTRL … #define regGFX_IMU_CORE_CTRL_BASE_IDX … #define regGFX_IMU_GFX_RESET_CTRL … #define regGFX_IMU_GFX_RESET_CTRL_BASE_IDX … #define regGFX_IMU_D_RAM_ADDR … #define regGFX_IMU_D_RAM_ADDR_BASE_IDX … #define regGFX_IMU_D_RAM_DATA … #define regGFX_IMU_D_RAM_DATA_BASE_IDX … // addressBlock: gc_gfx_cpwd_gfx_imu_cpwd_gfx_imu_pspdec // base address: 0x3fe00 #define regGFX_IMU_RLC_BOOTLOADER_ADDR_HI … #define regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_BASE_IDX … #define regGFX_IMU_RLC_BOOTLOADER_ADDR_LO … #define regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_BASE_IDX … #define regGFX_IMU_RLC_BOOTLOADER_SIZE … #define regGFX_IMU_RLC_BOOTLOADER_SIZE_BASE_IDX … #define regGFX_IMU_I_RAM_ADDR … #define regGFX_IMU_I_RAM_ADDR_BASE_IDX … #define regGFX_IMU_I_RAM_DATA … #define regGFX_IMU_I_RAM_DATA_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_grbmhdec // base address: 0x8180 #define regGRBMH_CNTL … #define regGRBMH_CNTL_BASE_IDX … #define regGRBMH_INTF_CNTL … #define regGRBMH_INTF_CNTL_BASE_IDX … #define regGRBMH_STATUS … #define regGRBMH_STATUS_BASE_IDX … #define regGRBMH_FGCG0_TARG … #define regGRBMH_FGCG0_TARG_BASE_IDX … #define regGRBMH_SOFT_RESET … #define regGRBMH_SOFT_RESET_BASE_IDX … #define regGRBMH_READ_ERROR … #define regGRBMH_READ_ERROR_BASE_IDX … #define regGRBMH_GFX_CLKEN_CNTL … #define regGRBMH_GFX_CLKEN_CNTL_BASE_IDX … #define regGRBMH_FGCG2_MISC … #define regGRBMH_FGCG2_MISC_BASE_IDX … #define regGRBMH_FGCG1_TARGVF … #define regGRBMH_FGCG1_TARGVF_BASE_IDX … #define regGRBMH_NOWHERE … #define regGRBMH_NOWHERE_BASE_IDX … #define regGRBMH_INVALID_PIPE … #define regGRBMH_INVALID_PIPE_BASE_IDX … #define regGRBMH_SYNC … #define regGRBMH_SYNC_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_padec // base address: 0x8800 #define regGRBMH_CC_GC_SA_UNIT_DISABLE … #define regGRBMH_CC_GC_SA_UNIT_DISABLE_BASE_IDX … #define regCC_GC_SA_UNIT_DISABLE_1 … #define regCC_GC_SA_UNIT_DISABLE_1_BASE_IDX … #define regGE_RATE_CNTL_1 … #define regGE_RATE_CNTL_1_BASE_IDX … #define regGE_RATE_CNTL_2 … #define regGE_RATE_CNTL_2_BASE_IDX … #define regCC_GC_SHADER_ARRAY_CONFIG … #define regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX … #define regGE_SE_CNTL_STATUS … #define regGE_SE_CNTL_STATUS_BASE_IDX … #define regGE_SPI_IF_SAFE_REG … #define regGE_SPI_IF_SAFE_REG_BASE_IDX … #define regGE_PA_IF_SAFE_REG … #define regGE_PA_IF_SAFE_REG_BASE_IDX … #define regPA_SU_DEBUG_CNTL … #define regPA_SU_DEBUG_CNTL_BASE_IDX … #define regPA_CL_CNTL_STATUS … #define regPA_CL_CNTL_STATUS_BASE_IDX … #define regPA_CL_ENHANCE … #define regPA_CL_ENHANCE_BASE_IDX … #define regPA_CL_RESET_DEBUG … #define regPA_CL_RESET_DEBUG_BASE_IDX … #define regPA_SU_CNTL_STATUS … #define regPA_SU_CNTL_STATUS_BASE_IDX … #define regPA_SC_FIFO_DEPTH_CNTL … #define regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX … #define regPA_PH_DEBUG_CNTL … #define regPA_PH_DEBUG_CNTL_BASE_IDX … #define regPA_SC_DEBUG_CNTL … #define regPA_SC_DEBUG_CNTL_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_sqdec // base address: 0x8c00 #define regSQ_CONFIG … #define regSQ_CONFIG_BASE_IDX … #define regSQC_CONFIG … #define regSQC_CONFIG_BASE_IDX … #define regLDS_CONFIG … #define regLDS_CONFIG_BASE_IDX … #define regSQ_RANDOM_WAVE_PRI … #define regSQ_RANDOM_WAVE_PRI_BASE_IDX … #define regSQG_STATUS … #define regSQG_STATUS_BASE_IDX … #define regSQ_FIFO_SIZES … #define regSQ_FIFO_SIZES_BASE_IDX … #define regSQ_DSM_CNTL … #define regSQ_DSM_CNTL_BASE_IDX … #define regSQ_DSM_CNTL2 … #define regSQ_DSM_CNTL2_BASE_IDX … #define regSQG_THREAD_TRACE_CONFIG … #define regSQG_THREAD_TRACE_CONFIG_BASE_IDX … #define regSP_CONFIG … #define regSP_CONFIG_BASE_IDX … #define regSQ_ARB_CONFIG … #define regSQ_ARB_CONFIG_BASE_IDX … #define regSQ_DYN_VGPR … #define regSQ_DYN_VGPR_BASE_IDX … #define regSQ_DEBUG_HOST_TRAP_STATUS … #define regSQ_DEBUG_HOST_TRAP_STATUS_BASE_IDX … #define regSQG_GL1X_CTRL … #define regSQG_GL1X_CTRL_BASE_IDX … #define regSQG_GL1X_STATUS … #define regSQG_GL1X_STATUS_BASE_IDX … #define regSQG_CONFIG … #define regSQG_CONFIG_BASE_IDX … #define regSQ_PERF_SNAPSHOT_CTRL … #define regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX … #define regCC_GC_SHADER_RATE_CONFIG … #define regCC_GC_SHADER_RATE_CONFIG_BASE_IDX … #define regCC_GC_SHADER_RATE_CONFIG_1 … #define regCC_GC_SHADER_RATE_CONFIG_1_BASE_IDX … #define regSQ_INTERRUPT_AUTO_MASK … #define regSQ_INTERRUPT_AUTO_MASK_BASE_IDX … #define regSQ_INTERRUPT_MSG_CTRL … #define regSQ_INTERRUPT_MSG_CTRL_BASE_IDX … #define regSQ_WATCH0_ADDR_H … #define regSQ_WATCH0_ADDR_H_BASE_IDX … #define regSQ_WATCH0_ADDR_L … #define regSQ_WATCH0_ADDR_L_BASE_IDX … #define regSQ_WATCH0_CNTL … #define regSQ_WATCH0_CNTL_BASE_IDX … #define regSQ_WATCH1_ADDR_H … #define regSQ_WATCH1_ADDR_H_BASE_IDX … #define regSQ_WATCH1_ADDR_L … #define regSQ_WATCH1_ADDR_L_BASE_IDX … #define regSQ_WATCH1_CNTL … #define regSQ_WATCH1_CNTL_BASE_IDX … #define regSQ_WATCH2_ADDR_H … #define regSQ_WATCH2_ADDR_H_BASE_IDX … #define regSQ_WATCH2_ADDR_L … #define regSQ_WATCH2_ADDR_L_BASE_IDX … #define regSQ_WATCH2_CNTL … #define regSQ_WATCH2_CNTL_BASE_IDX … #define regSQ_WATCH3_ADDR_H … #define regSQ_WATCH3_ADDR_H_BASE_IDX … #define regSQ_WATCH3_ADDR_L … #define regSQ_WATCH3_ADDR_L_BASE_IDX … #define regSQ_WATCH3_CNTL … #define regSQ_WATCH3_CNTL_BASE_IDX … #define regSQ_IND_INDEX … #define regSQ_IND_INDEX_BASE_IDX … #define regSQ_IND_DATA … #define regSQ_IND_DATA_BASE_IDX … #define regSQ_CMD … #define regSQ_CMD_BASE_IDX … #define regSQC_MISC_CONFIG … #define regSQC_MISC_CONFIG_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_shsdec // base address: 0x9000 #define regSX_DEBUG_BUSY … #define regSX_DEBUG_BUSY_BASE_IDX … #define regSX_DEBUG_BUSY_2 … #define regSX_DEBUG_BUSY_2_BASE_IDX … #define regSX_DEBUG_BUSY_3 … #define regSX_DEBUG_BUSY_3_BASE_IDX … #define regSX_DEBUG_BUSY_4 … #define regSX_DEBUG_BUSY_4_BASE_IDX … #define regSX_DEBUG_1 … #define regSX_DEBUG_1_BASE_IDX … #define regSX_DEBUG_BUSY_5 … #define regSX_DEBUG_BUSY_5_BASE_IDX … #define regSX_DEBUG_BUSY_6 … #define regSX_DEBUG_BUSY_6_BASE_IDX … #define regSX_DEBUG_BUSY_7 … #define regSX_DEBUG_BUSY_7_BASE_IDX … #define regSX_DEBUG_BUSY_8 … #define regSX_DEBUG_BUSY_8_BASE_IDX … #define regSX_DEBUG_BUSY_9 … #define regSX_DEBUG_BUSY_9_BASE_IDX … #define regSX_DEBUG_BUSY_10 … #define regSX_DEBUG_BUSY_10_BASE_IDX … #define regSPI_PS_MAX_WAVE_ID … #define regSPI_PS_MAX_WAVE_ID_BASE_IDX … #define regSPI_SCRATCH_ADDR_STATUS … #define regSPI_SCRATCH_ADDR_STATUS_BASE_IDX … #define regSPI_GFX_CNTL … #define regSPI_GFX_CNTL_BASE_IDX … #define regSPI_DEBUG_CNTL_2 … #define regSPI_DEBUG_CNTL_2_BASE_IDX … #define regSPI_DEBUG_CNTL_3 … #define regSPI_DEBUG_CNTL_3_BASE_IDX … #define regSPI_DEBUG_CNTL … #define regSPI_DEBUG_CNTL_BASE_IDX … #define regSPI_DEBUG_READ … #define regSPI_DEBUG_READ_BASE_IDX … #define regSPI_DSM_CNTL … #define regSPI_DSM_CNTL_BASE_IDX … #define regSPI_DSM_CNTL2 … #define regSPI_DSM_CNTL2_BASE_IDX … #define regSPI_EDC_CNT … #define regSPI_EDC_CNT_BASE_IDX … #define regSPIRA_DEBUG_READ … #define regSPIRA_DEBUG_READ_BASE_IDX … #define regSPI_DEBUG_BUSY … #define regSPI_DEBUG_BUSY_BASE_IDX … #define regSPI_CONFIG_PS_CU_EN … #define regSPI_CONFIG_PS_CU_EN_BASE_IDX … #define regSPI_CONFIG_CU_MASK_GFX0 … #define regSPI_CONFIG_CU_MASK_GFX0_BASE_IDX … #define regSPI_CONFIG_CU_MASK_HP3D0 … #define regSPI_CONFIG_CU_MASK_HP3D0_BASE_IDX … #define regSPI_CONFIG_CU_MASK_GFX1 … #define regSPI_CONFIG_CU_MASK_GFX1_BASE_IDX … #define regSPI_CONFIG_CU_MASK_HP3D1 … #define regSPI_CONFIG_CU_MASK_HP3D1_BASE_IDX … #define regSPI_CONFIG_CU_MASK_CS0 … #define regSPI_CONFIG_CU_MASK_CS0_BASE_IDX … #define regSPI_CONFIG_CU_MASK_CS1 … #define regSPI_CONFIG_CU_MASK_CS1_BASE_IDX … #define regSPI_CONFIG_CU_MASK_CS2 … #define regSPI_CONFIG_CU_MASK_CS2_BASE_IDX … #define regSPI_CONFIG_CU_MASK_CS3 … #define regSPI_CONFIG_CU_MASK_CS3_BASE_IDX … #define regSPI_CONFIG_CU_MASK_CS4 … #define regSPI_CONFIG_CU_MASK_CS4_BASE_IDX … #define regSPI_CONFIG_CU_MASK_CS5 … #define regSPI_CONFIG_CU_MASK_CS5_BASE_IDX … #define regSPI_CONFIG_CU_MASK_CS6 … #define regSPI_CONFIG_CU_MASK_CS6_BASE_IDX … #define regSPI_CONFIG_CU_MASK_CS7 … #define regSPI_CONFIG_CU_MASK_CS7_BASE_IDX … #define regSPI_WF_LIFETIME_CNTL … #define regSPI_WF_LIFETIME_CNTL_BASE_IDX … #define regSPI_WF_LIFETIME_LIMIT_0 … #define regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX … #define regSPI_WF_LIFETIME_LIMIT_2 … #define regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX … #define regSPI_WF_LIFETIME_LIMIT_3 … #define regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_0 … #define regSPI_WF_LIFETIME_STATUS_0_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_2 … #define regSPI_WF_LIFETIME_STATUS_2_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_4 … #define regSPI_WF_LIFETIME_STATUS_4_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_6 … #define regSPI_WF_LIFETIME_STATUS_6_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_7 … #define regSPI_WF_LIFETIME_STATUS_7_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_9 … #define regSPI_WF_LIFETIME_STATUS_9_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_11 … #define regSPI_WF_LIFETIME_STATUS_11_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_13 … #define regSPI_WF_LIFETIME_STATUS_13_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_14 … #define regSPI_WF_LIFETIME_STATUS_14_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_15 … #define regSPI_WF_LIFETIME_STATUS_15_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_16 … #define regSPI_WF_LIFETIME_STATUS_16_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_17 … #define regSPI_WF_LIFETIME_STATUS_17_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_18 … #define regSPI_WF_LIFETIME_STATUS_18_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_19 … #define regSPI_WF_LIFETIME_STATUS_19_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_20 … #define regSPI_WF_LIFETIME_STATUS_20_BASE_IDX … #define regSPI_WF_LIFETIME_DEBUG … #define regSPI_WF_LIFETIME_DEBUG_BASE_IDX … #define regSPI_WF_LIFETIME_STATUS_21 … #define regSPI_WF_LIFETIME_STATUS_21_BASE_IDX … #define regSPI_WGP_WORK_PENDING … #define regSPI_WGP_WORK_PENDING_BASE_IDX … #define regSPI_CREST_MODE … #define regSPI_CREST_MODE_BASE_IDX … #define regSPI_SLAVE_DEBUG_BUSY … #define regSPI_SLAVE_DEBUG_BUSY_BASE_IDX … #define regSPI_LB_CTR_CTRL … #define regSPI_LB_CTR_CTRL_BASE_IDX … #define regSPI_LB_WGP_MASK … #define regSPI_LB_WGP_MASK_BASE_IDX … #define regSPI_LB_DATA_REG … #define regSPI_LB_DATA_REG_BASE_IDX … #define regSPI_PG_ENABLE_STATIC_WGP_MASK … #define regSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX … #define regSPI_GDS_CREDITS … #define regSPI_GDS_CREDITS_BASE_IDX … #define regSPI_SX_EXPORT_BUFFER_SIZES … #define regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX … #define regSPI_SX_SCOREBOARD_BUFFER_SIZES … #define regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX … #define regSPI_CSQ_WF_ACTIVE_STATUS … #define regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX … #define regSPI_CSQ_WF_ACTIVE_COUNT_0 … #define regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX … #define regSPI_CSQ_WF_ACTIVE_COUNT_1 … #define regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX … #define regSPI_CSQ_WF_ACTIVE_COUNT_2 … #define regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX … #define regSPI_CSQ_WF_ACTIVE_COUNT_3 … #define regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX … #define regSPI_LB_DATA_WAVES … #define regSPI_LB_DATA_WAVES_BASE_IDX … #define regSPI_LB_DATA_PERWGP_WAVE_HSGS … #define regSPI_LB_DATA_PERWGP_WAVE_HSGS_BASE_IDX … #define regSPI_LB_DATA_PERWGP_WAVE_PS … #define regSPI_LB_DATA_PERWGP_WAVE_PS_BASE_IDX … #define regSPI_LB_DATA_PERWGP_WAVE_CS … #define regSPI_LB_DATA_PERWGP_WAVE_CS_BASE_IDX … #define regSPI_WF_ACTIVE_COUNT_GFX … #define regSPI_WF_ACTIVE_COUNT_GFX_BASE_IDX … #define regSPI_WF_ACTIVE_COUNT_HPG … #define regSPI_WF_ACTIVE_COUNT_HPG_BASE_IDX … #define regSPIS_DEBUG_READ … #define regSPIS_DEBUG_READ_BASE_IDX … #define regBCI_DEBUG_READ … #define regBCI_DEBUG_READ_BASE_IDX … #define regSPI_P0_TRAP_SCREEN_PSBA_LO … #define regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX … #define regSPI_P0_TRAP_SCREEN_PSBA_HI … #define regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX … #define regSPI_P0_TRAP_SCREEN_PSMA_LO … #define regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX … #define regSPI_P0_TRAP_SCREEN_PSMA_HI … #define regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX … #define regSPI_P0_TRAP_SCREEN_GPR_MIN … #define regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX … #define regSPI_P1_TRAP_SCREEN_PSBA_LO … #define regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX … #define regSPI_P1_TRAP_SCREEN_PSBA_HI … #define regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX … #define regSPI_P1_TRAP_SCREEN_PSMA_LO … #define regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX … #define regSPI_P1_TRAP_SCREEN_PSMA_HI … #define regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX … #define regSPI_P1_TRAP_SCREEN_GPR_MIN … #define regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX … #define regSPI_GFX_CRAWLER_CONFIG … #define regSPI_GFX_CRAWLER_CONFIG_BASE_IDX … #define regSPI_CS_CRAWLER_CONFIG … #define regSPI_CS_CRAWLER_CONFIG_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_tpdec // base address: 0x9400 #define regTD_CNTL … #define regTD_CNTL_BASE_IDX … #define regTD_STATUS … #define regTD_STATUS_BASE_IDX … #define regTD_POWER_CNTL … #define regTD_POWER_CNTL_BASE_IDX … #define regTD_CNTL2 … #define regTD_CNTL2_BASE_IDX … #define regTD_DSM_CNTL … #define regTD_DSM_CNTL_BASE_IDX … #define regTD_DSM_CNTL2 … #define regTD_DSM_CNTL2_BASE_IDX … #define regTD_SCRATCH … #define regTD_SCRATCH_BASE_IDX … #define regTA_CNTL … #define regTA_CNTL_BASE_IDX … #define regTA_CNTL_AUX … #define regTA_CNTL_AUX_BASE_IDX … #define regTA_CNTL2 … #define regTA_CNTL2_BASE_IDX … #define regTA_STATUS … #define regTA_STATUS_BASE_IDX … #define regTA_SCRATCH … #define regTA_SCRATCH_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_rbdec // base address: 0x9800 #define regDB_DEBUG … #define regDB_DEBUG_BASE_IDX … #define regDB_DEBUG2 … #define regDB_DEBUG2_BASE_IDX … #define regDB_DEBUG3 … #define regDB_DEBUG3_BASE_IDX … #define regDB_DEBUG4 … #define regDB_DEBUG4_BASE_IDX … #define regDB_CREDIT_LIMIT … #define regDB_CREDIT_LIMIT_BASE_IDX … #define regDB_WATERMARKS … #define regDB_WATERMARKS_BASE_IDX … #define regDB_FREE_CACHELINES … #define regDB_FREE_CACHELINES_BASE_IDX … #define regDB_FIFO_DEPTH1 … #define regDB_FIFO_DEPTH1_BASE_IDX … #define regDB_FIFO_DEPTH2 … #define regDB_FIFO_DEPTH2_BASE_IDX … #define regDB_RING_CONTROL … #define regDB_RING_CONTROL_BASE_IDX … #define regDB_MEM_ARB_WATERMARKS … #define regDB_MEM_ARB_WATERMARKS_BASE_IDX … #define regDB_FIFO_DEPTH3 … #define regDB_FIFO_DEPTH3_BASE_IDX … #define regDB_DEBUG6 … #define regDB_DEBUG6_BASE_IDX … #define regDB_EXCEPTION_CONTROL … #define regDB_EXCEPTION_CONTROL_BASE_IDX … #define regDB_DEBUG7 … #define regDB_DEBUG7_BASE_IDX … #define regDB_DEBUG5 … #define regDB_DEBUG5_BASE_IDX … #define regDB_MEM_CONFIG … #define regDB_MEM_CONFIG_BASE_IDX … #define regDB_ARB_CONFIG … #define regDB_ARB_CONFIG_BASE_IDX … #define regDB_DFD_INDIRECT_SEL … #define regDB_DFD_INDIRECT_SEL_BASE_IDX … #define regDB_DFD_INDIRECT_DAT … #define regDB_DFD_INDIRECT_DAT_BASE_IDX … #define regDB_SUMMARIZER_TIMEOUTS … #define regDB_SUMMARIZER_TIMEOUTS_BASE_IDX … #define regDB_FGCG_SRAMS_CLK_CTRL … #define regDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX … #define regDB_FGCG_INTERFACES_CLK_CTRL … #define regDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX … #define regDB_FIFO_DEPTH4 … #define regDB_FIFO_DEPTH4_BASE_IDX … #define regCC_RB_BACKEND_DISABLE … #define regCC_RB_BACKEND_DISABLE_BASE_IDX … #define regGB_ADDR_CONFIG … #define regGB_ADDR_CONFIG_BASE_IDX … #define regGB_ADDR_CONFIG_1 … #define regGB_ADDR_CONFIG_1_BASE_IDX … #define regGB_BACKEND_MAP … #define regGB_BACKEND_MAP_BASE_IDX … #define regGB_GPU_ID … #define regGB_GPU_ID_BASE_IDX … #define regGB_ADDR_CONFIG_READ … #define regGB_ADDR_CONFIG_READ_BASE_IDX … #define regCB_HW_CONTROL_4 … #define regCB_HW_CONTROL_4_BASE_IDX … #define regCB_HW_CONTROL_3 … #define regCB_HW_CONTROL_3_BASE_IDX … #define regCB_HW_CONTROL … #define regCB_HW_CONTROL_BASE_IDX … #define regCB_HW_CONTROL_1 … #define regCB_HW_CONTROL_1_BASE_IDX … #define regCB_HW_CONTROL_2 … #define regCB_HW_CONTROL_2_BASE_IDX … #define regCB_HW_MEM_ARBITER_CTL … #define regCB_HW_MEM_ARBITER_CTL_BASE_IDX … #define regCB_FGCG_SRAM_OVERRIDE … #define regCB_FGCG_SRAM_OVERRIDE_BASE_IDX … #define regCB_CACHE_EVICT_POINTS … #define regCB_CACHE_EVICT_POINTS_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_spipdec2 // base address: 0x9c80 #define regSPI_PQEV_CTRL … #define regSPI_PQEV_CTRL_BASE_IDX … #define regSPI_EXP_THROTTLE_CTRL … #define regSPI_EXP_THROTTLE_CTRL_BASE_IDX … // addressBlock: gc_gfx_se_rmi_gfx_se_rmidec // base address: 0x2e200 #define regRMI_GENERAL_CNTL … #define regRMI_GENERAL_CNTL_BASE_IDX … #define regRMI_GENERAL_CNTL1 … #define regRMI_GENERAL_CNTL1_BASE_IDX … #define regRMI_GENERAL_STATUS … #define regRMI_GENERAL_STATUS_BASE_IDX … #define regRMI_SUBBLOCK_STATUS0 … #define regRMI_SUBBLOCK_STATUS0_BASE_IDX … #define regRMI_SUBBLOCK_STATUS1 … #define regRMI_SUBBLOCK_STATUS1_BASE_IDX … #define regRMI_SUBBLOCK_STATUS2 … #define regRMI_SUBBLOCK_STATUS2_BASE_IDX … #define regRMI_SUBBLOCK_STATUS3 … #define regRMI_SUBBLOCK_STATUS3_BASE_IDX … #define regRMI_XBAR_CONFIG … #define regRMI_XBAR_CONFIG_BASE_IDX … #define regRMI_PROBE_POP_LOGIC_CNTL … #define regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX … #define regRMI_UTC_XNACK_N_MISC_CNTL … #define regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX … #define regRMI_DEMUX_CNTL … #define regRMI_DEMUX_CNTL_BASE_IDX … #define regRMI_UTCL1_CNTL1 … #define regRMI_UTCL1_CNTL1_BASE_IDX … #define regRMI_UTCL1_CNTL2 … #define regRMI_UTCL1_CNTL2_BASE_IDX … #define regRMI_UTC_UNIT_CONFIG … #define regRMI_UTC_UNIT_CONFIG_BASE_IDX … #define regRMI_TCIW_FORMATTER0_CNTL … #define regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX … #define regRMI_TCIW_FORMATTER1_CNTL … #define regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX … #define regRMI_SCOREBOARD_CNTL … #define regRMI_SCOREBOARD_CNTL_BASE_IDX … #define regRMI_SCOREBOARD_STATUS0 … #define regRMI_SCOREBOARD_STATUS0_BASE_IDX … #define regRMI_SCOREBOARD_STATUS1 … #define regRMI_SCOREBOARD_STATUS1_BASE_IDX … #define regRMI_SCOREBOARD_STATUS2 … #define regRMI_SCOREBOARD_STATUS2_BASE_IDX … #define regRMI_XBAR_ARBITER_CONFIG … #define regRMI_XBAR_ARBITER_CONFIG_BASE_IDX … #define regRMI_XBAR_ARBITER_CONFIG_1 … #define regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX … #define regRMI_CLOCK_CNTRL … #define regRMI_CLOCK_CNTRL_BASE_IDX … #define regRMI_UTCL1_STATUS … #define regRMI_UTCL1_STATUS_BASE_IDX … #define regRMI_RB_GLX_CID_MAP … #define regRMI_RB_GLX_CID_MAP_BASE_IDX … #define regRMI_XNACK_DEBUG … #define regRMI_XNACK_DEBUG_BASE_IDX … #define regRMI_SPARE … #define regRMI_SPARE_BASE_IDX … #define regRMI_SPARE_1 … #define regRMI_SPARE_1_BASE_IDX … #define regRMI_SPARE_2 … #define regRMI_SPARE_2_BASE_IDX … #define regCC_RMI_REDUNDANCY … #define regCC_RMI_REDUNDANCY_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_utcl1dec // base address: 0x9fb0 #define regUTCL1_CTRL_1 … #define regUTCL1_CTRL_1_BASE_IDX … #define regUTCL1_HASH_CTRL … #define regUTCL1_HASH_CTRL_BASE_IDX … #define regUTCL1_ALOG … #define regUTCL1_ALOG_BASE_IDX … #define regUTCL1_STATUS … #define regUTCL1_STATUS_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_shdec // base address: 0xb000 #define regSPI_SHADER_PGM_CHKSUM_PS … #define regSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX … #define regSPI_SHADER_PGM_RSRC3_PS … #define regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX … #define regSPI_SHADER_PGM_RSRC4_PS … #define regSPI_SHADER_PGM_RSRC4_PS_BASE_IDX … #define regSPI_SHADER_PGM_LO_PS … #define regSPI_SHADER_PGM_LO_PS_BASE_IDX … #define regSPI_SHADER_PGM_HI_PS … #define regSPI_SHADER_PGM_HI_PS_BASE_IDX … #define regSPI_SHADER_PGM_RSRC1_PS … #define regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX … #define regSPI_SHADER_PGM_RSRC2_PS … #define regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_0 … #define regSPI_SHADER_USER_DATA_PS_0_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_1 … #define regSPI_SHADER_USER_DATA_PS_1_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_2 … #define regSPI_SHADER_USER_DATA_PS_2_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_3 … #define regSPI_SHADER_USER_DATA_PS_3_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_4 … #define regSPI_SHADER_USER_DATA_PS_4_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_5 … #define regSPI_SHADER_USER_DATA_PS_5_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_6 … #define regSPI_SHADER_USER_DATA_PS_6_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_7 … #define regSPI_SHADER_USER_DATA_PS_7_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_8 … #define regSPI_SHADER_USER_DATA_PS_8_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_9 … #define regSPI_SHADER_USER_DATA_PS_9_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_10 … #define regSPI_SHADER_USER_DATA_PS_10_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_11 … #define regSPI_SHADER_USER_DATA_PS_11_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_12 … #define regSPI_SHADER_USER_DATA_PS_12_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_13 … #define regSPI_SHADER_USER_DATA_PS_13_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_14 … #define regSPI_SHADER_USER_DATA_PS_14_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_15 … #define regSPI_SHADER_USER_DATA_PS_15_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_16 … #define regSPI_SHADER_USER_DATA_PS_16_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_17 … #define regSPI_SHADER_USER_DATA_PS_17_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_18 … #define regSPI_SHADER_USER_DATA_PS_18_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_19 … #define regSPI_SHADER_USER_DATA_PS_19_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_20 … #define regSPI_SHADER_USER_DATA_PS_20_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_21 … #define regSPI_SHADER_USER_DATA_PS_21_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_22 … #define regSPI_SHADER_USER_DATA_PS_22_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_23 … #define regSPI_SHADER_USER_DATA_PS_23_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_24 … #define regSPI_SHADER_USER_DATA_PS_24_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_25 … #define regSPI_SHADER_USER_DATA_PS_25_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_26 … #define regSPI_SHADER_USER_DATA_PS_26_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_27 … #define regSPI_SHADER_USER_DATA_PS_27_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_28 … #define regSPI_SHADER_USER_DATA_PS_28_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_29 … #define regSPI_SHADER_USER_DATA_PS_29_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_30 … #define regSPI_SHADER_USER_DATA_PS_30_BASE_IDX … #define regSPI_SHADER_USER_DATA_PS_31 … #define regSPI_SHADER_USER_DATA_PS_31_BASE_IDX … #define regSPI_SHADER_REQ_CTRL_PS … #define regSPI_SHADER_REQ_CTRL_PS_BASE_IDX … #define regSPI_SHADER_GS_OUT_CONFIG_PS … #define regSPI_SHADER_GS_OUT_CONFIG_PS_BASE_IDX … #define regSPI_SHADER_USER_ACCUM_PS_0 … #define regSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX … #define regSPI_SHADER_USER_ACCUM_PS_1 … #define regSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX … #define regSPI_SHADER_USER_ACCUM_PS_2 … #define regSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX … #define regSPI_SHADER_USER_ACCUM_PS_3 … #define regSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX … #define regSPI_SHADER_PGM_CHKSUM_GS … #define regSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX … #define regSPI_SHADER_USER_DATA_ADDR_LO_GS … #define regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX … #define regSPI_SHADER_USER_DATA_ADDR_HI_GS … #define regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX … #define regSPI_SHADER_PGM_LO_GS … #define regSPI_SHADER_PGM_LO_GS_BASE_IDX … #define regSPI_SHADER_PGM_HI_GS … #define regSPI_SHADER_PGM_HI_GS_BASE_IDX … #define regSPI_SHADER_PGM_HI_ES … #define regSPI_SHADER_PGM_HI_ES_BASE_IDX … #define regSPI_SHADER_PGM_RSRC3_GS … #define regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX … #define regSPI_SHADER_PGM_RSRC4_GS … #define regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX … #define regSPI_SHADER_PGM_LO_ES … #define regSPI_SHADER_PGM_LO_ES_BASE_IDX … #define regSPI_SHADER_PGM_RSRC1_GS … #define regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX … #define regSPI_SHADER_PGM_RSRC2_GS … #define regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_0 … #define regSPI_SHADER_USER_DATA_GS_0_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_1 … #define regSPI_SHADER_USER_DATA_GS_1_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_2 … #define regSPI_SHADER_USER_DATA_GS_2_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_3 … #define regSPI_SHADER_USER_DATA_GS_3_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_4 … #define regSPI_SHADER_USER_DATA_GS_4_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_5 … #define regSPI_SHADER_USER_DATA_GS_5_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_6 … #define regSPI_SHADER_USER_DATA_GS_6_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_7 … #define regSPI_SHADER_USER_DATA_GS_7_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_8 … #define regSPI_SHADER_USER_DATA_GS_8_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_9 … #define regSPI_SHADER_USER_DATA_GS_9_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_10 … #define regSPI_SHADER_USER_DATA_GS_10_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_11 … #define regSPI_SHADER_USER_DATA_GS_11_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_12 … #define regSPI_SHADER_USER_DATA_GS_12_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_13 … #define regSPI_SHADER_USER_DATA_GS_13_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_14 … #define regSPI_SHADER_USER_DATA_GS_14_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_15 … #define regSPI_SHADER_USER_DATA_GS_15_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_16 … #define regSPI_SHADER_USER_DATA_GS_16_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_17 … #define regSPI_SHADER_USER_DATA_GS_17_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_18 … #define regSPI_SHADER_USER_DATA_GS_18_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_19 … #define regSPI_SHADER_USER_DATA_GS_19_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_20 … #define regSPI_SHADER_USER_DATA_GS_20_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_21 … #define regSPI_SHADER_USER_DATA_GS_21_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_22 … #define regSPI_SHADER_USER_DATA_GS_22_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_23 … #define regSPI_SHADER_USER_DATA_GS_23_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_24 … #define regSPI_SHADER_USER_DATA_GS_24_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_25 … #define regSPI_SHADER_USER_DATA_GS_25_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_26 … #define regSPI_SHADER_USER_DATA_GS_26_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_27 … #define regSPI_SHADER_USER_DATA_GS_27_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_28 … #define regSPI_SHADER_USER_DATA_GS_28_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_29 … #define regSPI_SHADER_USER_DATA_GS_29_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_30 … #define regSPI_SHADER_USER_DATA_GS_30_BASE_IDX … #define regSPI_SHADER_USER_DATA_GS_31 … #define regSPI_SHADER_USER_DATA_GS_31_BASE_IDX … #define regSPI_SHADER_GS_MESHLET_DIM … #define regSPI_SHADER_GS_MESHLET_DIM_BASE_IDX … #define regSPI_SHADER_GS_MESHLET_EXP_ALLOC … #define regSPI_SHADER_GS_MESHLET_EXP_ALLOC_BASE_IDX … #define regSPI_SHADER_GS_MESHLET_CTRL … #define regSPI_SHADER_GS_MESHLET_CTRL_BASE_IDX … #define regSPI_SHADER_REQ_CTRL_ESGS … #define regSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX … #define regSPI_SHADER_GS_OUT_CONFIG_PS_GS … #define regSPI_SHADER_GS_OUT_CONFIG_PS_GS_BASE_IDX … #define regSPI_SHADER_USER_ACCUM_ESGS_0 … #define regSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX … #define regSPI_SHADER_USER_ACCUM_ESGS_1 … #define regSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX … #define regSPI_SHADER_USER_ACCUM_ESGS_2 … #define regSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX … #define regSPI_SHADER_USER_ACCUM_ESGS_3 … #define regSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX … #define regSPI_SHADER_PGM_CHKSUM_HS … #define regSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX … #define regSPI_SHADER_USER_DATA_ADDR_LO_HS … #define regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX … #define regSPI_SHADER_USER_DATA_ADDR_HI_HS … #define regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX … #define regSPI_SHADER_PGM_LO_HS … #define regSPI_SHADER_PGM_LO_HS_BASE_IDX … #define regSPI_SHADER_PGM_HI_HS … #define regSPI_SHADER_PGM_HI_HS_BASE_IDX … #define regSPI_SHADER_PGM_HI_LS … #define regSPI_SHADER_PGM_HI_LS_BASE_IDX … #define regSPI_SHADER_PGM_RSRC3_HS … #define regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX … #define regSPI_SHADER_PGM_RSRC4_HS … #define regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX … #define regSPI_SHADER_PGM_LO_LS … #define regSPI_SHADER_PGM_LO_LS_BASE_IDX … #define regSPI_SHADER_PGM_RSRC1_HS … #define regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX … #define regSPI_SHADER_PGM_RSRC2_HS … #define regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_0 … #define regSPI_SHADER_USER_DATA_HS_0_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_1 … #define regSPI_SHADER_USER_DATA_HS_1_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_2 … #define regSPI_SHADER_USER_DATA_HS_2_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_3 … #define regSPI_SHADER_USER_DATA_HS_3_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_4 … #define regSPI_SHADER_USER_DATA_HS_4_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_5 … #define regSPI_SHADER_USER_DATA_HS_5_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_6 … #define regSPI_SHADER_USER_DATA_HS_6_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_7 … #define regSPI_SHADER_USER_DATA_HS_7_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_8 … #define regSPI_SHADER_USER_DATA_HS_8_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_9 … #define regSPI_SHADER_USER_DATA_HS_9_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_10 … #define regSPI_SHADER_USER_DATA_HS_10_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_11 … #define regSPI_SHADER_USER_DATA_HS_11_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_12 … #define regSPI_SHADER_USER_DATA_HS_12_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_13 … #define regSPI_SHADER_USER_DATA_HS_13_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_14 … #define regSPI_SHADER_USER_DATA_HS_14_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_15 … #define regSPI_SHADER_USER_DATA_HS_15_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_16 … #define regSPI_SHADER_USER_DATA_HS_16_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_17 … #define regSPI_SHADER_USER_DATA_HS_17_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_18 … #define regSPI_SHADER_USER_DATA_HS_18_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_19 … #define regSPI_SHADER_USER_DATA_HS_19_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_20 … #define regSPI_SHADER_USER_DATA_HS_20_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_21 … #define regSPI_SHADER_USER_DATA_HS_21_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_22 … #define regSPI_SHADER_USER_DATA_HS_22_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_23 … #define regSPI_SHADER_USER_DATA_HS_23_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_24 … #define regSPI_SHADER_USER_DATA_HS_24_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_25 … #define regSPI_SHADER_USER_DATA_HS_25_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_26 … #define regSPI_SHADER_USER_DATA_HS_26_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_27 … #define regSPI_SHADER_USER_DATA_HS_27_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_28 … #define regSPI_SHADER_USER_DATA_HS_28_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_29 … #define regSPI_SHADER_USER_DATA_HS_29_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_30 … #define regSPI_SHADER_USER_DATA_HS_30_BASE_IDX … #define regSPI_SHADER_USER_DATA_HS_31 … #define regSPI_SHADER_USER_DATA_HS_31_BASE_IDX … #define regSPI_SHADER_REQ_CTRL_LSHS … #define regSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX … #define regSPI_SHADER_USER_ACCUM_LSHS_0 … #define regSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX … #define regSPI_SHADER_USER_ACCUM_LSHS_1 … #define regSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX … #define regSPI_SHADER_USER_ACCUM_LSHS_2 … #define regSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX … #define regSPI_SHADER_USER_ACCUM_LSHS_3 … #define regSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_spipdec // base address: 0xc700 #define regSPI_ARB_PRIORITY … #define regSPI_ARB_PRIORITY_BASE_IDX … #define regSPI_ARB_CYCLES_0 … #define regSPI_ARB_CYCLES_0_BASE_IDX … #define regSPI_ARB_CYCLES_1 … #define regSPI_ARB_CYCLES_1_BASE_IDX … #define regSPI_WCL_PIPE_PERCENT_GFX … #define regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX … #define regSPI_WCL_PIPE_PERCENT_HP3D … #define regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX … #define regSPI_WCL_PIPE_PERCENT_CS0 … #define regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX … #define regSPI_WCL_PIPE_PERCENT_CS1 … #define regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX … #define regSPI_WCL_PIPE_PERCENT_CS2 … #define regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX … #define regSPI_WCL_PIPE_PERCENT_CS3 … #define regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX … #define regSPI_WCL_PIPE_PERCENT_CS4 … #define regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX … #define regSPI_WCL_PIPE_PERCENT_CS5 … #define regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX … #define regSPI_WCL_PIPE_PERCENT_CS6 … #define regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX … #define regSPI_WCL_PIPE_PERCENT_CS7 … #define regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX … #define regSPI_USER_ACCUM_VMID_CNTL … #define regSPI_USER_ACCUM_VMID_CNTL_BASE_IDX … #define regSPI_GDBG_PER_VMID_CNTL … #define regSPI_GDBG_PER_VMID_CNTL_BASE_IDX … #define regSPI_COMPUTE_QUEUE_RESET … #define regSPI_COMPUTE_QUEUE_RESET_BASE_IDX … #define regSPI_COMPUTE_WF_CTX_SAVE … #define regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX … #define regSPI_SAVE_RESTORE_STATUS … #define regSPI_SAVE_RESTORE_STATUS_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_tcpdec // base address: 0xca80 #define regTCP_WATCH0_ADDR_H … #define regTCP_WATCH0_ADDR_H_BASE_IDX … #define regTCP_WATCH0_ADDR_L … #define regTCP_WATCH0_ADDR_L_BASE_IDX … #define regTCP_WATCH0_CNTL … #define regTCP_WATCH0_CNTL_BASE_IDX … #define regTCP_WATCH1_ADDR_H … #define regTCP_WATCH1_ADDR_H_BASE_IDX … #define regTCP_WATCH1_ADDR_L … #define regTCP_WATCH1_ADDR_L_BASE_IDX … #define regTCP_WATCH1_CNTL … #define regTCP_WATCH1_CNTL_BASE_IDX … #define regTCP_WATCH2_ADDR_H … #define regTCP_WATCH2_ADDR_H_BASE_IDX … #define regTCP_WATCH2_ADDR_L … #define regTCP_WATCH2_ADDR_L_BASE_IDX … #define regTCP_WATCH2_CNTL … #define regTCP_WATCH2_CNTL_BASE_IDX … #define regTCP_WATCH3_ADDR_H … #define regTCP_WATCH3_ADDR_H_BASE_IDX … #define regTCP_WATCH3_ADDR_L … #define regTCP_WATCH3_ADDR_L_BASE_IDX … #define regTCP_WATCH3_CNTL … #define regTCP_WATCH3_CNTL_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_rasdec // base address: 0xce00 #define regRAS_SIGNATURE_CONTROL … #define regRAS_SIGNATURE_CONTROL_BASE_IDX … #define regRAS_SIGNATURE_MASK … #define regRAS_SIGNATURE_MASK_BASE_IDX … #define regRAS_SX_SIGNATURE0 … #define regRAS_SX_SIGNATURE0_BASE_IDX … #define regRAS_SX_SIGNATURE1 … #define regRAS_SX_SIGNATURE1_BASE_IDX … #define regRAS_SX_SIGNATURE2 … #define regRAS_SX_SIGNATURE2_BASE_IDX … #define regRAS_SX_SIGNATURE3 … #define regRAS_SX_SIGNATURE3_BASE_IDX … #define regRAS_DB_SIGNATURE0 … #define regRAS_DB_SIGNATURE0_BASE_IDX … #define regRAS_PA_SIGNATURE0 … #define regRAS_PA_SIGNATURE0_BASE_IDX … #define regRAS_SC_SIGNATURE0 … #define regRAS_SC_SIGNATURE0_BASE_IDX … #define regRAS_SC_SIGNATURE1 … #define regRAS_SC_SIGNATURE1_BASE_IDX … #define regRAS_SC_SIGNATURE2 … #define regRAS_SC_SIGNATURE2_BASE_IDX … #define regRAS_SC_SIGNATURE3 … #define regRAS_SC_SIGNATURE3_BASE_IDX … #define regRAS_SC_SIGNATURE4 … #define regRAS_SC_SIGNATURE4_BASE_IDX … #define regRAS_SC_SIGNATURE5 … #define regRAS_SC_SIGNATURE5_BASE_IDX … #define regRAS_SC_SIGNATURE6 … #define regRAS_SC_SIGNATURE6_BASE_IDX … #define regRAS_SC_SIGNATURE7 … #define regRAS_SC_SIGNATURE7_BASE_IDX … #define regRAS_SPI_SIGNATURE0 … #define regRAS_SPI_SIGNATURE0_BASE_IDX … #define regRAS_SPI_SIGNATURE1 … #define regRAS_SPI_SIGNATURE1_BASE_IDX … #define regRAS_CB_SIGNATURE0 … #define regRAS_CB_SIGNATURE0_BASE_IDX … #define regRAS_BCI_SIGNATURE0 … #define regRAS_BCI_SIGNATURE0_BASE_IDX … #define regRAS_BCI_SIGNATURE1 … #define regRAS_BCI_SIGNATURE1_BASE_IDX … #define regRAS_GE_SIGNATURE1 … #define regRAS_GE_SIGNATURE1_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_gfxdec0 // base address: 0x28000 #define regDB_RENDER_CONTROL … #define regDB_RENDER_CONTROL_BASE_IDX … #define regDB_DEPTH_VIEW … #define regDB_DEPTH_VIEW_BASE_IDX … #define regDB_DEPTH_VIEW1 … #define regDB_DEPTH_VIEW1_BASE_IDX … #define regDB_RENDER_OVERRIDE … #define regDB_RENDER_OVERRIDE_BASE_IDX … #define regDB_RENDER_OVERRIDE2 … #define regDB_RENDER_OVERRIDE2_BASE_IDX … #define regDB_DEPTH_SIZE_XY … #define regDB_DEPTH_SIZE_XY_BASE_IDX … #define regDB_Z_INFO … #define regDB_Z_INFO_BASE_IDX … #define regDB_STENCIL_INFO … #define regDB_STENCIL_INFO_BASE_IDX … #define regDB_Z_READ_BASE … #define regDB_Z_READ_BASE_BASE_IDX … #define regDB_Z_READ_BASE_HI … #define regDB_Z_READ_BASE_HI_BASE_IDX … #define regDB_Z_WRITE_BASE … #define regDB_Z_WRITE_BASE_BASE_IDX … #define regDB_Z_WRITE_BASE_HI … #define regDB_Z_WRITE_BASE_HI_BASE_IDX … #define regDB_STENCIL_READ_BASE … #define regDB_STENCIL_READ_BASE_BASE_IDX … #define regDB_STENCIL_READ_BASE_HI … #define regDB_STENCIL_READ_BASE_HI_BASE_IDX … #define regDB_STENCIL_WRITE_BASE … #define regDB_STENCIL_WRITE_BASE_BASE_IDX … #define regDB_STENCIL_WRITE_BASE_HI … #define regDB_STENCIL_WRITE_BASE_HI_BASE_IDX … #define regDB_GL1_INTERFACE_CONTROL … #define regDB_GL1_INTERFACE_CONTROL_BASE_IDX … #define regDB_MEM_TEMPORAL … #define regDB_MEM_TEMPORAL_BASE_IDX … #define regDB_DEPTH_BOUNDS_MIN … #define regDB_DEPTH_BOUNDS_MIN_BASE_IDX … #define regDB_DEPTH_BOUNDS_MAX … #define regDB_DEPTH_BOUNDS_MAX_BASE_IDX … #define regDB_COUNT_CONTROL … #define regDB_COUNT_CONTROL_BASE_IDX … #define regDB_VIEWPORT_CONTROL … #define regDB_VIEWPORT_CONTROL_BASE_IDX … #define regDB_SPI_VRS_CENTER_LOCATION … #define regDB_SPI_VRS_CENTER_LOCATION_BASE_IDX … #define regDB_SHADER_CONTROL … #define regDB_SHADER_CONTROL_BASE_IDX … #define regDB_DEPTH_CONTROL … #define regDB_DEPTH_CONTROL_BASE_IDX … #define regDB_STENCIL_CONTROL … #define regDB_STENCIL_CONTROL_BASE_IDX … #define regDB_EQAA … #define regDB_EQAA_BASE_IDX … #define regDB_ALPHA_TO_MASK … #define regDB_ALPHA_TO_MASK_BASE_IDX … #define regTA_BC_BASE_ADDR … #define regTA_BC_BASE_ADDR_BASE_IDX … #define regTA_BC_BASE_ADDR_HI … #define regTA_BC_BASE_ADDR_HI_BASE_IDX … #define regDB_STENCIL_REF … #define regDB_STENCIL_REF_BASE_IDX … #define regDB_STENCIL_OPVAL … #define regDB_STENCIL_OPVAL_BASE_IDX … #define regDB_STENCIL_READ_MASK … #define regDB_STENCIL_READ_MASK_BASE_IDX … #define regDB_STENCIL_WRITE_MASK … #define regDB_STENCIL_WRITE_MASK_BASE_IDX … #define regSC_MEM_TEMPORAL … #define regSC_MEM_TEMPORAL_BASE_IDX … #define regSC_MEM_SPEC_READ … #define regSC_MEM_SPEC_READ_BASE_IDX … #define regPA_SC_VPORT_0_TL … #define regPA_SC_VPORT_0_TL_BASE_IDX … #define regPA_SC_VPORT_0_BR … #define regPA_SC_VPORT_0_BR_BASE_IDX … #define regPA_SC_VPORT_1_TL … #define regPA_SC_VPORT_1_TL_BASE_IDX … #define regPA_SC_VPORT_1_BR … #define regPA_SC_VPORT_1_BR_BASE_IDX … #define regPA_SC_VPORT_2_TL … #define regPA_SC_VPORT_2_TL_BASE_IDX … #define regPA_SC_VPORT_2_BR … #define regPA_SC_VPORT_2_BR_BASE_IDX … #define regPA_SC_VPORT_3_TL … #define regPA_SC_VPORT_3_TL_BASE_IDX … #define regPA_SC_VPORT_3_BR … #define regPA_SC_VPORT_3_BR_BASE_IDX … #define regPA_SC_VPORT_4_TL … #define regPA_SC_VPORT_4_TL_BASE_IDX … #define regPA_SC_VPORT_4_BR … #define regPA_SC_VPORT_4_BR_BASE_IDX … #define regPA_SC_VPORT_5_TL … #define regPA_SC_VPORT_5_TL_BASE_IDX … #define regPA_SC_VPORT_5_BR … #define regPA_SC_VPORT_5_BR_BASE_IDX … #define regPA_SC_VPORT_6_TL … #define regPA_SC_VPORT_6_TL_BASE_IDX … #define regPA_SC_VPORT_6_BR … #define regPA_SC_VPORT_6_BR_BASE_IDX … #define regPA_SC_VPORT_7_TL … #define regPA_SC_VPORT_7_TL_BASE_IDX … #define regPA_SC_VPORT_7_BR … #define regPA_SC_VPORT_7_BR_BASE_IDX … #define regPA_SC_VPORT_8_TL … #define regPA_SC_VPORT_8_TL_BASE_IDX … #define regPA_SC_VPORT_8_BR … #define regPA_SC_VPORT_8_BR_BASE_IDX … #define regPA_SC_VPORT_9_TL … #define regPA_SC_VPORT_9_TL_BASE_IDX … #define regPA_SC_VPORT_9_BR … #define regPA_SC_VPORT_9_BR_BASE_IDX … #define regPA_SC_VPORT_10_TL … #define regPA_SC_VPORT_10_TL_BASE_IDX … #define regPA_SC_VPORT_10_BR … #define regPA_SC_VPORT_10_BR_BASE_IDX … #define regPA_SC_VPORT_11_TL … #define regPA_SC_VPORT_11_TL_BASE_IDX … #define regPA_SC_VPORT_11_BR … #define regPA_SC_VPORT_11_BR_BASE_IDX … #define regPA_SC_VPORT_12_TL … #define regPA_SC_VPORT_12_TL_BASE_IDX … #define regPA_SC_VPORT_12_BR … #define regPA_SC_VPORT_12_BR_BASE_IDX … #define regPA_SC_VPORT_13_TL … #define regPA_SC_VPORT_13_TL_BASE_IDX … #define regPA_SC_VPORT_13_BR … #define regPA_SC_VPORT_13_BR_BASE_IDX … #define regPA_SC_VPORT_14_TL … #define regPA_SC_VPORT_14_TL_BASE_IDX … #define regPA_SC_VPORT_14_BR … #define regPA_SC_VPORT_14_BR_BASE_IDX … #define regPA_SC_VPORT_15_TL … #define regPA_SC_VPORT_15_TL_BASE_IDX … #define regPA_SC_VPORT_15_BR … #define regPA_SC_VPORT_15_BR_BASE_IDX … #define regPA_SC_SCREEN_SCISSOR_TL … #define regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX … #define regPA_SC_SCREEN_SCISSOR_BR … #define regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX … #define regPA_SC_WINDOW_OFFSET … #define regPA_SC_WINDOW_OFFSET_BASE_IDX … #define regPA_SC_WINDOW_SCISSOR_TL … #define regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX … #define regPA_SC_WINDOW_SCISSOR_BR … #define regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX … #define regPA_SC_CLIPRECT_RULE … #define regPA_SC_CLIPRECT_RULE_BASE_IDX … #define regPA_SC_CLIPRECT_0_TL … #define regPA_SC_CLIPRECT_0_TL_BASE_IDX … #define regPA_SC_CLIPRECT_0_BR … #define regPA_SC_CLIPRECT_0_BR_BASE_IDX … #define regPA_SC_CLIPRECT_1_TL … #define regPA_SC_CLIPRECT_1_TL_BASE_IDX … #define regPA_SC_CLIPRECT_1_BR … #define regPA_SC_CLIPRECT_1_BR_BASE_IDX … #define regPA_SC_CLIPRECT_2_TL … #define regPA_SC_CLIPRECT_2_TL_BASE_IDX … #define regPA_SC_CLIPRECT_2_BR … #define regPA_SC_CLIPRECT_2_BR_BASE_IDX … #define regPA_SC_CLIPRECT_3_TL … #define regPA_SC_CLIPRECT_3_TL_BASE_IDX … #define regPA_SC_CLIPRECT_3_BR … #define regPA_SC_CLIPRECT_3_BR_BASE_IDX … #define regPA_SC_EDGERULE … #define regPA_SC_EDGERULE_BASE_IDX … #define regPA_SU_HARDWARE_SCREEN_OFFSET … #define regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX … #define regPA_SC_GENERIC_SCISSOR_TL … #define regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX … #define regPA_SC_GENERIC_SCISSOR_BR … #define regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_0_TL … #define regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_0_BR … #define regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_1_TL … #define regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_1_BR … #define regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_2_TL … #define regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_2_BR … #define regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_3_TL … #define regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_3_BR … #define regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_4_TL … #define regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_4_BR … #define regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_5_TL … #define regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_5_BR … #define regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_6_TL … #define regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_6_BR … #define regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_7_TL … #define regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_7_BR … #define regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_8_TL … #define regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_8_BR … #define regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_9_TL … #define regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_9_BR … #define regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_10_TL … #define regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_10_BR … #define regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_11_TL … #define regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_11_BR … #define regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_12_TL … #define regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_12_BR … #define regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_13_TL … #define regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_13_BR … #define regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_14_TL … #define regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_14_BR … #define regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_15_TL … #define regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX … #define regPA_SC_VPORT_SCISSOR_15_BR … #define regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX … #define regPA_CL_UCP_0_X … #define regPA_CL_UCP_0_X_BASE_IDX … #define regPA_CL_UCP_0_Y … #define regPA_CL_UCP_0_Y_BASE_IDX … #define regPA_CL_UCP_0_Z … #define regPA_CL_UCP_0_Z_BASE_IDX … #define regPA_CL_UCP_0_W … #define regPA_CL_UCP_0_W_BASE_IDX … #define regPA_CL_UCP_1_X … #define regPA_CL_UCP_1_X_BASE_IDX … #define regPA_CL_UCP_1_Y … #define regPA_CL_UCP_1_Y_BASE_IDX … #define regPA_CL_UCP_1_Z … #define regPA_CL_UCP_1_Z_BASE_IDX … #define regPA_CL_UCP_1_W … #define regPA_CL_UCP_1_W_BASE_IDX … #define regPA_CL_UCP_2_X … #define regPA_CL_UCP_2_X_BASE_IDX … #define regPA_CL_UCP_2_Y … #define regPA_CL_UCP_2_Y_BASE_IDX … #define regPA_CL_UCP_2_Z … #define regPA_CL_UCP_2_Z_BASE_IDX … #define regPA_CL_UCP_2_W … #define regPA_CL_UCP_2_W_BASE_IDX … #define regPA_CL_UCP_3_X … #define regPA_CL_UCP_3_X_BASE_IDX … #define regPA_CL_UCP_3_Y … #define regPA_CL_UCP_3_Y_BASE_IDX … #define regPA_CL_UCP_3_Z … #define regPA_CL_UCP_3_Z_BASE_IDX … #define regPA_CL_UCP_3_W … #define regPA_CL_UCP_3_W_BASE_IDX … #define regPA_CL_UCP_4_X … #define regPA_CL_UCP_4_X_BASE_IDX … #define regPA_CL_UCP_4_Y … #define regPA_CL_UCP_4_Y_BASE_IDX … #define regPA_CL_UCP_4_Z … #define regPA_CL_UCP_4_Z_BASE_IDX … #define regPA_CL_UCP_4_W … #define regPA_CL_UCP_4_W_BASE_IDX … #define regPA_CL_UCP_5_X … #define regPA_CL_UCP_5_X_BASE_IDX … #define regPA_CL_UCP_5_Y … #define regPA_CL_UCP_5_Y_BASE_IDX … #define regPA_CL_UCP_5_Z … #define regPA_CL_UCP_5_Z_BASE_IDX … #define regPA_CL_UCP_5_W … #define regPA_CL_UCP_5_W_BASE_IDX … #define regPA_CL_PROG_NEAR_CLIP_Z … #define regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX … #define regPA_RATE_CNTL … #define regPA_RATE_CNTL_BASE_IDX … #define regPA_SC_RASTER_CONFIG … #define regPA_SC_RASTER_CONFIG_BASE_IDX … #define regPA_SC_RASTER_CONFIG_1 … #define regPA_SC_RASTER_CONFIG_1_BASE_IDX … #define regPA_SC_SCREEN_EXTENT_CONTROL … #define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX … #define regPA_SC_TILE_STEERING_OVERRIDE … #define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX … #define regCB_CP_PIPEID … #define regCB_CP_PIPEID_BASE_IDX … #define regCB_CP_VMID … #define regCB_CP_VMID_BASE_IDX … #define regPA_SC_CLIPRECT_0_EXT … #define regPA_SC_CLIPRECT_0_EXT_BASE_IDX … #define regPA_SC_CLIPRECT_1_EXT … #define regPA_SC_CLIPRECT_1_EXT_BASE_IDX … #define regPA_SC_CLIPRECT_2_EXT … #define regPA_SC_CLIPRECT_2_EXT_BASE_IDX … #define regPA_SC_CLIPRECT_3_EXT … #define regPA_SC_CLIPRECT_3_EXT_BASE_IDX … #define regPA_SC_VRS_OVERRIDE_CNTL … #define regPA_SC_VRS_OVERRIDE_CNTL_BASE_IDX … #define regPA_SC_VRS_RATE_FEEDBACK_BASE … #define regPA_SC_VRS_RATE_FEEDBACK_BASE_BASE_IDX … #define regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT … #define regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_BASE_IDX … #define regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY … #define regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_BASE_IDX … #define regPA_SC_VRS_INFO … #define regPA_SC_VRS_INFO_BASE_IDX … #define regPA_SC_VRS_RATE_BASE … #define regPA_SC_VRS_RATE_BASE_BASE_IDX … #define regPA_SC_VRS_RATE_BASE_EXT … #define regPA_SC_VRS_RATE_BASE_EXT_BASE_IDX … #define regPA_SC_VRS_RATE_SIZE_XY … #define regPA_SC_VRS_RATE_SIZE_XY_BASE_IDX … #define regCB_RMI_GL2_CACHE_CONTROL … #define regCB_RMI_GL2_CACHE_CONTROL_BASE_IDX … #define regCB_BLEND_RED … #define regCB_BLEND_RED_BASE_IDX … #define regCB_BLEND_GREEN … #define regCB_BLEND_GREEN_BASE_IDX … #define regCB_BLEND_BLUE … #define regCB_BLEND_BLUE_BASE_IDX … #define regCB_BLEND_ALPHA … #define regCB_BLEND_ALPHA_BASE_IDX … #define regPA_CL_GB_VERT_CLIP_ADJ … #define regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX … #define regPA_CL_GB_VERT_DISC_ADJ … #define regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX … #define regPA_CL_GB_HORZ_CLIP_ADJ … #define regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX … #define regPA_CL_GB_HORZ_DISC_ADJ … #define regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX … #define regPA_CL_VPORT_XSCALE … #define regPA_CL_VPORT_XSCALE_BASE_IDX … #define regPA_CL_VPORT_XOFFSET … #define regPA_CL_VPORT_XOFFSET_BASE_IDX … #define regPA_CL_VPORT_YSCALE … #define regPA_CL_VPORT_YSCALE_BASE_IDX … #define regPA_CL_VPORT_YOFFSET … #define regPA_CL_VPORT_YOFFSET_BASE_IDX … #define regPA_CL_VPORT_ZSCALE … #define regPA_CL_VPORT_ZSCALE_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET … #define regPA_CL_VPORT_ZOFFSET_BASE_IDX … #define regPA_SC_VPORT_ZMIN_0 … #define regPA_SC_VPORT_ZMIN_0_BASE_IDX … #define regPA_SC_VPORT_ZMAX_0 … #define regPA_SC_VPORT_ZMAX_0_BASE_IDX … #define regPA_CL_VPORT_XSCALE_1 … #define regPA_CL_VPORT_XSCALE_1_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_1 … #define regPA_CL_VPORT_XOFFSET_1_BASE_IDX … #define regPA_CL_VPORT_YSCALE_1 … #define regPA_CL_VPORT_YSCALE_1_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_1 … #define regPA_CL_VPORT_YOFFSET_1_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_1 … #define regPA_CL_VPORT_ZSCALE_1_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_1 … #define regPA_CL_VPORT_ZOFFSET_1_BASE_IDX … #define regPA_SC_VPORT_ZMIN_1 … #define regPA_SC_VPORT_ZMIN_1_BASE_IDX … #define regPA_SC_VPORT_ZMAX_1 … #define regPA_SC_VPORT_ZMAX_1_BASE_IDX … #define regPA_CL_VPORT_XSCALE_2 … #define regPA_CL_VPORT_XSCALE_2_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_2 … #define regPA_CL_VPORT_XOFFSET_2_BASE_IDX … #define regPA_CL_VPORT_YSCALE_2 … #define regPA_CL_VPORT_YSCALE_2_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_2 … #define regPA_CL_VPORT_YOFFSET_2_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_2 … #define regPA_CL_VPORT_ZSCALE_2_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_2 … #define regPA_CL_VPORT_ZOFFSET_2_BASE_IDX … #define regPA_SC_VPORT_ZMIN_2 … #define regPA_SC_VPORT_ZMIN_2_BASE_IDX … #define regPA_SC_VPORT_ZMAX_2 … #define regPA_SC_VPORT_ZMAX_2_BASE_IDX … #define regPA_CL_VPORT_XSCALE_3 … #define regPA_CL_VPORT_XSCALE_3_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_3 … #define regPA_CL_VPORT_XOFFSET_3_BASE_IDX … #define regPA_CL_VPORT_YSCALE_3 … #define regPA_CL_VPORT_YSCALE_3_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_3 … #define regPA_CL_VPORT_YOFFSET_3_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_3 … #define regPA_CL_VPORT_ZSCALE_3_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_3 … #define regPA_CL_VPORT_ZOFFSET_3_BASE_IDX … #define regPA_SC_VPORT_ZMIN_3 … #define regPA_SC_VPORT_ZMIN_3_BASE_IDX … #define regPA_SC_VPORT_ZMAX_3 … #define regPA_SC_VPORT_ZMAX_3_BASE_IDX … #define regPA_CL_VPORT_XSCALE_4 … #define regPA_CL_VPORT_XSCALE_4_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_4 … #define regPA_CL_VPORT_XOFFSET_4_BASE_IDX … #define regPA_CL_VPORT_YSCALE_4 … #define regPA_CL_VPORT_YSCALE_4_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_4 … #define regPA_CL_VPORT_YOFFSET_4_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_4 … #define regPA_CL_VPORT_ZSCALE_4_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_4 … #define regPA_CL_VPORT_ZOFFSET_4_BASE_IDX … #define regPA_SC_VPORT_ZMIN_4 … #define regPA_SC_VPORT_ZMIN_4_BASE_IDX … #define regPA_SC_VPORT_ZMAX_4 … #define regPA_SC_VPORT_ZMAX_4_BASE_IDX … #define regPA_CL_VPORT_XSCALE_5 … #define regPA_CL_VPORT_XSCALE_5_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_5 … #define regPA_CL_VPORT_XOFFSET_5_BASE_IDX … #define regPA_CL_VPORT_YSCALE_5 … #define regPA_CL_VPORT_YSCALE_5_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_5 … #define regPA_CL_VPORT_YOFFSET_5_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_5 … #define regPA_CL_VPORT_ZSCALE_5_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_5 … #define regPA_CL_VPORT_ZOFFSET_5_BASE_IDX … #define regPA_SC_VPORT_ZMIN_5 … #define regPA_SC_VPORT_ZMIN_5_BASE_IDX … #define regPA_SC_VPORT_ZMAX_5 … #define regPA_SC_VPORT_ZMAX_5_BASE_IDX … #define regPA_CL_VPORT_XSCALE_6 … #define regPA_CL_VPORT_XSCALE_6_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_6 … #define regPA_CL_VPORT_XOFFSET_6_BASE_IDX … #define regPA_CL_VPORT_YSCALE_6 … #define regPA_CL_VPORT_YSCALE_6_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_6 … #define regPA_CL_VPORT_YOFFSET_6_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_6 … #define regPA_CL_VPORT_ZSCALE_6_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_6 … #define regPA_CL_VPORT_ZOFFSET_6_BASE_IDX … #define regPA_SC_VPORT_ZMIN_6 … #define regPA_SC_VPORT_ZMIN_6_BASE_IDX … #define regPA_SC_VPORT_ZMAX_6 … #define regPA_SC_VPORT_ZMAX_6_BASE_IDX … #define regPA_CL_VPORT_XSCALE_7 … #define regPA_CL_VPORT_XSCALE_7_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_7 … #define regPA_CL_VPORT_XOFFSET_7_BASE_IDX … #define regPA_CL_VPORT_YSCALE_7 … #define regPA_CL_VPORT_YSCALE_7_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_7 … #define regPA_CL_VPORT_YOFFSET_7_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_7 … #define regPA_CL_VPORT_ZSCALE_7_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_7 … #define regPA_CL_VPORT_ZOFFSET_7_BASE_IDX … #define regPA_SC_VPORT_ZMIN_7 … #define regPA_SC_VPORT_ZMIN_7_BASE_IDX … #define regPA_SC_VPORT_ZMAX_7 … #define regPA_SC_VPORT_ZMAX_7_BASE_IDX … #define regPA_CL_VPORT_XSCALE_8 … #define regPA_CL_VPORT_XSCALE_8_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_8 … #define regPA_CL_VPORT_XOFFSET_8_BASE_IDX … #define regPA_CL_VPORT_YSCALE_8 … #define regPA_CL_VPORT_YSCALE_8_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_8 … #define regPA_CL_VPORT_YOFFSET_8_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_8 … #define regPA_CL_VPORT_ZSCALE_8_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_8 … #define regPA_CL_VPORT_ZOFFSET_8_BASE_IDX … #define regPA_SC_VPORT_ZMIN_8 … #define regPA_SC_VPORT_ZMIN_8_BASE_IDX … #define regPA_SC_VPORT_ZMAX_8 … #define regPA_SC_VPORT_ZMAX_8_BASE_IDX … #define regPA_CL_VPORT_XSCALE_9 … #define regPA_CL_VPORT_XSCALE_9_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_9 … #define regPA_CL_VPORT_XOFFSET_9_BASE_IDX … #define regPA_CL_VPORT_YSCALE_9 … #define regPA_CL_VPORT_YSCALE_9_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_9 … #define regPA_CL_VPORT_YOFFSET_9_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_9 … #define regPA_CL_VPORT_ZSCALE_9_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_9 … #define regPA_CL_VPORT_ZOFFSET_9_BASE_IDX … #define regPA_SC_VPORT_ZMIN_9 … #define regPA_SC_VPORT_ZMIN_9_BASE_IDX … #define regPA_SC_VPORT_ZMAX_9 … #define regPA_SC_VPORT_ZMAX_9_BASE_IDX … #define regPA_CL_VPORT_XSCALE_10 … #define regPA_CL_VPORT_XSCALE_10_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_10 … #define regPA_CL_VPORT_XOFFSET_10_BASE_IDX … #define regPA_CL_VPORT_YSCALE_10 … #define regPA_CL_VPORT_YSCALE_10_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_10 … #define regPA_CL_VPORT_YOFFSET_10_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_10 … #define regPA_CL_VPORT_ZSCALE_10_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_10 … #define regPA_CL_VPORT_ZOFFSET_10_BASE_IDX … #define regPA_SC_VPORT_ZMIN_10 … #define regPA_SC_VPORT_ZMIN_10_BASE_IDX … #define regPA_SC_VPORT_ZMAX_10 … #define regPA_SC_VPORT_ZMAX_10_BASE_IDX … #define regPA_CL_VPORT_XSCALE_11 … #define regPA_CL_VPORT_XSCALE_11_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_11 … #define regPA_CL_VPORT_XOFFSET_11_BASE_IDX … #define regPA_CL_VPORT_YSCALE_11 … #define regPA_CL_VPORT_YSCALE_11_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_11 … #define regPA_CL_VPORT_YOFFSET_11_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_11 … #define regPA_CL_VPORT_ZSCALE_11_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_11 … #define regPA_CL_VPORT_ZOFFSET_11_BASE_IDX … #define regPA_SC_VPORT_ZMIN_11 … #define regPA_SC_VPORT_ZMIN_11_BASE_IDX … #define regPA_SC_VPORT_ZMAX_11 … #define regPA_SC_VPORT_ZMAX_11_BASE_IDX … #define regPA_CL_VPORT_XSCALE_12 … #define regPA_CL_VPORT_XSCALE_12_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_12 … #define regPA_CL_VPORT_XOFFSET_12_BASE_IDX … #define regPA_CL_VPORT_YSCALE_12 … #define regPA_CL_VPORT_YSCALE_12_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_12 … #define regPA_CL_VPORT_YOFFSET_12_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_12 … #define regPA_CL_VPORT_ZSCALE_12_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_12 … #define regPA_CL_VPORT_ZOFFSET_12_BASE_IDX … #define regPA_SC_VPORT_ZMIN_12 … #define regPA_SC_VPORT_ZMIN_12_BASE_IDX … #define regPA_SC_VPORT_ZMAX_12 … #define regPA_SC_VPORT_ZMAX_12_BASE_IDX … #define regPA_CL_VPORT_XSCALE_13 … #define regPA_CL_VPORT_XSCALE_13_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_13 … #define regPA_CL_VPORT_XOFFSET_13_BASE_IDX … #define regPA_CL_VPORT_YSCALE_13 … #define regPA_CL_VPORT_YSCALE_13_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_13 … #define regPA_CL_VPORT_YOFFSET_13_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_13 … #define regPA_CL_VPORT_ZSCALE_13_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_13 … #define regPA_CL_VPORT_ZOFFSET_13_BASE_IDX … #define regPA_SC_VPORT_ZMIN_13 … #define regPA_SC_VPORT_ZMIN_13_BASE_IDX … #define regPA_SC_VPORT_ZMAX_13 … #define regPA_SC_VPORT_ZMAX_13_BASE_IDX … #define regPA_CL_VPORT_XSCALE_14 … #define regPA_CL_VPORT_XSCALE_14_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_14 … #define regPA_CL_VPORT_XOFFSET_14_BASE_IDX … #define regPA_CL_VPORT_YSCALE_14 … #define regPA_CL_VPORT_YSCALE_14_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_14 … #define regPA_CL_VPORT_YOFFSET_14_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_14 … #define regPA_CL_VPORT_ZSCALE_14_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_14 … #define regPA_CL_VPORT_ZOFFSET_14_BASE_IDX … #define regPA_SC_VPORT_ZMIN_14 … #define regPA_SC_VPORT_ZMIN_14_BASE_IDX … #define regPA_SC_VPORT_ZMAX_14 … #define regPA_SC_VPORT_ZMAX_14_BASE_IDX … #define regPA_CL_VPORT_XSCALE_15 … #define regPA_CL_VPORT_XSCALE_15_BASE_IDX … #define regPA_CL_VPORT_XOFFSET_15 … #define regPA_CL_VPORT_XOFFSET_15_BASE_IDX … #define regPA_CL_VPORT_YSCALE_15 … #define regPA_CL_VPORT_YSCALE_15_BASE_IDX … #define regPA_CL_VPORT_YOFFSET_15 … #define regPA_CL_VPORT_YOFFSET_15_BASE_IDX … #define regPA_CL_VPORT_ZSCALE_15 … #define regPA_CL_VPORT_ZSCALE_15_BASE_IDX … #define regPA_CL_VPORT_ZOFFSET_15 … #define regPA_CL_VPORT_ZOFFSET_15_BASE_IDX … #define regPA_SC_VPORT_ZMIN_15 … #define regPA_SC_VPORT_ZMIN_15_BASE_IDX … #define regPA_SC_VPORT_ZMAX_15 … #define regPA_SC_VPORT_ZMAX_15_BASE_IDX … #define regSPI_PS_IN_CONTROL … #define regSPI_PS_IN_CONTROL_BASE_IDX … #define regSPI_INTERP_CONTROL_0 … #define regSPI_INTERP_CONTROL_0_BASE_IDX … #define regSPI_SHADER_IDX_FORMAT … #define regSPI_SHADER_IDX_FORMAT_BASE_IDX … #define regSPI_SHADER_POS_FORMAT … #define regSPI_SHADER_POS_FORMAT_BASE_IDX … #define regSPI_SHADER_Z_FORMAT … #define regSPI_SHADER_Z_FORMAT_BASE_IDX … #define regSPI_SHADER_COL_FORMAT … #define regSPI_SHADER_COL_FORMAT_BASE_IDX … #define regSPI_BARYC_CNTL … #define regSPI_BARYC_CNTL_BASE_IDX … #define regSPI_PS_INPUT_ENA … #define regSPI_PS_INPUT_ENA_BASE_IDX … #define regSPI_PS_INPUT_ADDR … #define regSPI_PS_INPUT_ADDR_BASE_IDX … #define regSPI_PS_INPUT_CNTL_0 … #define regSPI_PS_INPUT_CNTL_0_BASE_IDX … #define regSPI_PS_INPUT_CNTL_1 … #define regSPI_PS_INPUT_CNTL_1_BASE_IDX … #define regSPI_PS_INPUT_CNTL_2 … #define regSPI_PS_INPUT_CNTL_2_BASE_IDX … #define regSPI_PS_INPUT_CNTL_3 … #define regSPI_PS_INPUT_CNTL_3_BASE_IDX … #define regSPI_PS_INPUT_CNTL_4 … #define regSPI_PS_INPUT_CNTL_4_BASE_IDX … #define regSPI_PS_INPUT_CNTL_5 … #define regSPI_PS_INPUT_CNTL_5_BASE_IDX … #define regSPI_PS_INPUT_CNTL_6 … #define regSPI_PS_INPUT_CNTL_6_BASE_IDX … #define regSPI_PS_INPUT_CNTL_7 … #define regSPI_PS_INPUT_CNTL_7_BASE_IDX … #define regSPI_PS_INPUT_CNTL_8 … #define regSPI_PS_INPUT_CNTL_8_BASE_IDX … #define regSPI_PS_INPUT_CNTL_9 … #define regSPI_PS_INPUT_CNTL_9_BASE_IDX … #define regSPI_PS_INPUT_CNTL_10 … #define regSPI_PS_INPUT_CNTL_10_BASE_IDX … #define regSPI_PS_INPUT_CNTL_11 … #define regSPI_PS_INPUT_CNTL_11_BASE_IDX … #define regSPI_PS_INPUT_CNTL_12 … #define regSPI_PS_INPUT_CNTL_12_BASE_IDX … #define regSPI_PS_INPUT_CNTL_13 … #define regSPI_PS_INPUT_CNTL_13_BASE_IDX … #define regSPI_PS_INPUT_CNTL_14 … #define regSPI_PS_INPUT_CNTL_14_BASE_IDX … #define regSPI_PS_INPUT_CNTL_15 … #define regSPI_PS_INPUT_CNTL_15_BASE_IDX … #define regSPI_PS_INPUT_CNTL_16 … #define regSPI_PS_INPUT_CNTL_16_BASE_IDX … #define regSPI_PS_INPUT_CNTL_17 … #define regSPI_PS_INPUT_CNTL_17_BASE_IDX … #define regSPI_PS_INPUT_CNTL_18 … #define regSPI_PS_INPUT_CNTL_18_BASE_IDX … #define regSPI_PS_INPUT_CNTL_19 … #define regSPI_PS_INPUT_CNTL_19_BASE_IDX … #define regSPI_PS_INPUT_CNTL_20 … #define regSPI_PS_INPUT_CNTL_20_BASE_IDX … #define regSPI_PS_INPUT_CNTL_21 … #define regSPI_PS_INPUT_CNTL_21_BASE_IDX … #define regSPI_PS_INPUT_CNTL_22 … #define regSPI_PS_INPUT_CNTL_22_BASE_IDX … #define regSPI_PS_INPUT_CNTL_23 … #define regSPI_PS_INPUT_CNTL_23_BASE_IDX … #define regSPI_PS_INPUT_CNTL_24 … #define regSPI_PS_INPUT_CNTL_24_BASE_IDX … #define regSPI_PS_INPUT_CNTL_25 … #define regSPI_PS_INPUT_CNTL_25_BASE_IDX … #define regSPI_PS_INPUT_CNTL_26 … #define regSPI_PS_INPUT_CNTL_26_BASE_IDX … #define regSPI_PS_INPUT_CNTL_27 … #define regSPI_PS_INPUT_CNTL_27_BASE_IDX … #define regSPI_PS_INPUT_CNTL_28 … #define regSPI_PS_INPUT_CNTL_28_BASE_IDX … #define regSPI_PS_INPUT_CNTL_29 … #define regSPI_PS_INPUT_CNTL_29_BASE_IDX … #define regSPI_PS_INPUT_CNTL_30 … #define regSPI_PS_INPUT_CNTL_30_BASE_IDX … #define regSPI_PS_INPUT_CNTL_31 … #define regSPI_PS_INPUT_CNTL_31_BASE_IDX … #define regSPI_BARYC_SSAA_CNTL … #define regSPI_BARYC_SSAA_CNTL_BASE_IDX … #define regSPI_TMPRING_SIZE … #define regSPI_TMPRING_SIZE_BASE_IDX … #define regSPI_GFX_SCRATCH_BASE_LO … #define regSPI_GFX_SCRATCH_BASE_LO_BASE_IDX … #define regSPI_GFX_SCRATCH_BASE_HI … #define regSPI_GFX_SCRATCH_BASE_HI_BASE_IDX … #define regSX_PS_DOWNCONVERT_CONTROL … #define regSX_PS_DOWNCONVERT_CONTROL_BASE_IDX … #define regSX_PS_DOWNCONVERT … #define regSX_PS_DOWNCONVERT_BASE_IDX … #define regSX_BLEND_OPT_EPSILON … #define regSX_BLEND_OPT_EPSILON_BASE_IDX … #define regSX_BLEND_OPT_CONTROL … #define regSX_BLEND_OPT_CONTROL_BASE_IDX … #define regSX_MRT0_BLEND_OPT … #define regSX_MRT0_BLEND_OPT_BASE_IDX … #define regSX_MRT1_BLEND_OPT … #define regSX_MRT1_BLEND_OPT_BASE_IDX … #define regSX_MRT2_BLEND_OPT … #define regSX_MRT2_BLEND_OPT_BASE_IDX … #define regSX_MRT3_BLEND_OPT … #define regSX_MRT3_BLEND_OPT_BASE_IDX … #define regSX_MRT4_BLEND_OPT … #define regSX_MRT4_BLEND_OPT_BASE_IDX … #define regSX_MRT5_BLEND_OPT … #define regSX_MRT5_BLEND_OPT_BASE_IDX … #define regSX_MRT6_BLEND_OPT … #define regSX_MRT6_BLEND_OPT_BASE_IDX … #define regSX_MRT7_BLEND_OPT … #define regSX_MRT7_BLEND_OPT_BASE_IDX … #define regCB_BLEND0_CONTROL … #define regCB_BLEND0_CONTROL_BASE_IDX … #define regCB_BLEND1_CONTROL … #define regCB_BLEND1_CONTROL_BASE_IDX … #define regCB_BLEND2_CONTROL … #define regCB_BLEND2_CONTROL_BASE_IDX … #define regCB_BLEND3_CONTROL … #define regCB_BLEND3_CONTROL_BASE_IDX … #define regCB_BLEND4_CONTROL … #define regCB_BLEND4_CONTROL_BASE_IDX … #define regCB_BLEND5_CONTROL … #define regCB_BLEND5_CONTROL_BASE_IDX … #define regCB_BLEND6_CONTROL … #define regCB_BLEND6_CONTROL_BASE_IDX … #define regCB_BLEND7_CONTROL … #define regCB_BLEND7_CONTROL_BASE_IDX … #define regPA_CL_POINT_X_RAD … #define regPA_CL_POINT_X_RAD_BASE_IDX … #define regPA_CL_POINT_Y_RAD … #define regPA_CL_POINT_Y_RAD_BASE_IDX … #define regPA_CL_POINT_SIZE … #define regPA_CL_POINT_SIZE_BASE_IDX … #define regPA_CL_POINT_CULL_RAD … #define regPA_CL_POINT_CULL_RAD_BASE_IDX … #define regGE_MAX_OUTPUT_PER_SUBGROUP … #define regGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX … #define regPA_CL_CLIP_CNTL … #define regPA_CL_CLIP_CNTL_BASE_IDX … #define regPA_CL_VTE_CNTL … #define regPA_CL_VTE_CNTL_BASE_IDX … #define regPA_CL_VS_OUT_CNTL … #define regPA_CL_VS_OUT_CNTL_BASE_IDX … #define regPA_SU_SC_MODE_CNTL … #define regPA_SU_SC_MODE_CNTL_BASE_IDX … #define regPA_CL_NANINF_CNTL … #define regPA_CL_NANINF_CNTL_BASE_IDX … #define regPA_SU_LINE_STIPPLE_CNTL … #define regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX … #define regPA_SU_LINE_STIPPLE_SCALE … #define regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX … #define regPA_SU_PRIM_FILTER_CNTL … #define regPA_SU_PRIM_FILTER_CNTL_BASE_IDX … #define regPA_SU_SMALL_PRIM_FILTER_CNTL … #define regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX … #define regPA_CL_NGG_CNTL … #define regPA_CL_NGG_CNTL_BASE_IDX … #define regPA_SU_OVER_RASTERIZATION_CNTL … #define regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX … #define regPA_STEREO_CNTL … #define regPA_STEREO_CNTL_BASE_IDX … #define regPA_STATE_STEREO_X … #define regPA_STATE_STEREO_X_BASE_IDX … #define regPA_CL_VRS_CNTL … #define regPA_CL_VRS_CNTL_BASE_IDX … #define regCB_TARGET_MASK … #define regCB_TARGET_MASK_BASE_IDX … #define regCB_SHADER_MASK … #define regCB_SHADER_MASK_BASE_IDX … #define regCB_COLOR_CONTROL … #define regCB_COLOR_CONTROL_BASE_IDX … #define regPA_SU_POINT_SIZE … #define regPA_SU_POINT_SIZE_BASE_IDX … #define regPA_SU_POINT_MINMAX … #define regPA_SU_POINT_MINMAX_BASE_IDX … #define regPA_SU_LINE_CNTL … #define regPA_SU_LINE_CNTL_BASE_IDX … #define regPA_SC_LINE_STIPPLE … #define regPA_SC_LINE_STIPPLE_BASE_IDX … #define regPA_SC_LINE_STIPPLE_RESET … #define regPA_SC_LINE_STIPPLE_RESET_BASE_IDX … #define regPA_SC_MODE_CNTL_0 … #define regPA_SC_MODE_CNTL_0_BASE_IDX … #define regPA_SC_MODE_CNTL_1 … #define regPA_SC_MODE_CNTL_1_BASE_IDX … #define regGE_SE_ENHANCE … #define regGE_SE_ENHANCE_BASE_IDX … #define regVGT_REUSE_OFF … #define regVGT_REUSE_OFF_BASE_IDX … #define regVGT_DRAW_PAYLOAD_CNTL … #define regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX … #define regDB_HTILE_SURFACE … #define regDB_HTILE_SURFACE_BASE_IDX … #define regDB_SRESULTS_COMPARE_STATE0 … #define regDB_SRESULTS_COMPARE_STATE0_BASE_IDX … #define regDB_SRESULTS_COMPARE_STATE1 … #define regDB_SRESULTS_COMPARE_STATE1_BASE_IDX … #define regVGT_GS_MAX_VERT_OUT … #define regVGT_GS_MAX_VERT_OUT_BASE_IDX … #define regVGT_GS_INSTANCE_CNT … #define regVGT_GS_INSTANCE_CNT_BASE_IDX … #define regGE_NGG_SUBGRP_CNTL … #define regGE_NGG_SUBGRP_CNTL_BASE_IDX … #define regPA_SU_POLY_OFFSET_DB_FMT_CNTL … #define regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX … #define regPA_SU_POLY_OFFSET_CLAMP … #define regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX … #define regPA_SU_POLY_OFFSET_FRONT_SCALE … #define regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX … #define regPA_SU_POLY_OFFSET_FRONT_OFFSET … #define regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX … #define regPA_SU_POLY_OFFSET_BACK_SCALE … #define regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX … #define regPA_SU_POLY_OFFSET_BACK_OFFSET … #define regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX … #define regPA_SC_HIZ_INFO … #define regPA_SC_HIZ_INFO_BASE_IDX … #define regPA_SC_HIS_INFO … #define regPA_SC_HIS_INFO_BASE_IDX … #define regPA_SC_HIZ_BASE … #define regPA_SC_HIZ_BASE_BASE_IDX … #define regPA_SC_HIZ_BASE_EXT … #define regPA_SC_HIZ_BASE_EXT_BASE_IDX … #define regPA_SC_HIZ_SIZE_XY … #define regPA_SC_HIZ_SIZE_XY_BASE_IDX … #define regPA_SC_HIS_BASE … #define regPA_SC_HIS_BASE_BASE_IDX … #define regPA_SC_HIS_BASE_EXT … #define regPA_SC_HIS_BASE_EXT_BASE_IDX … #define regPA_SC_HIS_SIZE_XY … #define regPA_SC_HIS_SIZE_XY_BASE_IDX … #define regPA_SC_BINNER_OUTPUT_TIMEOUT_CNTL … #define regPA_SC_BINNER_OUTPUT_TIMEOUT_CNTL_BASE_IDX … #define regPA_SC_BINNER_DYNAMIC_BATCH_LIMIT … #define regPA_SC_BINNER_DYNAMIC_BATCH_LIMIT_BASE_IDX … #define regPA_SC_HISZ_CONTROL … #define regPA_SC_HISZ_CONTROL_BASE_IDX … #define regPA_SC_HISZ_RENDER_OVERRIDE … #define regPA_SC_HISZ_RENDER_OVERRIDE_BASE_IDX … #define regPA_SC_LINE_CNTL … #define regPA_SC_LINE_CNTL_BASE_IDX … #define regPA_SC_AA_CONFIG … #define regPA_SC_AA_CONFIG_BASE_IDX … #define regPA_SU_VTX_CNTL … #define regPA_SU_VTX_CNTL_BASE_IDX … #define regPA_SC_CENTROID_PRIORITY_0 … #define regPA_SC_CENTROID_PRIORITY_0_BASE_IDX … #define regPA_SC_CENTROID_PRIORITY_1 … #define regPA_SC_CENTROID_PRIORITY_1_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 … #define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX … #define regPA_SC_AA_MASK_X0Y0_X1Y0 … #define regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX … #define regPA_SC_AA_MASK_X0Y1_X1Y1 … #define regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX … #define regPA_SC_BINNER_OUTPUT_TIMEOUT_COUNTER … #define regPA_SC_BINNER_OUTPUT_TIMEOUT_COUNTER_BASE_IDX … #define regPA_SC_BINNER_CNTL_0 … #define regPA_SC_BINNER_CNTL_0_BASE_IDX … #define regPA_SC_BINNER_CNTL_1 … #define regPA_SC_BINNER_CNTL_1_BASE_IDX … #define regPA_SC_BINNER_CNTL_2 … #define regPA_SC_BINNER_CNTL_2_BASE_IDX … #define regPA_SC_NGG_MODE_CNTL … #define regPA_SC_NGG_MODE_CNTL_BASE_IDX … #define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL … #define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX … #define regPA_SC_SHADER_CONTROL … #define regPA_SC_SHADER_CONTROL_BASE_IDX … #define regPA_SC_SAMPLE_PROPERTIES … #define regPA_SC_SAMPLE_PROPERTIES_BASE_IDX … #define regCB_COLOR0_BASE … #define regCB_COLOR0_BASE_BASE_IDX … #define regCB_COLOR0_VIEW … #define regCB_COLOR0_VIEW_BASE_IDX … #define regCB_COLOR0_VIEW2 … #define regCB_COLOR0_VIEW2_BASE_IDX … #define regCB_COLOR0_ATTRIB … #define regCB_COLOR0_ATTRIB_BASE_IDX … #define regCB_COLOR0_FDCC_CONTROL … #define regCB_COLOR0_FDCC_CONTROL_BASE_IDX … #define regCB_COLOR0_ATTRIB2 … #define regCB_COLOR0_ATTRIB2_BASE_IDX … #define regCB_COLOR0_ATTRIB3 … #define regCB_COLOR0_ATTRIB3_BASE_IDX … #define regCB_COLOR1_BASE … #define regCB_COLOR1_BASE_BASE_IDX … #define regCB_COLOR1_VIEW … #define regCB_COLOR1_VIEW_BASE_IDX … #define regCB_COLOR1_VIEW2 … #define regCB_COLOR1_VIEW2_BASE_IDX … #define regCB_COLOR1_ATTRIB … #define regCB_COLOR1_ATTRIB_BASE_IDX … #define regCB_COLOR1_FDCC_CONTROL … #define regCB_COLOR1_FDCC_CONTROL_BASE_IDX … #define regCB_COLOR1_ATTRIB2 … #define regCB_COLOR1_ATTRIB2_BASE_IDX … #define regCB_COLOR1_ATTRIB3 … #define regCB_COLOR1_ATTRIB3_BASE_IDX … #define regCB_COLOR2_BASE … #define regCB_COLOR2_BASE_BASE_IDX … #define regCB_COLOR2_VIEW … #define regCB_COLOR2_VIEW_BASE_IDX … #define regCB_COLOR2_VIEW2 … #define regCB_COLOR2_VIEW2_BASE_IDX … #define regCB_COLOR2_ATTRIB … #define regCB_COLOR2_ATTRIB_BASE_IDX … #define regCB_COLOR2_FDCC_CONTROL … #define regCB_COLOR2_FDCC_CONTROL_BASE_IDX … #define regCB_COLOR2_ATTRIB2 … #define regCB_COLOR2_ATTRIB2_BASE_IDX … #define regCB_COLOR2_ATTRIB3 … #define regCB_COLOR2_ATTRIB3_BASE_IDX … #define regCB_COLOR3_BASE … #define regCB_COLOR3_BASE_BASE_IDX … #define regCB_COLOR3_VIEW … #define regCB_COLOR3_VIEW_BASE_IDX … #define regCB_COLOR3_VIEW2 … #define regCB_COLOR3_VIEW2_BASE_IDX … #define regCB_COLOR3_ATTRIB … #define regCB_COLOR3_ATTRIB_BASE_IDX … #define regCB_COLOR3_FDCC_CONTROL … #define regCB_COLOR3_FDCC_CONTROL_BASE_IDX … #define regCB_COLOR3_ATTRIB2 … #define regCB_COLOR3_ATTRIB2_BASE_IDX … #define regCB_COLOR3_ATTRIB3 … #define regCB_COLOR3_ATTRIB3_BASE_IDX … #define regCB_COLOR4_BASE … #define regCB_COLOR4_BASE_BASE_IDX … #define regCB_COLOR4_VIEW … #define regCB_COLOR4_VIEW_BASE_IDX … #define regCB_COLOR4_VIEW2 … #define regCB_COLOR4_VIEW2_BASE_IDX … #define regCB_COLOR4_ATTRIB … #define regCB_COLOR4_ATTRIB_BASE_IDX … #define regCB_COLOR4_FDCC_CONTROL … #define regCB_COLOR4_FDCC_CONTROL_BASE_IDX … #define regCB_COLOR4_ATTRIB2 … #define regCB_COLOR4_ATTRIB2_BASE_IDX … #define regCB_COLOR4_ATTRIB3 … #define regCB_COLOR4_ATTRIB3_BASE_IDX … #define regCB_COLOR5_BASE … #define regCB_COLOR5_BASE_BASE_IDX … #define regCB_COLOR5_VIEW … #define regCB_COLOR5_VIEW_BASE_IDX … #define regCB_COLOR5_VIEW2 … #define regCB_COLOR5_VIEW2_BASE_IDX … #define regCB_COLOR5_ATTRIB … #define regCB_COLOR5_ATTRIB_BASE_IDX … #define regCB_COLOR5_FDCC_CONTROL … #define regCB_COLOR5_FDCC_CONTROL_BASE_IDX … #define regCB_COLOR5_ATTRIB2 … #define regCB_COLOR5_ATTRIB2_BASE_IDX … #define regCB_COLOR5_ATTRIB3 … #define regCB_COLOR5_ATTRIB3_BASE_IDX … #define regCB_COLOR6_BASE … #define regCB_COLOR6_BASE_BASE_IDX … #define regCB_COLOR6_VIEW … #define regCB_COLOR6_VIEW_BASE_IDX … #define regCB_COLOR6_VIEW2 … #define regCB_COLOR6_VIEW2_BASE_IDX … #define regCB_COLOR6_ATTRIB … #define regCB_COLOR6_ATTRIB_BASE_IDX … #define regCB_COLOR6_FDCC_CONTROL … #define regCB_COLOR6_FDCC_CONTROL_BASE_IDX … #define regCB_COLOR6_ATTRIB2 … #define regCB_COLOR6_ATTRIB2_BASE_IDX … #define regCB_COLOR6_ATTRIB3 … #define regCB_COLOR6_ATTRIB3_BASE_IDX … #define regCB_COLOR7_BASE … #define regCB_COLOR7_BASE_BASE_IDX … #define regCB_COLOR7_VIEW … #define regCB_COLOR7_VIEW_BASE_IDX … #define regCB_COLOR7_VIEW2 … #define regCB_COLOR7_VIEW2_BASE_IDX … #define regCB_COLOR7_ATTRIB … #define regCB_COLOR7_ATTRIB_BASE_IDX … #define regCB_COLOR7_FDCC_CONTROL … #define regCB_COLOR7_FDCC_CONTROL_BASE_IDX … #define regCB_COLOR7_ATTRIB2 … #define regCB_COLOR7_ATTRIB2_BASE_IDX … #define regCB_COLOR7_ATTRIB3 … #define regCB_COLOR7_ATTRIB3_BASE_IDX … #define regCB_COLOR0_BASE_EXT … #define regCB_COLOR0_BASE_EXT_BASE_IDX … #define regCB_COLOR1_BASE_EXT … #define regCB_COLOR1_BASE_EXT_BASE_IDX … #define regCB_COLOR2_BASE_EXT … #define regCB_COLOR2_BASE_EXT_BASE_IDX … #define regCB_COLOR3_BASE_EXT … #define regCB_COLOR3_BASE_EXT_BASE_IDX … #define regCB_COLOR4_BASE_EXT … #define regCB_COLOR4_BASE_EXT_BASE_IDX … #define regCB_COLOR5_BASE_EXT … #define regCB_COLOR5_BASE_EXT_BASE_IDX … #define regCB_COLOR6_BASE_EXT … #define regCB_COLOR6_BASE_EXT_BASE_IDX … #define regCB_COLOR7_BASE_EXT … #define regCB_COLOR7_BASE_EXT_BASE_IDX … #define regCB_COLOR0_INFO … #define regCB_COLOR0_INFO_BASE_IDX … #define regCB_COLOR1_INFO … #define regCB_COLOR1_INFO_BASE_IDX … #define regCB_COLOR2_INFO … #define regCB_COLOR2_INFO_BASE_IDX … #define regCB_COLOR3_INFO … #define regCB_COLOR3_INFO_BASE_IDX … #define regCB_COLOR4_INFO … #define regCB_COLOR4_INFO_BASE_IDX … #define regCB_COLOR5_INFO … #define regCB_COLOR5_INFO_BASE_IDX … #define regCB_COLOR6_INFO … #define regCB_COLOR6_INFO_BASE_IDX … #define regCB_COLOR7_INFO … #define regCB_COLOR7_INFO_BASE_IDX … #define regCB_MEM0_INFO … #define regCB_MEM0_INFO_BASE_IDX … #define regCB_MEM1_INFO … #define regCB_MEM1_INFO_BASE_IDX … #define regCB_MEM2_INFO … #define regCB_MEM2_INFO_BASE_IDX … #define regCB_MEM3_INFO … #define regCB_MEM3_INFO_BASE_IDX … #define regCB_MEM4_INFO … #define regCB_MEM4_INFO_BASE_IDX … #define regCB_MEM5_INFO … #define regCB_MEM5_INFO_BASE_IDX … #define regCB_MEM6_INFO … #define regCB_MEM6_INFO_BASE_IDX … #define regCB_MEM7_INFO … #define regCB_MEM7_INFO_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_pfvf_padec // base address: 0x2a500 #define regPA_SC_VRS_SURFACE_CNTL … #define regPA_SC_VRS_SURFACE_CNTL_BASE_IDX … #define regPA_SC_ENHANCE … #define regPA_SC_ENHANCE_BASE_IDX … #define regPA_SC_ENHANCE_1 … #define regPA_SC_ENHANCE_1_BASE_IDX … #define regPA_SC_ENHANCE_2 … #define regPA_SC_ENHANCE_2_BASE_IDX … #define regPA_SC_ENHANCE_3 … #define regPA_SC_ENHANCE_3_BASE_IDX … #define regPA_SC_BINNER_CNTL_OVERRIDE … #define regPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX … #define regPA_SC_PBB_OVERRIDE_FLAG … #define regPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX … #define regPA_SC_DSM_CNTL … #define regPA_SC_DSM_CNTL_BASE_IDX … #define regPA_SC_TILE_STEERING_CREST_OVERRIDE … #define regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX … #define regPA_SC_FIFO_SIZE … #define regPA_SC_FIFO_SIZE_BASE_IDX … #define regPA_SC_IF_FIFO_SIZE … #define regPA_SC_IF_FIFO_SIZE_BASE_IDX … #define regPA_SC_PACKER_WAVE_ID_CNTL … #define regPA_SC_PACKER_WAVE_ID_CNTL_BASE_IDX … #define regPA_SC_ATM_CNTL … #define regPA_SC_ATM_CNTL_BASE_IDX … #define regPA_SC_PKR_WAVE_TABLE_CNTL … #define regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX … #define regPA_SC_FORCE_EOV_MAX_CNTS … #define regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX … #define regPA_SC_BINNER_EVENT_CNTL_0 … #define regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX … #define regPA_SC_BINNER_EVENT_CNTL_1 … #define regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX … #define regPA_SC_BINNER_EVENT_CNTL_2 … #define regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX … #define regPA_SC_BINNER_EVENT_CNTL_3 … #define regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX … #define regPA_SC_BINNER_TIMEOUT_COUNTER … #define regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX … #define regPA_SC_BINNER_PERF_CNTL_0 … #define regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX … #define regPA_SC_BINNER_PERF_CNTL_1 … #define regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX … #define regPA_SC_BINNER_PERF_CNTL_2 … #define regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX … #define regPA_SC_BINNER_PERF_CNTL_3 … #define regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX … #define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK … #define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX … #define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK … #define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX … #define regPA_SC_TRAP_SCREEN_HV_LOCK … #define regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX … #define regPA_PH_INTERFACE_FIFO_SIZE … #define regPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX … #define regPA_PH_ENHANCE … #define regPA_PH_ENHANCE_BASE_IDX … #define regPA_SC_VRS_SURFACE_CNTL_1 … #define regPA_SC_VRS_SURFACE_CNTL_1_BASE_IDX … #define regPA_SC_HIZ_SURFACE_CNTL … #define regPA_SC_HIZ_SURFACE_CNTL_BASE_IDX … #define regPA_SC_HIS_SURFACE_CNTL … #define regPA_SC_HIS_SURFACE_CNTL_BASE_IDX … #define regPA_SC_HIZ_DEBUG … #define regPA_SC_HIZ_DEBUG_BASE_IDX … #define regPA_SC_HIS_DEBUG … #define regPA_SC_HIS_DEBUG_BASE_IDX … #define regSC_MEM_SCOPE … #define regSC_MEM_SCOPE_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_pfvf_sqdec // base address: 0x2a780 #define regSQ_RUNTIME_CONFIG … #define regSQ_RUNTIME_CONFIG_BASE_IDX … #define regSQ_DEBUG_STS_GLOBAL … #define regSQ_DEBUG_STS_GLOBAL_BASE_IDX … #define regSQ_DEBUG_STS_GLOBAL2 … #define regSQ_DEBUG_STS_GLOBAL2_BASE_IDX … #define regSH_MEM_BASES … #define regSH_MEM_BASES_BASE_IDX … #define regSH_MEM_CONFIG … #define regSH_MEM_CONFIG_BASE_IDX … #define regSQ_DEBUG … #define regSQ_DEBUG_BASE_IDX … #define regSQ_SHADER_TBA_LO … #define regSQ_SHADER_TBA_LO_BASE_IDX … #define regSQ_SHADER_TBA_HI … #define regSQ_SHADER_TBA_HI_BASE_IDX … #define regSQ_SHADER_TMA_LO … #define regSQ_SHADER_TMA_LO_BASE_IDX … #define regSQ_SHADER_TMA_HI … #define regSQ_SHADER_TMA_HI_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_pfonly_spidec // base address: 0x2e500 #define regSPI_CDBG_SYS_GFX … #define regSPI_CDBG_SYS_GFX_BASE_IDX … #define regSPI_CDBG_SYS_HP3D … #define regSPI_CDBG_SYS_HP3D_BASE_IDX … #define regSPI_CDBG_SYS_CS0 … #define regSPI_CDBG_SYS_CS0_BASE_IDX … #define regSPI_GDBG_WAVE_CNTL … #define regSPI_GDBG_WAVE_CNTL_BASE_IDX … #define regSPI_GDBG_TRAP_CONFIG … #define regSPI_GDBG_TRAP_CONFIG_BASE_IDX … #define regSPI_GDBG_WAVE_CNTL3 … #define regSPI_GDBG_WAVE_CNTL3_BASE_IDX … #define regSPI_RESET_DEBUG … #define regSPI_RESET_DEBUG_BASE_IDX … #define regGDS_COMPUTE_MAX_WAVE_ID … #define regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX … #define regSPI_ARB_CNTL_0 … #define regSPI_ARB_CNTL_0_BASE_IDX … #define regSPI_FEATURE_CTRL … #define regSPI_FEATURE_CTRL_BASE_IDX … #define regSPI_SHADER_RSRC_LIMIT_CTRL … #define regSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX … #define regPC_CONFIG_CNTL_0 … #define regPC_CONFIG_CNTL_0_BASE_IDX … #define regPC_CONFIG_CNTL_1 … #define regPC_CONFIG_CNTL_1_BASE_IDX … #define regSPI_COMPUTE_WF_CTX_SAVE_STATUS … #define regSPI_COMPUTE_WF_CTX_SAVE_STATUS_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_pfonly_utcl1dec // base address: 0x2e600 #define regUTCL1_CTRL_0 … #define regUTCL1_CTRL_0_BASE_IDX … #define regUTCL1_UTCL0_INVREQ_DISABLE … #define regUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX … #define regUTCL1_CTRL_2 … #define regUTCL1_CTRL_2_BASE_IDX … #define regUTCL1_FIFO_SIZING … #define regUTCL1_FIFO_SIZING_BASE_IDX … #define regGCRD_SA0_TARGETS_DISABLE … #define regGCRD_SA0_TARGETS_DISABLE_BASE_IDX … #define regGCRD_SA1_TARGETS_DISABLE … #define regGCRD_SA1_TARGETS_DISABLE_BASE_IDX … #define regGCRD_CREDIT_SAFE … #define regGCRD_CREDIT_SAFE_BASE_IDX … #define regUTCL1_IDENTITY_MODE0 … #define regUTCL1_IDENTITY_MODE0_BASE_IDX … #define regUTCL1_IDENTITY_MODE1 … #define regUTCL1_IDENTITY_MODE1_BASE_IDX … #define regUTCL1_IDENTITY_MODE2 … #define regUTCL1_IDENTITY_MODE2_BASE_IDX … #define regUTCL1_IDENTITY_MODE3 … #define regUTCL1_IDENTITY_MODE3_BASE_IDX … #define regUTCL1_IDENTITY_MODE4 … #define regUTCL1_IDENTITY_MODE4_BASE_IDX … #define regUTCL1_IDENTITY_MODE5 … #define regUTCL1_IDENTITY_MODE5_BASE_IDX … #define regUTCL1_IDENTITY_MODE6 … #define regUTCL1_IDENTITY_MODE6_BASE_IDX … #define regUTCL1_IDENTITY_MODE7 … #define regUTCL1_IDENTITY_MODE7_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_pfonly_tcpdec // base address: 0x2e680 #define regTCP_INVALIDATE … #define regTCP_INVALIDATE_BASE_IDX … #define regTCP_STATUS … #define regTCP_STATUS_BASE_IDX … #define regTCP_CNTL … #define regTCP_CNTL_BASE_IDX … #define regTCP_CNTL2 … #define regTCP_CNTL2_BASE_IDX … #define regTCP_CREDIT … #define regTCP_CREDIT_BASE_IDX … #define regTCP_COMPRESSION_CNTL … #define regTCP_COMPRESSION_CNTL_BASE_IDX … #define regTCP_ARB … #define regTCP_ARB_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_pfonly2_spidec // base address: 0x2f000 #define regSPI_RESOURCE_RESERVE_CU_0 … #define regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_1 … #define regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_2 … #define regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_3 … #define regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_4 … #define regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_5 … #define regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_6 … #define regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_7 … #define regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_8 … #define regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_9 … #define regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_10 … #define regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_11 … #define regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_12 … #define regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_13 … #define regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_14 … #define regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX … #define regSPI_RESOURCE_RESERVE_CU_15 … #define regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_0 … #define regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_1 … #define regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_2 … #define regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_3 … #define regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_4 … #define regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_5 … #define regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_6 … #define regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_7 … #define regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_8 … #define regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_9 … #define regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_10 … #define regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_11 … #define regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_12 … #define regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_13 … #define regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_14 … #define regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX … #define regSPI_RESOURCE_RESERVE_EN_CU_15 … #define regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_gfxudec // base address: 0x30000 #define regVGT_TF_RING_SIZE … #define regVGT_TF_RING_SIZE_BASE_IDX … #define regVGT_HS_OFFCHIP_PARAM … #define regVGT_HS_OFFCHIP_PARAM_BASE_IDX … #define regGE_POS_RING_BASE … #define regGE_POS_RING_BASE_BASE_IDX … #define regGE_POS_RING_SIZE … #define regGE_POS_RING_SIZE_BASE_IDX … #define regGE_PRIM_RING_BASE … #define regGE_PRIM_RING_BASE_BASE_IDX … #define regGE_PRIM_RING_SIZE … #define regGE_PRIM_RING_SIZE_BASE_IDX … #define regPA_SU_LINE_STIPPLE_VALUE … #define regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX … #define regPA_SC_LINE_STIPPLE_STATE … #define regPA_SC_LINE_STIPPLE_STATE_BASE_IDX … #define regPA_SC_SCREEN_EXTENT_MIN_0 … #define regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX … #define regPA_SC_SCREEN_EXTENT_MAX_0 … #define regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX … #define regPA_SC_SCREEN_EXTENT_MIN_1 … #define regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX … #define regPA_SC_SCREEN_EXTENT_MAX_1 … #define regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX … #define regPA_SC_P3D_TRAP_SCREEN_HV_EN … #define regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX … #define regPA_SC_P3D_TRAP_SCREEN_H … #define regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX … #define regPA_SC_P3D_TRAP_SCREEN_V … #define regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX … #define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE … #define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX … #define regPA_SC_P3D_TRAP_SCREEN_COUNT … #define regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX … #define regPA_SC_HP3D_TRAP_SCREEN_HV_EN … #define regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX … #define regPA_SC_HP3D_TRAP_SCREEN_H … #define regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX … #define regPA_SC_HP3D_TRAP_SCREEN_V … #define regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX … #define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE … #define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX … #define regPA_SC_HP3D_TRAP_SCREEN_COUNT … #define regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX … #define regPA_SC_TRAP_SCREEN_HV_EN … #define regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX … #define regPA_SC_TRAP_SCREEN_H … #define regPA_SC_TRAP_SCREEN_H_BASE_IDX … #define regPA_SC_TRAP_SCREEN_V … #define regPA_SC_TRAP_SCREEN_V_BASE_IDX … #define regPA_SC_TRAP_SCREEN_OCCURRENCE … #define regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX … #define regPA_SC_TRAP_SCREEN_COUNT … #define regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX … #define regSQ_THREAD_TRACE_USERDATA_0 … #define regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX … #define regSQ_THREAD_TRACE_USERDATA_1 … #define regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX … #define regSQ_THREAD_TRACE_USERDATA_2 … #define regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX … #define regSQ_THREAD_TRACE_USERDATA_3 … #define regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX … #define regSQ_THREAD_TRACE_USERDATA_4 … #define regSQ_THREAD_TRACE_USERDATA_4_BASE_IDX … #define regSQ_THREAD_TRACE_USERDATA_5 … #define regSQ_THREAD_TRACE_USERDATA_5_BASE_IDX … #define regSQ_THREAD_TRACE_USERDATA_6 … #define regSQ_THREAD_TRACE_USERDATA_6_BASE_IDX … #define regSQ_THREAD_TRACE_USERDATA_7 … #define regSQ_THREAD_TRACE_USERDATA_7_BASE_IDX … #define regSQC_CACHES … #define regSQC_CACHES_BASE_IDX … #define regTA_CS_BC_BASE_ADDR … #define regTA_CS_BC_BASE_ADDR_BASE_IDX … #define regTA_CS_BC_BASE_ADDR_HI … #define regTA_CS_BC_BASE_ADDR_HI_BASE_IDX … #define regDB_OCCLUSION_COUNT0_LOW … #define regDB_OCCLUSION_COUNT0_LOW_BASE_IDX … #define regDB_OCCLUSION_COUNT0_HI … #define regDB_OCCLUSION_COUNT0_HI_BASE_IDX … #define regDB_OCCLUSION_COUNT1_LOW … #define regDB_OCCLUSION_COUNT1_LOW_BASE_IDX … #define regDB_OCCLUSION_COUNT1_HI … #define regDB_OCCLUSION_COUNT1_HI_BASE_IDX … #define regDB_OCCLUSION_COUNT2_LOW … #define regDB_OCCLUSION_COUNT2_LOW_BASE_IDX … #define regDB_OCCLUSION_COUNT2_HI … #define regDB_OCCLUSION_COUNT2_HI_BASE_IDX … #define regDB_OCCLUSION_COUNT3_LOW … #define regDB_OCCLUSION_COUNT3_LOW_BASE_IDX … #define regDB_OCCLUSION_COUNT3_HI … #define regDB_OCCLUSION_COUNT3_HI_BASE_IDX … #define regSPI_CONFIG_CNTL … #define regSPI_CONFIG_CNTL_BASE_IDX … #define regSPI_CONFIG_CNTL_1 … #define regSPI_CONFIG_CNTL_1_BASE_IDX … #define regSPI_CONFIG_CNTL_2 … #define regSPI_CONFIG_CNTL_2_BASE_IDX … #define regSPI_GS_THROTTLE_CNTL1 … #define regSPI_GS_THROTTLE_CNTL1_BASE_IDX … #define regSPI_GS_THROTTLE_CNTL2 … #define regSPI_GS_THROTTLE_CNTL2_BASE_IDX … #define regSPI_ATTRIBUTE_RING_BASE … #define regSPI_ATTRIBUTE_RING_BASE_BASE_IDX … #define regSPI_ATTRIBUTE_RING_SIZE … #define regSPI_ATTRIBUTE_RING_SIZE_BASE_IDX … #define regSPI_SQG_EVENT_CTL … #define regSPI_SQG_EVENT_CTL_BASE_IDX … #define regSPI_GRP_LAUNCH_GUARANTEE_ENABLE … #define regSPI_GRP_LAUNCH_GUARANTEE_ENABLE_BASE_IDX … #define regSPI_GRP_LAUNCH_GUARANTEE_CTRL … #define regSPI_GRP_LAUNCH_GUARANTEE_CTRL_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_gl1dec // base address: 0x33400 #define regGL1_ARB_CTRL … #define regGL1_ARB_CTRL_BASE_IDX … #define regGL1_DRAM_BURST_MASK … #define regGL1_DRAM_BURST_MASK_BASE_IDX … #define regGL1_ARB_STATUS … #define regGL1_ARB_STATUS_BASE_IDX … #define regGL1_DRAM_BURST_CTRL … #define regGL1_DRAM_BURST_CTRL_BASE_IDX … #define regGL1I_GL1R_REP_FGCG_OVERRIDE … #define regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX … #define regGL1A_GL1C_CREDITS … #define regGL1A_GL1C_CREDITS_BASE_IDX … #define regGL1A_CLIENT_FREE_DELAY … #define regGL1A_CLIENT_FREE_DELAY_BASE_IDX … #define regGL1A_COMPRESSION_MODE … #define regGL1A_COMPRESSION_MODE_BASE_IDX … #define regGL1A_COMPRESSOR_OVERRIDE … #define regGL1A_COMPRESSOR_OVERRIDE_BASE_IDX … #define regGL1X_ARB_CTRL … #define regGL1X_ARB_CTRL_BASE_IDX … #define regGL1X_DRAM_BURST_MASK … #define regGL1X_DRAM_BURST_MASK_BASE_IDX … #define regGL1X_ARB_STATUS … #define regGL1X_ARB_STATUS_BASE_IDX … #define regGL1X_DRAM_BURST_CTRL … #define regGL1X_DRAM_BURST_CTRL_BASE_IDX … #define regGL1XI_GL1XR_REP_FGCG_OVERRIDE … #define regGL1XI_GL1XR_REP_FGCG_OVERRIDE_BASE_IDX … #define regGL1XA_GL1XC_CREDITS … #define regGL1XA_GL1XC_CREDITS_BASE_IDX … #define regGL1XA_CLIENT_FREE_DELAY … #define regGL1XA_CLIENT_FREE_DELAY_BASE_IDX … #define regGL1XA_COMPRESSION_MODE … #define regGL1XA_COMPRESSION_MODE_BASE_IDX … #define regGL1XA_COMPRESSOR_OVERRIDE … #define regGL1XA_COMPRESSOR_OVERRIDE_BASE_IDX … #define regGL1C_CTRL … #define regGL1C_CTRL_BASE_IDX … #define regGL1C_STATUS … #define regGL1C_STATUS_BASE_IDX … #define regGL1C_UTCL0_CNTL1 … #define regGL1C_UTCL0_CNTL1_BASE_IDX … #define regGL1C_UTCL0_CNTL2 … #define regGL1C_UTCL0_CNTL2_BASE_IDX … #define regGL1C_UTCL0_STATUS … #define regGL1C_UTCL0_STATUS_BASE_IDX … #define regGL1C_UTCL0_RETRY … #define regGL1C_UTCL0_RETRY_BASE_IDX … #define regGL1C_CTRL2 … #define regGL1C_CTRL2_BASE_IDX … #define regGL1XC_CTRL … #define regGL1XC_CTRL_BASE_IDX … #define regGL1XC_STATUS … #define regGL1XC_STATUS_BASE_IDX … #define regGL1XC_UTCL0_CNTL1 … #define regGL1XC_UTCL0_CNTL1_BASE_IDX … #define regGL1XC_UTCL0_CNTL2 … #define regGL1XC_UTCL0_CNTL2_BASE_IDX … #define regGL1XC_UTCL0_STATUS … #define regGL1XC_UTCL0_STATUS_BASE_IDX … #define regGL1XC_UTCL0_RETRY … #define regGL1XC_UTCL0_RETRY_BASE_IDX … #define regGL1XC_CTRL2 … #define regGL1XC_CTRL2_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_pfonly_secacdec // base address: 0x33a00 #define regSE_CAC_CTRL_1 … #define regSE_CAC_CTRL_1_BASE_IDX … #define regSE_CAC_CTRL_2 … #define regSE_CAC_CTRL_2_BASE_IDX … #define regSE_CAC_SOFT_CTRL … #define regSE_CAC_SOFT_CTRL_BASE_IDX … #define regSE_CAC_OVR_VAL_LOWER … #define regSE_CAC_OVR_VAL_LOWER_BASE_IDX … #define regSE_CAC_OVR_VAL_UPPER … #define regSE_CAC_OVR_VAL_UPPER_BASE_IDX … #define regSE_CAC_WINDOW_AGGR_VALUE_LO … #define regSE_CAC_WINDOW_AGGR_VALUE_LO_BASE_IDX … #define regSE_CAC_WINDOW_AGGR_VALUE_HI … #define regSE_CAC_WINDOW_AGGR_VALUE_HI_BASE_IDX … #define regSE_CAC_WINDOW_GFXCLK_CYCLE … #define regSE_CAC_WINDOW_GFXCLK_CYCLE_BASE_IDX … #define regDIDT_EDC_CTRL … #define regDIDT_EDC_CTRL_BASE_IDX … #define regDIDT_EDC_THROTTLE_CTRL … #define regDIDT_EDC_THROTTLE_CTRL_BASE_IDX … #define regDIDT_EDC_THRESHOLD … #define regDIDT_EDC_THRESHOLD_BASE_IDX … #define regDIDT_EDC_STRETCH_THRESHOLD … #define regDIDT_EDC_STRETCH_THRESHOLD_BASE_IDX … #define regDIDT_EDC_STALL_PATTERN_1_2 … #define regDIDT_EDC_STALL_PATTERN_1_2_BASE_IDX … #define regDIDT_EDC_STALL_PATTERN_3_4 … #define regDIDT_EDC_STALL_PATTERN_3_4_BASE_IDX … #define regDIDT_EDC_STALL_PATTERN_5_6 … #define regDIDT_EDC_STALL_PATTERN_5_6_BASE_IDX … #define regDIDT_EDC_STALL_PATTERN_7 … #define regDIDT_EDC_STALL_PATTERN_7_BASE_IDX … #define regDIDT_EDC_STATUS … #define regDIDT_EDC_STATUS_BASE_IDX … #define regDIDT_EDC_OVERFLOW … #define regDIDT_EDC_OVERFLOW_BASE_IDX … #define regDIDT_EDC_ROLLING_POWER_DELTA … #define regDIDT_EDC_ROLLING_POWER_DELTA_BASE_IDX … #define regDIDT_EDC_STALL_PERF_COUNTER … #define regDIDT_EDC_STALL_PERF_COUNTER_BASE_IDX … #define regSE_CAC_WEIGHT_TA_0 … #define regSE_CAC_WEIGHT_TA_0_BASE_IDX … #define regSE_CAC_WEIGHT_TA_1 … #define regSE_CAC_WEIGHT_TA_1_BASE_IDX … #define regSE_CAC_WEIGHT_TA_2 … #define regSE_CAC_WEIGHT_TA_2_BASE_IDX … #define regSE_CAC_WEIGHT_TD_0 … #define regSE_CAC_WEIGHT_TD_0_BASE_IDX … #define regSE_CAC_WEIGHT_TD_1 … #define regSE_CAC_WEIGHT_TD_1_BASE_IDX … #define regSE_CAC_WEIGHT_TD_2 … #define regSE_CAC_WEIGHT_TD_2_BASE_IDX … #define regSE_CAC_WEIGHT_TD_3 … #define regSE_CAC_WEIGHT_TD_3_BASE_IDX … #define regSE_CAC_WEIGHT_TD_4 … #define regSE_CAC_WEIGHT_TD_4_BASE_IDX … #define regSE_CAC_WEIGHT_TD_5 … #define regSE_CAC_WEIGHT_TD_5_BASE_IDX … #define regSE_CAC_WEIGHT_TD_6 … #define regSE_CAC_WEIGHT_TD_6_BASE_IDX … #define regSE_CAC_WEIGHT_TD_7 … #define regSE_CAC_WEIGHT_TD_7_BASE_IDX … #define regSE_CAC_WEIGHT_TD_8 … #define regSE_CAC_WEIGHT_TD_8_BASE_IDX … #define regSE_CAC_WEIGHT_TD_9 … #define regSE_CAC_WEIGHT_TD_9_BASE_IDX … #define regSE_CAC_WEIGHT_TCP_0 … #define regSE_CAC_WEIGHT_TCP_0_BASE_IDX … #define regSE_CAC_WEIGHT_TCP_1 … #define regSE_CAC_WEIGHT_TCP_1_BASE_IDX … #define regSE_CAC_WEIGHT_TCP_2 … #define regSE_CAC_WEIGHT_TCP_2_BASE_IDX … #define regSE_CAC_WEIGHT_TCP_3 … #define regSE_CAC_WEIGHT_TCP_3_BASE_IDX … #define regSE_CAC_WEIGHT_SQ_0 … #define regSE_CAC_WEIGHT_SQ_0_BASE_IDX … #define regSE_CAC_WEIGHT_SQ_1 … #define regSE_CAC_WEIGHT_SQ_1_BASE_IDX … #define regSE_CAC_WEIGHT_SQ_2 … #define regSE_CAC_WEIGHT_SQ_2_BASE_IDX … #define regSE_CAC_WEIGHT_SP_0 … #define regSE_CAC_WEIGHT_SP_0_BASE_IDX … #define regSE_CAC_WEIGHT_SP_1 … #define regSE_CAC_WEIGHT_SP_1_BASE_IDX … #define regSE_CAC_WEIGHT_SP_2 … #define regSE_CAC_WEIGHT_SP_2_BASE_IDX … #define regSE_CAC_WEIGHT_LDS_0 … #define regSE_CAC_WEIGHT_LDS_0_BASE_IDX … #define regSE_CAC_WEIGHT_LDS_1 … #define regSE_CAC_WEIGHT_LDS_1_BASE_IDX … #define regSE_CAC_WEIGHT_LDS_2 … #define regSE_CAC_WEIGHT_LDS_2_BASE_IDX … #define regSE_CAC_WEIGHT_LDS_3 … #define regSE_CAC_WEIGHT_LDS_3_BASE_IDX … #define regSE_CAC_WEIGHT_SQC_0 … #define regSE_CAC_WEIGHT_SQC_0_BASE_IDX … #define regSE_CAC_WEIGHT_SQC_1 … #define regSE_CAC_WEIGHT_SQC_1_BASE_IDX … #define regSE_CAC_WEIGHT_CU_0 … #define regSE_CAC_WEIGHT_CU_0_BASE_IDX … #define regSE_CAC_WEIGHT_BCI_0 … #define regSE_CAC_WEIGHT_BCI_0_BASE_IDX … #define regSE_CAC_WEIGHT_CB_0 … #define regSE_CAC_WEIGHT_CB_0_BASE_IDX … #define regSE_CAC_WEIGHT_CB_1 … #define regSE_CAC_WEIGHT_CB_1_BASE_IDX … #define regSE_CAC_WEIGHT_CB_2 … #define regSE_CAC_WEIGHT_CB_2_BASE_IDX … #define regSE_CAC_WEIGHT_CB_3 … #define regSE_CAC_WEIGHT_CB_3_BASE_IDX … #define regSE_CAC_WEIGHT_CB_4 … #define regSE_CAC_WEIGHT_CB_4_BASE_IDX … #define regSE_CAC_WEIGHT_CB_5 … #define regSE_CAC_WEIGHT_CB_5_BASE_IDX … #define regSE_CAC_WEIGHT_CB_6 … #define regSE_CAC_WEIGHT_CB_6_BASE_IDX … #define regSE_CAC_WEIGHT_CB_7 … #define regSE_CAC_WEIGHT_CB_7_BASE_IDX … #define regSE_CAC_WEIGHT_CB_8 … #define regSE_CAC_WEIGHT_CB_8_BASE_IDX … #define regSE_CAC_WEIGHT_CB_9 … #define regSE_CAC_WEIGHT_CB_9_BASE_IDX … #define regSE_CAC_WEIGHT_CB_10 … #define regSE_CAC_WEIGHT_CB_10_BASE_IDX … #define regSE_CAC_WEIGHT_CB_11 … #define regSE_CAC_WEIGHT_CB_11_BASE_IDX … #define regSE_CAC_WEIGHT_DB_0 … #define regSE_CAC_WEIGHT_DB_0_BASE_IDX … #define regSE_CAC_WEIGHT_DB_1 … #define regSE_CAC_WEIGHT_DB_1_BASE_IDX … #define regSE_CAC_WEIGHT_DB_2 … #define regSE_CAC_WEIGHT_DB_2_BASE_IDX … #define regSE_CAC_WEIGHT_DB_3 … #define regSE_CAC_WEIGHT_DB_3_BASE_IDX … #define regSE_CAC_WEIGHT_DB_4 … #define regSE_CAC_WEIGHT_DB_4_BASE_IDX … #define regSE_CAC_WEIGHT_SX_0 … #define regSE_CAC_WEIGHT_SX_0_BASE_IDX … #define regSE_CAC_WEIGHT_SXRB_0 … #define regSE_CAC_WEIGHT_SXRB_0_BASE_IDX … #define regSE_CAC_WEIGHT_UTCL1_0 … #define regSE_CAC_WEIGHT_UTCL1_0_BASE_IDX … #define regSE_CAC_WEIGHT_GL1C_0 … #define regSE_CAC_WEIGHT_GL1C_0_BASE_IDX … #define regSE_CAC_WEIGHT_GL1C_1 … #define regSE_CAC_WEIGHT_GL1C_1_BASE_IDX … #define regSE_CAC_WEIGHT_SPI_0 … #define regSE_CAC_WEIGHT_SPI_0_BASE_IDX … #define regSE_CAC_WEIGHT_SPI_1 … #define regSE_CAC_WEIGHT_SPI_1_BASE_IDX … #define regSE_CAC_WEIGHT_SPI_2 … #define regSE_CAC_WEIGHT_SPI_2_BASE_IDX … #define regSE_CAC_WEIGHT_PC_0 … #define regSE_CAC_WEIGHT_PC_0_BASE_IDX … #define regSE_CAC_WEIGHT_PA_0 … #define regSE_CAC_WEIGHT_PA_0_BASE_IDX … #define regSE_CAC_WEIGHT_PA_1 … #define regSE_CAC_WEIGHT_PA_1_BASE_IDX … #define regSE_CAC_WEIGHT_PA_2 … #define regSE_CAC_WEIGHT_PA_2_BASE_IDX … #define regSE_CAC_WEIGHT_PA_3 … #define regSE_CAC_WEIGHT_PA_3_BASE_IDX … #define regSE_CAC_WEIGHT_SC_0 … #define regSE_CAC_WEIGHT_SC_0_BASE_IDX … #define regSE_CAC_WEIGHT_SC_1 … #define regSE_CAC_WEIGHT_SC_1_BASE_IDX … #define regSE_CAC_WEIGHT_SC_2 … #define regSE_CAC_WEIGHT_SC_2_BASE_IDX … #define regSE_CAC_WEIGHT_SC_3 … #define regSE_CAC_WEIGHT_SC_3_BASE_IDX … #define regSE_CAC_WEIGHT_GL1XC_0 … #define regSE_CAC_WEIGHT_GL1XC_0_BASE_IDX … #define regSE_CAC_WEIGHT_GL1XC_1 … #define regSE_CAC_WEIGHT_GL1XC_1_BASE_IDX … #define regSE_CAC_WEIGHT_SE_GE_0 … #define regSE_CAC_WEIGHT_SE_GE_0_BASE_IDX … #define regSE_CAC_IND_INDEX … #define regSE_CAC_IND_INDEX_BASE_IDX … #define regSE_CAC_IND_DATA … #define regSE_CAC_IND_DATA_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_perfddec // base address: 0x34000 #define regGE2_SE_PERFCOUNTER0_LO … #define regGE2_SE_PERFCOUNTER0_LO_BASE_IDX … #define regGE2_SE_PERFCOUNTER0_HI … #define regGE2_SE_PERFCOUNTER0_HI_BASE_IDX … #define regGE2_SE_PERFCOUNTER1_LO … #define regGE2_SE_PERFCOUNTER1_LO_BASE_IDX … #define regGE2_SE_PERFCOUNTER1_HI … #define regGE2_SE_PERFCOUNTER1_HI_BASE_IDX … #define regGE2_SE_PERFCOUNTER2_LO … #define regGE2_SE_PERFCOUNTER2_LO_BASE_IDX … #define regGE2_SE_PERFCOUNTER2_HI … #define regGE2_SE_PERFCOUNTER2_HI_BASE_IDX … #define regGE2_SE_PERFCOUNTER3_LO … #define regGE2_SE_PERFCOUNTER3_LO_BASE_IDX … #define regGE2_SE_PERFCOUNTER3_HI … #define regGE2_SE_PERFCOUNTER3_HI_BASE_IDX … #define regGRBMH_PERFCOUNTER0_LO … #define regGRBMH_PERFCOUNTER0_LO_BASE_IDX … #define regGRBMH_PERFCOUNTER0_HI … #define regGRBMH_PERFCOUNTER0_HI_BASE_IDX … #define regGRBMH_PERFCOUNTER1_LO … #define regGRBMH_PERFCOUNTER1_LO_BASE_IDX … #define regGRBMH_PERFCOUNTER1_HI … #define regGRBMH_PERFCOUNTER1_HI_BASE_IDX … #define regPA_SU_PERFCOUNTER0_LO … #define regPA_SU_PERFCOUNTER0_LO_BASE_IDX … #define regPA_SU_PERFCOUNTER0_HI … #define regPA_SU_PERFCOUNTER0_HI_BASE_IDX … #define regPA_SU_PERFCOUNTER1_LO … #define regPA_SU_PERFCOUNTER1_LO_BASE_IDX … #define regPA_SU_PERFCOUNTER1_HI … #define regPA_SU_PERFCOUNTER1_HI_BASE_IDX … #define regPA_SU_PERFCOUNTER2_LO … #define regPA_SU_PERFCOUNTER2_LO_BASE_IDX … #define regPA_SU_PERFCOUNTER2_HI … #define regPA_SU_PERFCOUNTER2_HI_BASE_IDX … #define regPA_SU_PERFCOUNTER3_LO … #define regPA_SU_PERFCOUNTER3_LO_BASE_IDX … #define regPA_SU_PERFCOUNTER3_HI … #define regPA_SU_PERFCOUNTER3_HI_BASE_IDX … #define regPA_SC_PERFCOUNTER0_LO … #define regPA_SC_PERFCOUNTER0_LO_BASE_IDX … #define regPA_SC_PERFCOUNTER0_HI … #define regPA_SC_PERFCOUNTER0_HI_BASE_IDX … #define regPA_SC_PERFCOUNTER1_LO … #define regPA_SC_PERFCOUNTER1_LO_BASE_IDX … #define regPA_SC_PERFCOUNTER1_HI … #define regPA_SC_PERFCOUNTER1_HI_BASE_IDX … #define regPA_SC_PERFCOUNTER2_LO … #define regPA_SC_PERFCOUNTER2_LO_BASE_IDX … #define regPA_SC_PERFCOUNTER2_HI … #define regPA_SC_PERFCOUNTER2_HI_BASE_IDX … #define regPA_SC_PERFCOUNTER3_LO … #define regPA_SC_PERFCOUNTER3_LO_BASE_IDX … #define regPA_SC_PERFCOUNTER3_HI … #define regPA_SC_PERFCOUNTER3_HI_BASE_IDX … #define regPA_SC_PERFCOUNTER4_LO … #define regPA_SC_PERFCOUNTER4_LO_BASE_IDX … #define regPA_SC_PERFCOUNTER4_HI … #define regPA_SC_PERFCOUNTER4_HI_BASE_IDX … #define regPA_SC_PERFCOUNTER5_LO … #define regPA_SC_PERFCOUNTER5_LO_BASE_IDX … #define regPA_SC_PERFCOUNTER5_HI … #define regPA_SC_PERFCOUNTER5_HI_BASE_IDX … #define regPA_SC_PERFCOUNTER6_LO … #define regPA_SC_PERFCOUNTER6_LO_BASE_IDX … #define regPA_SC_PERFCOUNTER6_HI … #define regPA_SC_PERFCOUNTER6_HI_BASE_IDX … #define regPA_SC_PERFCOUNTER7_LO … #define regPA_SC_PERFCOUNTER7_LO_BASE_IDX … #define regPA_SC_PERFCOUNTER7_HI … #define regPA_SC_PERFCOUNTER7_HI_BASE_IDX … #define regSPI_PERFCOUNTER0_HI … #define regSPI_PERFCOUNTER0_HI_BASE_IDX … #define regSPI_PERFCOUNTER0_LO … #define regSPI_PERFCOUNTER0_LO_BASE_IDX … #define regSPI_PERFCOUNTER1_HI … #define regSPI_PERFCOUNTER1_HI_BASE_IDX … #define regSPI_PERFCOUNTER1_LO … #define regSPI_PERFCOUNTER1_LO_BASE_IDX … #define regSPI_PERFCOUNTER2_HI … #define regSPI_PERFCOUNTER2_HI_BASE_IDX … #define regSPI_PERFCOUNTER2_LO … #define regSPI_PERFCOUNTER2_LO_BASE_IDX … #define regSPI_PERFCOUNTER3_HI … #define regSPI_PERFCOUNTER3_HI_BASE_IDX … #define regSPI_PERFCOUNTER3_LO … #define regSPI_PERFCOUNTER3_LO_BASE_IDX … #define regSPI_PERFCOUNTER4_HI … #define regSPI_PERFCOUNTER4_HI_BASE_IDX … #define regSPI_PERFCOUNTER4_LO … #define regSPI_PERFCOUNTER4_LO_BASE_IDX … #define regSPI_PERFCOUNTER5_HI … #define regSPI_PERFCOUNTER5_HI_BASE_IDX … #define regSPI_PERFCOUNTER5_LO … #define regSPI_PERFCOUNTER5_LO_BASE_IDX … #define regPC_PERFCOUNTER0_HI … #define regPC_PERFCOUNTER0_HI_BASE_IDX … #define regPC_PERFCOUNTER0_LO … #define regPC_PERFCOUNTER0_LO_BASE_IDX … #define regPC_PERFCOUNTER1_HI … #define regPC_PERFCOUNTER1_HI_BASE_IDX … #define regPC_PERFCOUNTER1_LO … #define regPC_PERFCOUNTER1_LO_BASE_IDX … #define regPC_PERFCOUNTER2_HI … #define regPC_PERFCOUNTER2_HI_BASE_IDX … #define regPC_PERFCOUNTER2_LO … #define regPC_PERFCOUNTER2_LO_BASE_IDX … #define regPC_PERFCOUNTER3_HI … #define regPC_PERFCOUNTER3_HI_BASE_IDX … #define regPC_PERFCOUNTER3_LO … #define regPC_PERFCOUNTER3_LO_BASE_IDX … #define regSQ_PERFCOUNTER0_LO … #define regSQ_PERFCOUNTER0_LO_BASE_IDX … #define regSQ_PERFCOUNTER1_LO … #define regSQ_PERFCOUNTER1_LO_BASE_IDX … #define regSQ_PERFCOUNTER2_LO … #define regSQ_PERFCOUNTER2_LO_BASE_IDX … #define regSQ_PERFCOUNTER3_LO … #define regSQ_PERFCOUNTER3_LO_BASE_IDX … #define regSQ_PERFCOUNTER4_LO … #define regSQ_PERFCOUNTER4_LO_BASE_IDX … #define regSQ_PERFCOUNTER5_LO … #define regSQ_PERFCOUNTER5_LO_BASE_IDX … #define regSQ_PERFCOUNTER6_LO … #define regSQ_PERFCOUNTER6_LO_BASE_IDX … #define regSQ_PERFCOUNTER7_LO … #define regSQ_PERFCOUNTER7_LO_BASE_IDX … #define regSQG_PERFCOUNTER0_LO … #define regSQG_PERFCOUNTER0_LO_BASE_IDX … #define regSQG_PERFCOUNTER0_HI … #define regSQG_PERFCOUNTER0_HI_BASE_IDX … #define regSQG_PERFCOUNTER1_LO … #define regSQG_PERFCOUNTER1_LO_BASE_IDX … #define regSQG_PERFCOUNTER1_HI … #define regSQG_PERFCOUNTER1_HI_BASE_IDX … #define regSQG_PERFCOUNTER2_LO … #define regSQG_PERFCOUNTER2_LO_BASE_IDX … #define regSQG_PERFCOUNTER2_HI … #define regSQG_PERFCOUNTER2_HI_BASE_IDX … #define regSQG_PERFCOUNTER3_LO … #define regSQG_PERFCOUNTER3_LO_BASE_IDX … #define regSQG_PERFCOUNTER3_HI … #define regSQG_PERFCOUNTER3_HI_BASE_IDX … #define regSQG_PERFCOUNTER4_LO … #define regSQG_PERFCOUNTER4_LO_BASE_IDX … #define regSQG_PERFCOUNTER4_HI … #define regSQG_PERFCOUNTER4_HI_BASE_IDX … #define regSQG_PERFCOUNTER5_LO … #define regSQG_PERFCOUNTER5_LO_BASE_IDX … #define regSQG_PERFCOUNTER5_HI … #define regSQG_PERFCOUNTER5_HI_BASE_IDX … #define regSQG_PERFCOUNTER6_LO … #define regSQG_PERFCOUNTER6_LO_BASE_IDX … #define regSQG_PERFCOUNTER6_HI … #define regSQG_PERFCOUNTER6_HI_BASE_IDX … #define regSQG_PERFCOUNTER7_LO … #define regSQG_PERFCOUNTER7_LO_BASE_IDX … #define regSQG_PERFCOUNTER7_HI … #define regSQG_PERFCOUNTER7_HI_BASE_IDX … #define regSX_PERFCOUNTER0_LO … #define regSX_PERFCOUNTER0_LO_BASE_IDX … #define regSX_PERFCOUNTER0_HI … #define regSX_PERFCOUNTER0_HI_BASE_IDX … #define regSX_PERFCOUNTER1_LO … #define regSX_PERFCOUNTER1_LO_BASE_IDX … #define regSX_PERFCOUNTER1_HI … #define regSX_PERFCOUNTER1_HI_BASE_IDX … #define regSX_PERFCOUNTER2_LO … #define regSX_PERFCOUNTER2_LO_BASE_IDX … #define regSX_PERFCOUNTER2_HI … #define regSX_PERFCOUNTER2_HI_BASE_IDX … #define regSX_PERFCOUNTER3_LO … #define regSX_PERFCOUNTER3_LO_BASE_IDX … #define regSX_PERFCOUNTER3_HI … #define regSX_PERFCOUNTER3_HI_BASE_IDX … #define regTA_PERFCOUNTER0_LO … #define regTA_PERFCOUNTER0_LO_BASE_IDX … #define regTA_PERFCOUNTER0_HI … #define regTA_PERFCOUNTER0_HI_BASE_IDX … #define regTA_PERFCOUNTER1_LO … #define regTA_PERFCOUNTER1_LO_BASE_IDX … #define regTA_PERFCOUNTER1_HI … #define regTA_PERFCOUNTER1_HI_BASE_IDX … #define regTD_PERFCOUNTER0_LO … #define regTD_PERFCOUNTER0_LO_BASE_IDX … #define regTD_PERFCOUNTER0_HI … #define regTD_PERFCOUNTER0_HI_BASE_IDX … #define regTD_PERFCOUNTER1_LO … #define regTD_PERFCOUNTER1_LO_BASE_IDX … #define regTD_PERFCOUNTER1_HI … #define regTD_PERFCOUNTER1_HI_BASE_IDX … #define regTCP_PERFCOUNTER0_LO … #define regTCP_PERFCOUNTER0_LO_BASE_IDX … #define regTCP_PERFCOUNTER0_HI … #define regTCP_PERFCOUNTER0_HI_BASE_IDX … #define regTCP_PERFCOUNTER1_LO … #define regTCP_PERFCOUNTER1_LO_BASE_IDX … #define regTCP_PERFCOUNTER1_HI … #define regTCP_PERFCOUNTER1_HI_BASE_IDX … #define regTCP_PERFCOUNTER2_LO … #define regTCP_PERFCOUNTER2_LO_BASE_IDX … #define regTCP_PERFCOUNTER2_HI … #define regTCP_PERFCOUNTER2_HI_BASE_IDX … #define regTCP_PERFCOUNTER3_LO … #define regTCP_PERFCOUNTER3_LO_BASE_IDX … #define regTCP_PERFCOUNTER3_HI … #define regTCP_PERFCOUNTER3_HI_BASE_IDX … #define regTCP_PERFCOUNTER_FILTER … #define regTCP_PERFCOUNTER_FILTER_BASE_IDX … #define regTCP_PERFCOUNTER_FILTER2 … #define regTCP_PERFCOUNTER_FILTER2_BASE_IDX … #define regTCP_PERFCOUNTER_FILTER_EN … #define regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX … #define regGL1C_PERFCOUNTER0_LO … #define regGL1C_PERFCOUNTER0_LO_BASE_IDX … #define regGL1C_PERFCOUNTER0_HI … #define regGL1C_PERFCOUNTER0_HI_BASE_IDX … #define regGL1C_PERFCOUNTER1_LO … #define regGL1C_PERFCOUNTER1_LO_BASE_IDX … #define regGL1C_PERFCOUNTER1_HI … #define regGL1C_PERFCOUNTER1_HI_BASE_IDX … #define regGL1C_PERFCOUNTER2_LO … #define regGL1C_PERFCOUNTER2_LO_BASE_IDX … #define regGL1C_PERFCOUNTER2_HI … #define regGL1C_PERFCOUNTER2_HI_BASE_IDX … #define regGL1C_PERFCOUNTER3_LO … #define regGL1C_PERFCOUNTER3_LO_BASE_IDX … #define regGL1C_PERFCOUNTER3_HI … #define regGL1C_PERFCOUNTER3_HI_BASE_IDX … #define regGL1XC_PERFCOUNTER0_LO … #define regGL1XC_PERFCOUNTER0_LO_BASE_IDX … #define regGL1XC_PERFCOUNTER0_HI … #define regGL1XC_PERFCOUNTER0_HI_BASE_IDX … #define regGL1XC_PERFCOUNTER1_LO … #define regGL1XC_PERFCOUNTER1_LO_BASE_IDX … #define regGL1XC_PERFCOUNTER1_HI … #define regGL1XC_PERFCOUNTER1_HI_BASE_IDX … #define regGL1XC_PERFCOUNTER2_LO … #define regGL1XC_PERFCOUNTER2_LO_BASE_IDX … #define regGL1XC_PERFCOUNTER2_HI … #define regGL1XC_PERFCOUNTER2_HI_BASE_IDX … #define regGL1XC_PERFCOUNTER3_LO … #define regGL1XC_PERFCOUNTER3_LO_BASE_IDX … #define regGL1XC_PERFCOUNTER3_HI … #define regGL1XC_PERFCOUNTER3_HI_BASE_IDX … #define regCB_PERFCOUNTER0_LO … #define regCB_PERFCOUNTER0_LO_BASE_IDX … #define regCB_PERFCOUNTER0_HI … #define regCB_PERFCOUNTER0_HI_BASE_IDX … #define regCB_PERFCOUNTER1_LO … #define regCB_PERFCOUNTER1_LO_BASE_IDX … #define regCB_PERFCOUNTER1_HI … #define regCB_PERFCOUNTER1_HI_BASE_IDX … #define regCB_PERFCOUNTER2_LO … #define regCB_PERFCOUNTER2_LO_BASE_IDX … #define regCB_PERFCOUNTER2_HI … #define regCB_PERFCOUNTER2_HI_BASE_IDX … #define regCB_PERFCOUNTER3_LO … #define regCB_PERFCOUNTER3_LO_BASE_IDX … #define regCB_PERFCOUNTER3_HI … #define regCB_PERFCOUNTER3_HI_BASE_IDX … #define regDB_PERFCOUNTER0_LO … #define regDB_PERFCOUNTER0_LO_BASE_IDX … #define regDB_PERFCOUNTER0_HI … #define regDB_PERFCOUNTER0_HI_BASE_IDX … #define regDB_PERFCOUNTER1_LO … #define regDB_PERFCOUNTER1_LO_BASE_IDX … #define regDB_PERFCOUNTER1_HI … #define regDB_PERFCOUNTER1_HI_BASE_IDX … #define regDB_PERFCOUNTER2_LO … #define regDB_PERFCOUNTER2_LO_BASE_IDX … #define regDB_PERFCOUNTER2_HI … #define regDB_PERFCOUNTER2_HI_BASE_IDX … #define regDB_PERFCOUNTER3_LO … #define regDB_PERFCOUNTER3_LO_BASE_IDX … #define regDB_PERFCOUNTER3_HI … #define regDB_PERFCOUNTER3_HI_BASE_IDX … #define regRMI_PERFCOUNTER0_LO … #define regRMI_PERFCOUNTER0_LO_BASE_IDX … #define regRMI_PERFCOUNTER0_HI … #define regRMI_PERFCOUNTER0_HI_BASE_IDX … #define regRMI_PERFCOUNTER1_LO … #define regRMI_PERFCOUNTER1_LO_BASE_IDX … #define regRMI_PERFCOUNTER1_HI … #define regRMI_PERFCOUNTER1_HI_BASE_IDX … #define regRMI_PERFCOUNTER2_LO … #define regRMI_PERFCOUNTER2_LO_BASE_IDX … #define regRMI_PERFCOUNTER2_HI … #define regRMI_PERFCOUNTER2_HI_BASE_IDX … #define regRMI_PERFCOUNTER3_LO … #define regRMI_PERFCOUNTER3_LO_BASE_IDX … #define regRMI_PERFCOUNTER3_HI … #define regRMI_PERFCOUNTER3_HI_BASE_IDX … #define regPA_PH_PERFCOUNTER0_LO … #define regPA_PH_PERFCOUNTER0_LO_BASE_IDX … #define regPA_PH_PERFCOUNTER0_HI … #define regPA_PH_PERFCOUNTER0_HI_BASE_IDX … #define regPA_PH_PERFCOUNTER1_LO … #define regPA_PH_PERFCOUNTER1_LO_BASE_IDX … #define regPA_PH_PERFCOUNTER1_HI … #define regPA_PH_PERFCOUNTER1_HI_BASE_IDX … #define regPA_PH_PERFCOUNTER2_LO … #define regPA_PH_PERFCOUNTER2_LO_BASE_IDX … #define regPA_PH_PERFCOUNTER2_HI … #define regPA_PH_PERFCOUNTER2_HI_BASE_IDX … #define regPA_PH_PERFCOUNTER3_LO … #define regPA_PH_PERFCOUNTER3_LO_BASE_IDX … #define regPA_PH_PERFCOUNTER3_HI … #define regPA_PH_PERFCOUNTER3_HI_BASE_IDX … #define regPA_PH_PERFCOUNTER4_LO … #define regPA_PH_PERFCOUNTER4_LO_BASE_IDX … #define regPA_PH_PERFCOUNTER4_HI … #define regPA_PH_PERFCOUNTER4_HI_BASE_IDX … #define regPA_PH_PERFCOUNTER5_LO … #define regPA_PH_PERFCOUNTER5_LO_BASE_IDX … #define regPA_PH_PERFCOUNTER5_HI … #define regPA_PH_PERFCOUNTER5_HI_BASE_IDX … #define regPA_PH_PERFCOUNTER6_LO … #define regPA_PH_PERFCOUNTER6_LO_BASE_IDX … #define regPA_PH_PERFCOUNTER6_HI … #define regPA_PH_PERFCOUNTER6_HI_BASE_IDX … #define regPA_PH_PERFCOUNTER7_LO … #define regPA_PH_PERFCOUNTER7_LO_BASE_IDX … #define regPA_PH_PERFCOUNTER7_HI … #define regPA_PH_PERFCOUNTER7_HI_BASE_IDX … #define regUTCL1_PERFCOUNTER0_LO … #define regUTCL1_PERFCOUNTER0_LO_BASE_IDX … #define regUTCL1_PERFCOUNTER0_HI … #define regUTCL1_PERFCOUNTER0_HI_BASE_IDX … #define regUTCL1_PERFCOUNTER1_LO … #define regUTCL1_PERFCOUNTER1_LO_BASE_IDX … #define regUTCL1_PERFCOUNTER1_HI … #define regUTCL1_PERFCOUNTER1_HI_BASE_IDX … #define regUTCL1_PERFCOUNTER2_LO … #define regUTCL1_PERFCOUNTER2_LO_BASE_IDX … #define regUTCL1_PERFCOUNTER2_HI … #define regUTCL1_PERFCOUNTER2_HI_BASE_IDX … #define regUTCL1_PERFCOUNTER3_LO … #define regUTCL1_PERFCOUNTER3_LO_BASE_IDX … #define regUTCL1_PERFCOUNTER3_HI … #define regUTCL1_PERFCOUNTER3_HI_BASE_IDX … #define regGL1A_PERFCOUNTER0_LO … #define regGL1A_PERFCOUNTER0_LO_BASE_IDX … #define regGL1A_PERFCOUNTER0_HI … #define regGL1A_PERFCOUNTER0_HI_BASE_IDX … #define regGL1A_PERFCOUNTER1_LO … #define regGL1A_PERFCOUNTER1_LO_BASE_IDX … #define regGL1A_PERFCOUNTER1_HI … #define regGL1A_PERFCOUNTER1_HI_BASE_IDX … #define regGL1A_PERFCOUNTER2_LO … #define regGL1A_PERFCOUNTER2_LO_BASE_IDX … #define regGL1A_PERFCOUNTER2_HI … #define regGL1A_PERFCOUNTER2_HI_BASE_IDX … #define regGL1A_PERFCOUNTER3_LO … #define regGL1A_PERFCOUNTER3_LO_BASE_IDX … #define regGL1A_PERFCOUNTER3_HI … #define regGL1A_PERFCOUNTER3_HI_BASE_IDX … #define regGL1XA_PERFCOUNTER0_LO … #define regGL1XA_PERFCOUNTER0_LO_BASE_IDX … #define regGL1XA_PERFCOUNTER0_HI … #define regGL1XA_PERFCOUNTER0_HI_BASE_IDX … #define regGL1XA_PERFCOUNTER1_LO … #define regGL1XA_PERFCOUNTER1_LO_BASE_IDX … #define regGL1XA_PERFCOUNTER1_HI … #define regGL1XA_PERFCOUNTER1_HI_BASE_IDX … #define regGL1XA_PERFCOUNTER2_LO … #define regGL1XA_PERFCOUNTER2_LO_BASE_IDX … #define regGL1XA_PERFCOUNTER2_HI … #define regGL1XA_PERFCOUNTER2_HI_BASE_IDX … #define regGL1XA_PERFCOUNTER3_LO … #define regGL1XA_PERFCOUNTER3_LO_BASE_IDX … #define regGL1XA_PERFCOUNTER3_HI … #define regGL1XA_PERFCOUNTER3_HI_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_perfsdec // base address: 0x36000 #define regGRBMH_CP_PERFMON_CNTL … #define regGRBMH_CP_PERFMON_CNTL_BASE_IDX … #define regCP_PERFMON_CNTL_1 … #define regCP_PERFMON_CNTL_1_BASE_IDX … #define regGE2_SE_PERFCOUNTER0_SELECT … #define regGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX … #define regGE2_SE_PERFCOUNTER0_SELECT1 … #define regGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX … #define regGE2_SE_PERFCOUNTER1_SELECT … #define regGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX … #define regGE2_SE_PERFCOUNTER1_SELECT1 … #define regGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX … #define regGE2_SE_PERFCOUNTER2_SELECT … #define regGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX … #define regGE2_SE_PERFCOUNTER2_SELECT1 … #define regGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX … #define regGE2_SE_PERFCOUNTER3_SELECT … #define regGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX … #define regGE2_SE_PERFCOUNTER3_SELECT1 … #define regGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX … #define regGRBMH_PERFCOUNTER0_SELECT … #define regGRBMH_PERFCOUNTER0_SELECT_BASE_IDX … #define regGRBMH_PERFCOUNTER1_SELECT … #define regGRBMH_PERFCOUNTER1_SELECT_BASE_IDX … #define regPA_SU_PERFCOUNTER0_SELECT … #define regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX … #define regPA_SU_PERFCOUNTER0_SELECT1 … #define regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX … #define regPA_SU_PERFCOUNTER1_SELECT … #define regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX … #define regPA_SU_PERFCOUNTER1_SELECT1 … #define regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX … #define regPA_SU_PERFCOUNTER2_SELECT … #define regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX … #define regPA_SU_PERFCOUNTER2_SELECT1 … #define regPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX … #define regPA_SU_PERFCOUNTER3_SELECT … #define regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX … #define regPA_SU_PERFCOUNTER3_SELECT1 … #define regPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX … #define regPA_SC_PERFCOUNTER0_SELECT … #define regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX … #define regPA_SC_PERFCOUNTER0_SELECT1 … #define regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX … #define regPA_SC_PERFCOUNTER1_SELECT … #define regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX … #define regPA_SC_PERFCOUNTER2_SELECT … #define regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX … #define regPA_SC_PERFCOUNTER3_SELECT … #define regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX … #define regPA_SC_PERFCOUNTER4_SELECT … #define regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX … #define regPA_SC_PERFCOUNTER5_SELECT … #define regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX … #define regPA_SC_PERFCOUNTER6_SELECT … #define regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX … #define regPA_SC_PERFCOUNTER7_SELECT … #define regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX … #define regSPI_PERFCOUNTER0_SELECT … #define regSPI_PERFCOUNTER0_SELECT_BASE_IDX … #define regSPI_PERFCOUNTER1_SELECT … #define regSPI_PERFCOUNTER1_SELECT_BASE_IDX … #define regSPI_PERFCOUNTER2_SELECT … #define regSPI_PERFCOUNTER2_SELECT_BASE_IDX … #define regSPI_PERFCOUNTER3_SELECT … #define regSPI_PERFCOUNTER3_SELECT_BASE_IDX … #define regSPI_PERFCOUNTER4_SELECT … #define regSPI_PERFCOUNTER4_SELECT_BASE_IDX … #define regSPI_PERFCOUNTER5_SELECT … #define regSPI_PERFCOUNTER5_SELECT_BASE_IDX … #define regSPI_PERFCOUNTER0_SELECT1 … #define regSPI_PERFCOUNTER0_SELECT1_BASE_IDX … #define regSPI_PERFCOUNTER1_SELECT1 … #define regSPI_PERFCOUNTER1_SELECT1_BASE_IDX … #define regSPI_PERFCOUNTER2_SELECT1 … #define regSPI_PERFCOUNTER2_SELECT1_BASE_IDX … #define regSPI_PERFCOUNTER3_SELECT1 … #define regSPI_PERFCOUNTER3_SELECT1_BASE_IDX … #define regSPI_PERFCOUNTER4_SELECT1 … #define regSPI_PERFCOUNTER4_SELECT1_BASE_IDX … #define regSPI_PERFCOUNTER5_SELECT1 … #define regSPI_PERFCOUNTER5_SELECT1_BASE_IDX … #define regSPI_PERFCOUNTER_BINS … #define regSPI_PERFCOUNTER_BINS_BASE_IDX … #define regPC_PERFCOUNTER0_SELECT … #define regPC_PERFCOUNTER0_SELECT_BASE_IDX … #define regPC_PERFCOUNTER1_SELECT … #define regPC_PERFCOUNTER1_SELECT_BASE_IDX … #define regPC_PERFCOUNTER2_SELECT … #define regPC_PERFCOUNTER2_SELECT_BASE_IDX … #define regPC_PERFCOUNTER3_SELECT … #define regPC_PERFCOUNTER3_SELECT_BASE_IDX … #define regPC_PERFCOUNTER0_SELECT1 … #define regPC_PERFCOUNTER0_SELECT1_BASE_IDX … #define regPC_PERFCOUNTER1_SELECT1 … #define regPC_PERFCOUNTER1_SELECT1_BASE_IDX … #define regPC_PERFCOUNTER2_SELECT1 … #define regPC_PERFCOUNTER2_SELECT1_BASE_IDX … #define regPC_PERFCOUNTER3_SELECT1 … #define regPC_PERFCOUNTER3_SELECT1_BASE_IDX … #define regSQ_PERFCOUNTER0_SELECT … #define regSQ_PERFCOUNTER0_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER1_SELECT … #define regSQ_PERFCOUNTER1_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER2_SELECT … #define regSQ_PERFCOUNTER2_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER3_SELECT … #define regSQ_PERFCOUNTER3_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER4_SELECT … #define regSQ_PERFCOUNTER4_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER5_SELECT … #define regSQ_PERFCOUNTER5_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER6_SELECT … #define regSQ_PERFCOUNTER6_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER7_SELECT … #define regSQ_PERFCOUNTER7_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER8_SELECT … #define regSQ_PERFCOUNTER8_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER9_SELECT … #define regSQ_PERFCOUNTER9_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER10_SELECT … #define regSQ_PERFCOUNTER10_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER11_SELECT … #define regSQ_PERFCOUNTER11_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER12_SELECT … #define regSQ_PERFCOUNTER12_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER13_SELECT … #define regSQ_PERFCOUNTER13_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER14_SELECT … #define regSQ_PERFCOUNTER14_SELECT_BASE_IDX … #define regSQ_PERFCOUNTER15_SELECT … #define regSQ_PERFCOUNTER15_SELECT_BASE_IDX … #define regSQG_PERFCOUNTER0_SELECT … #define regSQG_PERFCOUNTER0_SELECT_BASE_IDX … #define regSQG_PERFCOUNTER1_SELECT … #define regSQG_PERFCOUNTER1_SELECT_BASE_IDX … #define regSQG_PERFCOUNTER2_SELECT … #define regSQG_PERFCOUNTER2_SELECT_BASE_IDX … #define regSQG_PERFCOUNTER3_SELECT … #define regSQG_PERFCOUNTER3_SELECT_BASE_IDX … #define regSQG_PERFCOUNTER4_SELECT … #define regSQG_PERFCOUNTER4_SELECT_BASE_IDX … #define regSQG_PERFCOUNTER5_SELECT … #define regSQG_PERFCOUNTER5_SELECT_BASE_IDX … #define regSQG_PERFCOUNTER6_SELECT … #define regSQG_PERFCOUNTER6_SELECT_BASE_IDX … #define regSQG_PERFCOUNTER7_SELECT … #define regSQG_PERFCOUNTER7_SELECT_BASE_IDX … #define regSQG_PERFCOUNTER_CTRL … #define regSQG_PERFCOUNTER_CTRL_BASE_IDX … #define regSQG_PERFCOUNTER_CTRL2 … #define regSQG_PERFCOUNTER_CTRL2_BASE_IDX … #define regSQG_PERF_SAMPLE_FINISH … #define regSQG_PERF_SAMPLE_FINISH_BASE_IDX … #define regSQ_PERFCOUNTER_CTRL … #define regSQ_PERFCOUNTER_CTRL_BASE_IDX … #define regSQ_PERFCOUNTER_CTRL2 … #define regSQ_PERFCOUNTER_CTRL2_BASE_IDX … #define regSQ_THREAD_TRACE_BUF0_SIZE … #define regSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX … #define regSQ_THREAD_TRACE_BUF0_BASE_LO … #define regSQ_THREAD_TRACE_BUF0_BASE_LO_BASE_IDX … #define regSQ_THREAD_TRACE_BUF0_BASE_HI … #define regSQ_THREAD_TRACE_BUF0_BASE_HI_BASE_IDX … #define regSQ_THREAD_TRACE_BUF1_SIZE … #define regSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX … #define regSQ_THREAD_TRACE_BUF1_BASE_LO … #define regSQ_THREAD_TRACE_BUF1_BASE_LO_BASE_IDX … #define regSQ_THREAD_TRACE_BUF1_BASE_HI … #define regSQ_THREAD_TRACE_BUF1_BASE_HI_BASE_IDX … #define regSQ_THREAD_TRACE_CTRL … #define regSQ_THREAD_TRACE_CTRL_BASE_IDX … #define regSQ_THREAD_TRACE_MASK … #define regSQ_THREAD_TRACE_MASK_BASE_IDX … #define regSQ_THREAD_TRACE_TOKEN_MASK … #define regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX … #define regSQ_THREAD_TRACE_WPTR … #define regSQ_THREAD_TRACE_WPTR_BASE_IDX … #define regSQ_THREAD_TRACE_HALT … #define regSQ_THREAD_TRACE_HALT_BASE_IDX … #define regSQ_THREAD_TRACE_POWEROFF_RESTORE_1 … #define regSQ_THREAD_TRACE_POWEROFF_RESTORE_1_BASE_IDX … #define regSQ_THREAD_TRACE_STATUS … #define regSQ_THREAD_TRACE_STATUS_BASE_IDX … #define regSQ_THREAD_TRACE_STATUS2 … #define regSQ_THREAD_TRACE_STATUS2_BASE_IDX … #define regSQ_THREAD_TRACE_GFX_DRAW_CNTR … #define regSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX … #define regSQ_THREAD_TRACE_GFX_MARKER_CNTR … #define regSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX … #define regSQ_THREAD_TRACE_HP3D_DRAW_CNTR … #define regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX … #define regSQ_THREAD_TRACE_HP3D_MARKER_CNTR … #define regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX … #define regSQ_THREAD_TRACE_DROPPED_CNTR … #define regSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX … #define regSQ_THREAD_TRACE_FINISH_DONE_DEBUG … #define regSQ_THREAD_TRACE_FINISH_DONE_DEBUG_BASE_IDX … #define regSX_PERFCOUNTER0_SELECT … #define regSX_PERFCOUNTER0_SELECT_BASE_IDX … #define regSX_PERFCOUNTER1_SELECT … #define regSX_PERFCOUNTER1_SELECT_BASE_IDX … #define regSX_PERFCOUNTER2_SELECT … #define regSX_PERFCOUNTER2_SELECT_BASE_IDX … #define regSX_PERFCOUNTER3_SELECT … #define regSX_PERFCOUNTER3_SELECT_BASE_IDX … #define regSX_PERFCOUNTER0_SELECT1 … #define regSX_PERFCOUNTER0_SELECT1_BASE_IDX … #define regSX_PERFCOUNTER1_SELECT1 … #define regSX_PERFCOUNTER1_SELECT1_BASE_IDX … #define regSX_PERFCOUNTER2_SELECT1 … #define regSX_PERFCOUNTER2_SELECT1_BASE_IDX … #define regSX_PERFCOUNTER3_SELECT1 … #define regSX_PERFCOUNTER3_SELECT1_BASE_IDX … #define regTA_PERFCOUNTER0_SELECT … #define regTA_PERFCOUNTER0_SELECT_BASE_IDX … #define regTA_PERFCOUNTER0_SELECT1 … #define regTA_PERFCOUNTER0_SELECT1_BASE_IDX … #define regTA_PERFCOUNTER1_SELECT … #define regTA_PERFCOUNTER1_SELECT_BASE_IDX … #define regTD_PERFCOUNTER0_SELECT … #define regTD_PERFCOUNTER0_SELECT_BASE_IDX … #define regTD_PERFCOUNTER0_SELECT1 … #define regTD_PERFCOUNTER0_SELECT1_BASE_IDX … #define regTD_PERFCOUNTER1_SELECT … #define regTD_PERFCOUNTER1_SELECT_BASE_IDX … #define regTCP_PERFCOUNTER0_SELECT … #define regTCP_PERFCOUNTER0_SELECT_BASE_IDX … #define regTCP_PERFCOUNTER0_SELECT1 … #define regTCP_PERFCOUNTER0_SELECT1_BASE_IDX … #define regTCP_PERFCOUNTER1_SELECT … #define regTCP_PERFCOUNTER1_SELECT_BASE_IDX … #define regTCP_PERFCOUNTER1_SELECT1 … #define regTCP_PERFCOUNTER1_SELECT1_BASE_IDX … #define regTCP_PERFCOUNTER2_SELECT … #define regTCP_PERFCOUNTER2_SELECT_BASE_IDX … #define regTCP_PERFCOUNTER3_SELECT … #define regTCP_PERFCOUNTER3_SELECT_BASE_IDX … #define regGL1C_PERFCOUNTER0_SELECT … #define regGL1C_PERFCOUNTER0_SELECT_BASE_IDX … #define regGL1C_PERFCOUNTER0_SELECT1 … #define regGL1C_PERFCOUNTER0_SELECT1_BASE_IDX … #define regGL1C_PERFCOUNTER1_SELECT … #define regGL1C_PERFCOUNTER1_SELECT_BASE_IDX … #define regGL1C_PERFCOUNTER1_SELECT1 … #define regGL1C_PERFCOUNTER1_SELECT1_BASE_IDX … #define regGL1C_PERFCOUNTER2_SELECT … #define regGL1C_PERFCOUNTER2_SELECT_BASE_IDX … #define regGL1C_PERFCOUNTER2_SELECT1 … #define regGL1C_PERFCOUNTER2_SELECT1_BASE_IDX … #define regGL1C_PERFCOUNTER3_SELECT … #define regGL1C_PERFCOUNTER3_SELECT_BASE_IDX … #define regGL1C_PERFCOUNTER3_SELECT1 … #define regGL1C_PERFCOUNTER3_SELECT1_BASE_IDX … #define regGL1XC_PERFCOUNTER0_SELECT … #define regGL1XC_PERFCOUNTER0_SELECT_BASE_IDX … #define regGL1XC_PERFCOUNTER0_SELECT1 … #define regGL1XC_PERFCOUNTER0_SELECT1_BASE_IDX … #define regGL1XC_PERFCOUNTER1_SELECT … #define regGL1XC_PERFCOUNTER1_SELECT_BASE_IDX … #define regGL1XC_PERFCOUNTER1_SELECT1 … #define regGL1XC_PERFCOUNTER1_SELECT1_BASE_IDX … #define regGL1XC_PERFCOUNTER2_SELECT … #define regGL1XC_PERFCOUNTER2_SELECT_BASE_IDX … #define regGL1XC_PERFCOUNTER2_SELECT1 … #define regGL1XC_PERFCOUNTER2_SELECT1_BASE_IDX … #define regGL1XC_PERFCOUNTER3_SELECT … #define regGL1XC_PERFCOUNTER3_SELECT_BASE_IDX … #define regGL1XC_PERFCOUNTER3_SELECT1 … #define regGL1XC_PERFCOUNTER3_SELECT1_BASE_IDX … #define regCB_PERFCOUNTER_FILTER … #define regCB_PERFCOUNTER_FILTER_BASE_IDX … #define regCB_PERFCOUNTER0_SELECT … #define regCB_PERFCOUNTER0_SELECT_BASE_IDX … #define regCB_PERFCOUNTER0_SELECT1 … #define regCB_PERFCOUNTER0_SELECT1_BASE_IDX … #define regCB_PERFCOUNTER1_SELECT … #define regCB_PERFCOUNTER1_SELECT_BASE_IDX … #define regCB_PERFCOUNTER2_SELECT … #define regCB_PERFCOUNTER2_SELECT_BASE_IDX … #define regCB_PERFCOUNTER3_SELECT … #define regCB_PERFCOUNTER3_SELECT_BASE_IDX … #define regDB_PERFCOUNTER0_SELECT … #define regDB_PERFCOUNTER0_SELECT_BASE_IDX … #define regDB_PERFCOUNTER0_SELECT1 … #define regDB_PERFCOUNTER0_SELECT1_BASE_IDX … #define regDB_PERFCOUNTER1_SELECT … #define regDB_PERFCOUNTER1_SELECT_BASE_IDX … #define regDB_PERFCOUNTER1_SELECT1 … #define regDB_PERFCOUNTER1_SELECT1_BASE_IDX … #define regDB_PERFCOUNTER2_SELECT … #define regDB_PERFCOUNTER2_SELECT_BASE_IDX … #define regDB_PERFCOUNTER2_SELECT1 … #define regDB_PERFCOUNTER2_SELECT1_BASE_IDX … #define regDB_PERFCOUNTER3_SELECT … #define regDB_PERFCOUNTER3_SELECT_BASE_IDX … #define regDB_PERFCOUNTER3_SELECT1 … #define regDB_PERFCOUNTER3_SELECT1_BASE_IDX … #define regRMI_PERFCOUNTER0_SELECT … #define regRMI_PERFCOUNTER0_SELECT_BASE_IDX … #define regRMI_PERFCOUNTER0_SELECT1 … #define regRMI_PERFCOUNTER0_SELECT1_BASE_IDX … #define regRMI_PERFCOUNTER1_SELECT … #define regRMI_PERFCOUNTER1_SELECT_BASE_IDX … #define regRMI_PERFCOUNTER2_SELECT … #define regRMI_PERFCOUNTER2_SELECT_BASE_IDX … #define regRMI_PERFCOUNTER2_SELECT1 … #define regRMI_PERFCOUNTER2_SELECT1_BASE_IDX … #define regRMI_PERFCOUNTER3_SELECT … #define regRMI_PERFCOUNTER3_SELECT_BASE_IDX … #define regRMI_PERF_COUNTER_CNTL … #define regRMI_PERF_COUNTER_CNTL_BASE_IDX … #define regPA_PH_PERFCOUNTER0_SELECT … #define regPA_PH_PERFCOUNTER0_SELECT_BASE_IDX … #define regPA_PH_PERFCOUNTER0_SELECT1 … #define regPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX … #define regPA_PH_PERFCOUNTER1_SELECT … #define regPA_PH_PERFCOUNTER1_SELECT_BASE_IDX … #define regPA_PH_PERFCOUNTER2_SELECT … #define regPA_PH_PERFCOUNTER2_SELECT_BASE_IDX … #define regPA_PH_PERFCOUNTER3_SELECT … #define regPA_PH_PERFCOUNTER3_SELECT_BASE_IDX … #define regPA_PH_PERFCOUNTER4_SELECT … #define regPA_PH_PERFCOUNTER4_SELECT_BASE_IDX … #define regPA_PH_PERFCOUNTER5_SELECT … #define regPA_PH_PERFCOUNTER5_SELECT_BASE_IDX … #define regPA_PH_PERFCOUNTER6_SELECT … #define regPA_PH_PERFCOUNTER6_SELECT_BASE_IDX … #define regPA_PH_PERFCOUNTER7_SELECT … #define regPA_PH_PERFCOUNTER7_SELECT_BASE_IDX … #define regPA_PH_PERFCOUNTER1_SELECT1 … #define regPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX … #define regPA_PH_PERFCOUNTER2_SELECT1 … #define regPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX … #define regPA_PH_PERFCOUNTER3_SELECT1 … #define regPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX … #define regUTCL1_PERFCOUNTER0_SELECT … #define regUTCL1_PERFCOUNTER0_SELECT_BASE_IDX … #define regUTCL1_PERFCOUNTER1_SELECT … #define regUTCL1_PERFCOUNTER1_SELECT_BASE_IDX … #define regUTCL1_PERFCOUNTER2_SELECT … #define regUTCL1_PERFCOUNTER2_SELECT_BASE_IDX … #define regUTCL1_PERFCOUNTER3_SELECT … #define regUTCL1_PERFCOUNTER3_SELECT_BASE_IDX … #define regGL1A_PERFCOUNTER0_SELECT … #define regGL1A_PERFCOUNTER0_SELECT_BASE_IDX … #define regGL1A_PERFCOUNTER0_SELECT1 … #define regGL1A_PERFCOUNTER0_SELECT1_BASE_IDX … #define regGL1A_PERFCOUNTER1_SELECT … #define regGL1A_PERFCOUNTER1_SELECT_BASE_IDX … #define regGL1A_PERFCOUNTER1_SELECT1 … #define regGL1A_PERFCOUNTER1_SELECT1_BASE_IDX … #define regGL1A_PERFCOUNTER2_SELECT … #define regGL1A_PERFCOUNTER2_SELECT_BASE_IDX … #define regGL1A_PERFCOUNTER2_SELECT1 … #define regGL1A_PERFCOUNTER2_SELECT1_BASE_IDX … #define regGL1A_PERFCOUNTER3_SELECT … #define regGL1A_PERFCOUNTER3_SELECT_BASE_IDX … #define regGL1A_PERFCOUNTER3_SELECT1 … #define regGL1A_PERFCOUNTER3_SELECT1_BASE_IDX … #define regGL1XA_PERFCOUNTER0_SELECT … #define regGL1XA_PERFCOUNTER0_SELECT_BASE_IDX … #define regGL1XA_PERFCOUNTER0_SELECT1 … #define regGL1XA_PERFCOUNTER0_SELECT1_BASE_IDX … #define regGL1XA_PERFCOUNTER1_SELECT … #define regGL1XA_PERFCOUNTER1_SELECT_BASE_IDX … #define regGL1XA_PERFCOUNTER1_SELECT1 … #define regGL1XA_PERFCOUNTER1_SELECT1_BASE_IDX … #define regGL1XA_PERFCOUNTER2_SELECT … #define regGL1XA_PERFCOUNTER2_SELECT_BASE_IDX … #define regGL1XA_PERFCOUNTER2_SELECT1 … #define regGL1XA_PERFCOUNTER2_SELECT1_BASE_IDX … #define regGL1XA_PERFCOUNTER3_SELECT … #define regGL1XA_PERFCOUNTER3_SELECT_BASE_IDX … #define regGL1XA_PERFCOUNTER3_SELECT1 … #define regGL1XA_PERFCOUNTER3_SELECT1_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_pwrdec // base address: 0x3c000 #define regGFX_ICG_SPI_RA0_CLK_CTRL … #define regGFX_ICG_SPI_RA0_CLK_CTRL_BASE_IDX … #define regGFX_ICG_SPI_RA1_CLK_CTRL … #define regGFX_ICG_SPI_RA1_CLK_CTRL_BASE_IDX … #define regGFX_ICG_SPI_CS_CTRL … #define regGFX_ICG_SPI_CS_CTRL_BASE_IDX … #define regGFX_ICG_SPI_PS_CTRL … #define regGFX_ICG_SPI_PS_CTRL_BASE_IDX … #define regGFX_ICG_SPIS_CTRL … #define regGFX_ICG_SPIS_CTRL_BASE_IDX … #define regCGTX_SPI_DEBUG_CLK_CTRL … #define regCGTX_SPI_DEBUG_CLK_CTRL_BASE_IDX … #define regGFX_ICG_SPI_CTRL … #define regGFX_ICG_SPI_CTRL_BASE_IDX … #define regGFX_ICG_PC_CLK_CTRL … #define regGFX_ICG_PC_CLK_CTRL_BASE_IDX … #define regGFX_ICG_BCI_CTRL … #define regGFX_ICG_BCI_CTRL_BASE_IDX … #define regCGTT_VGT_CLK_CTRL … #define regCGTT_VGT_CLK_CTRL_BASE_IDX … #define regCGTT_GS_NGG_CLK_CTRL … #define regCGTT_GS_NGG_CLK_CTRL_BASE_IDX … #define regCGTT_PA_CLK_CTRL … #define regCGTT_PA_CLK_CTRL_BASE_IDX … #define regCGTT_SQ_CLK_CTRL … #define regCGTT_SQ_CLK_CTRL_BASE_IDX … #define regCGTT_SQG_CLK_CTRL … #define regCGTT_SQG_CLK_CTRL_BASE_IDX … #define regSQ_ALU_CLK_CTRL … #define regSQ_ALU_CLK_CTRL_BASE_IDX … #define regSQ_TEX_CLK_CTRL … #define regSQ_TEX_CLK_CTRL_BASE_IDX … #define regSQ_LDS_CLK_CTRL … #define regSQ_LDS_CLK_CTRL_BASE_IDX … #define regSQ_CLK_CTRL … #define regSQ_CLK_CTRL_BASE_IDX … #define regICG_SQ_CLK_CTRL … #define regICG_SQ_CLK_CTRL_BASE_IDX … #define regICG_SP_CLK_CTRL … #define regICG_SP_CLK_CTRL_BASE_IDX … #define regGFX_ICG_SX_CLK_CTRL0 … #define regGFX_ICG_SX_CLK_CTRL0_BASE_IDX … #define regGFX_ICG_SX_CLK_CTRL1 … #define regGFX_ICG_SX_CLK_CTRL1_BASE_IDX … #define regGFX_ICG_SX_CLK_CTRL2 … #define regGFX_ICG_SX_CLK_CTRL2_BASE_IDX … #define regGFX_ICG_SX_CLK_CTRL3 … #define regGFX_ICG_SX_CLK_CTRL3_BASE_IDX … #define regGFX_ICG_SX_CLK_CTRL4 … #define regGFX_ICG_SX_CLK_CTRL4_BASE_IDX … #define regGFX_ICG_TA_CTRL … #define regGFX_ICG_TA_CTRL_BASE_IDX … #define regGFX_ICG_TD_CTRL … #define regGFX_ICG_TD_CTRL_BASE_IDX … #define regDB_CGTT_CLK_CTRL_0 … #define regDB_CGTT_CLK_CTRL_0_BASE_IDX … #define regGFX_ICG_CB_CTRL … #define regGFX_ICG_CB_CTRL_BASE_IDX … #define regGFX_ICG_RMI_CTRL … #define regGFX_ICG_RMI_CTRL_BASE_IDX … #define regGFX_ICG_SE_CAC_CLK_CTRL … #define regGFX_ICG_SE_CAC_CLK_CTRL_BASE_IDX … #define regCGTT_PH_CLK_CTRL0 … #define regCGTT_PH_CLK_CTRL0_BASE_IDX … #define regCGTT_PH_CLK_CTRL1 … #define regCGTT_PH_CLK_CTRL1_BASE_IDX … #define regCGTT_PH_CLK_CTRL2 … #define regCGTT_PH_CLK_CTRL2_BASE_IDX … #define regCGTT_PH_CLK_CTRL3 … #define regCGTT_PH_CLK_CTRL3_BASE_IDX … #define regGFX_ICG_TCP_CTRL … #define regGFX_ICG_TCP_CTRL_BASE_IDX … #define regICG_LDS_CLK_CTRL … #define regICG_LDS_CLK_CTRL_BASE_IDX … #define regGFX_ICG_UTCL1_CTRL … #define regGFX_ICG_UTCL1_CTRL_BASE_IDX … #define regGFX_ICG_GRBMH_CTRL … #define regGFX_ICG_GRBMH_CTRL_BASE_IDX … // addressBlock: gc_gfx_se_gfx_sc_pwrdec // base address: 0x3c344 #define regCGTT_SC_CLK_CTRL0 … #define regCGTT_SC_CLK_CTRL0_BASE_IDX … #define regCGTT_SC_CLK_CTRL1 … #define regCGTT_SC_CLK_CTRL1_BASE_IDX … #define regCGTT_SC_CLK_CTRL2 … #define regCGTT_SC_CLK_CTRL2_BASE_IDX … #define regCGTT_SC_CLK_CTRL3 … #define regCGTT_SC_CLK_CTRL3_BASE_IDX … #define regCGTT_SC_CLK_CTRL4 … #define regCGTT_SC_CLK_CTRL4_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_gl1_pwrdec // base address: 0x3c364 #define regICG_GL1C_CLK_CTRL … #define regICG_GL1C_CLK_CTRL_BASE_IDX … #define regGL1I_GL1R_MGCG_OVERRIDE … #define regGL1I_GL1R_MGCG_OVERRIDE_BASE_IDX … #define regGL1XI_GL1XR_MGCG_OVERRIDE … #define regGL1XI_GL1XR_MGCG_OVERRIDE_BASE_IDX … #define regICG_GL1XC_CLK_CTRL … #define regICG_GL1XC_CLK_CTRL_BASE_IDX … #define regICG_GL1A_CTRL … #define regICG_GL1A_CTRL_BASE_IDX … #define regICG_GL1XA_CTRL … #define regICG_GL1XA_CTRL_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_hypdec // base address: 0x3e000 #define regGL1_PIPE_STEER … #define regGL1_PIPE_STEER_BASE_IDX … #define regGL1X_PIPE_STEER … #define regGL1X_PIPE_STEER_BASE_IDX … #define regGC_USER_SHADER_ARRAY_CONFIG … #define regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX … #define regGRBMH_GC_USER_SA_UNIT_DISABLE … #define regGRBMH_GC_USER_SA_UNIT_DISABLE_BASE_IDX … #define regGC_USER_SA_UNIT_DISABLE_1 … #define regGC_USER_SA_UNIT_DISABLE_1_BASE_IDX … #define regGC_USER_RB_BACKEND_DISABLE … #define regGC_USER_RB_BACKEND_DISABLE_BASE_IDX … #define regGC_USER_RMI_REDUNDANCY … #define regGC_USER_RMI_REDUNDANCY_BASE_IDX … #define regGC_USER_SHADER_RATE_CONFIG … #define regGC_USER_SHADER_RATE_CONFIG_BASE_IDX … #define regGC_USER_SHADER_RATE_CONFIG_1 … #define regGC_USER_SHADER_RATE_CONFIG_1_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_grbmh_hypdec // base address: 0x3e480 #define regGRBMH_WGP_SA0_REMAP_CNTL … #define regGRBMH_WGP_SA0_REMAP_CNTL_BASE_IDX … #define regGRBMH_WGP_SA1_REMAP_CNTL … #define regGRBMH_WGP_SA1_REMAP_CNTL_BASE_IDX … #define regGRBMH_RB_SA0_REMAP_CNTL … #define regGRBMH_RB_SA0_REMAP_CNTL_BASE_IDX … #define regGRBMH_RB_SA1_REMAP_CNTL … #define regGRBMH_RB_SA1_REMAP_CNTL_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_grbm_hypdec // base address: 0x3e800 #define regGRBMH_GRBM_SA_REMAP_CNTL … #define regGRBMH_GRBM_SA_REMAP_CNTL_BASE_IDX … // addressBlock: gc_gfx_se_gfx_se_utcl1_pspdec // base address: 0x3f7f0 #define regUTCL1_SECURITY … #define regUTCL1_SECURITY_BASE_IDX … // addressBlock: cpwd_gccacind // base address: 0x0 #define ixGC_CAC_ID … #define ixGC_CAC_CNTL … #define ixGC_CAC_ACC_CP0 … #define ixGC_CAC_ACC_CP1 … #define ixGC_CAC_ACC_CP2 … #define ixGC_CAC_ACC_EA0 … #define ixGC_CAC_ACC_EA1 … #define ixGC_CAC_ACC_EA2 … #define ixGC_CAC_ACC_EA3 … #define ixGC_CAC_ACC_EA4 … #define ixGC_CAC_ACC_EA5 … #define ixGC_CAC_ACC_UTCL2_ROUTER0 … #define ixGC_CAC_ACC_UTCL2_ROUTER1 … #define ixGC_CAC_ACC_UTCL2_ROUTER2 … #define ixGC_CAC_ACC_UTCL2_ROUTER3 … #define ixGC_CAC_ACC_UTCL2_ROUTER4 … #define ixGC_CAC_ACC_UTCL2_ROUTER5 … #define ixGC_CAC_ACC_UTCL2_ROUTER6 … #define ixGC_CAC_ACC_UTCL2_ROUTER7 … #define ixGC_CAC_ACC_UTCL2_ROUTER8 … #define ixGC_CAC_ACC_UTCL2_ROUTER9 … #define ixGC_CAC_ACC_UTCL2_VML20 … #define ixGC_CAC_ACC_UTCL2_VML21 … #define ixGC_CAC_ACC_UTCL2_VML22 … #define ixGC_CAC_ACC_UTCL2_VML23 … #define ixGC_CAC_ACC_UTCL2_VML24 … #define ixGC_CAC_ACC_UTCL2_WALKER0 … #define ixGC_CAC_ACC_UTCL2_WALKER1 … #define ixGC_CAC_ACC_UTCL2_WALKER2 … #define ixGC_CAC_ACC_UTCL2_WALKER3 … #define ixGC_CAC_ACC_UTCL2_WALKER4 … #define ixGC_CAC_ACC_GE0 … #define ixGC_CAC_ACC_GE1 … #define ixGC_CAC_ACC_GE2 … #define ixGC_CAC_ACC_PMM0 … #define ixGC_CAC_ACC_SDMA0 … #define ixGC_CAC_ACC_SDMA1 … #define ixGC_CAC_ACC_SDMA2 … #define ixGC_CAC_ACC_SDMA3 … #define ixGC_CAC_ACC_SDMA4 … #define ixGC_CAC_ACC_SDMA5 … #define ixGC_CAC_ACC_SDMA6 … #define ixGC_CAC_ACC_SDMA7 … #define ixGC_CAC_ACC_SDMA8 … #define ixGC_CAC_ACC_SDMA9 … #define ixGC_CAC_ACC_SDMA10 … #define ixGC_CAC_ACC_SDMA11 … #define ixGC_CAC_ACC_CHC0 … #define ixGC_CAC_ACC_CHC1 … #define ixGC_CAC_ACC_CHC2 … #define ixGC_CAC_ACC_RLC0 … #define ixGC_CAC_ACC_GRBM0 … #define ixGC_CAC_ACC_GRBM1 … #define ixGC_CAC_ACC_GL2C0 … #define ixGC_CAC_ACC_GL2C1 … #define ixGC_CAC_ACC_GL2C2 … #define ixGC_CAC_ACC_GL2C3 … #define ixGC_CAC_ACC_GL2C4 … #define ixEDC_STALL_TO_RELEASE_LUT_1_4 … #define ixEDC_STALL_TO_RELEASE_LUT_5_7 … #define ixPCC_STALL_TO_RELEASE_LUT_1_4 … #define ixPCC_STALL_TO_RELEASE_LUT_5_7 … #define ixSTALL_TO_PWRBRK_LUT_1_4 … #define ixSTALL_TO_PWRBRK_LUT_5_7 … #define ixPWRBRK_STALL_TO_RELEASE_LUT_1_4 … #define ixPWRBRK_STALL_TO_RELEASE_LUT_5_7 … #define ixPWRBRK_RELEASE_TO_STALL_LUT_1_8 … #define ixPWRBRK_RELEASE_TO_STALL_LUT_9_16 … #define ixPWRBRK_RELEASE_TO_STALL_LUT_17_20 … #define ixFIXED_PATTERN_PERF_COUNTER_1 … #define ixFIXED_PATTERN_PERF_COUNTER_2 … #define ixFIXED_PATTERN_PERF_COUNTER_3 … #define ixFIXED_PATTERN_PERF_COUNTER_4 … #define ixFIXED_PATTERN_PERF_COUNTER_5 … #define ixFIXED_PATTERN_PERF_COUNTER_6 … #define ixFIXED_PATTERN_PERF_COUNTER_7 … #define ixFIXED_PATTERN_PERF_COUNTER_8 … #define ixFIXED_PATTERN_PERF_COUNTER_9 … #define ixFIXED_PATTERN_PERF_COUNTER_10 … #define ixHW_LUT_UPDATE_STATUS_1 … #define ixHW_LUT_UPDATE_STATUS_2 … // addressBlock: rtavfs_rtavfs_ind_reg_blk // base address: 0x0 #define ixRTAVFS_REG0 … #define ixRTAVFS_REG1 … #define ixRTAVFS_REG2 … #define ixRTAVFS_REG3 … #define ixRTAVFS_REG4 … #define ixRTAVFS_REG5 … #define ixRTAVFS_REG6 … #define ixRTAVFS_REG7 … #define ixRTAVFS_REG8 … #define ixRTAVFS_REG9 … #define ixRTAVFS_REG10 … #define ixRTAVFS_REG11 … #define ixRTAVFS_REG12 … #define ixRTAVFS_REG13 … #define ixRTAVFS_REG14 … #define ixRTAVFS_REG15 … #define ixRTAVFS_REG16 … #define ixRTAVFS_REG17 … #define ixRTAVFS_REG18 … #define ixRTAVFS_REG19 … #define ixRTAVFS_REG20 … #define ixRTAVFS_REG21 … #define ixRTAVFS_REG22 … #define ixRTAVFS_REG23 … #define ixRTAVFS_REG24 … #define ixRTAVFS_REG25 … #define ixRTAVFS_REG26 … #define ixRTAVFS_REG27 … #define ixRTAVFS_REG28 … #define ixRTAVFS_REG29 … #define ixRTAVFS_REG30 … #define ixRTAVFS_REG31 … #define ixRTAVFS_REG32 … #define ixRTAVFS_REG33 … #define ixRTAVFS_REG34 … #define ixRTAVFS_REG35 … #define ixRTAVFS_REG36 … #define ixRTAVFS_REG37 … #define ixRTAVFS_REG38 … #define ixRTAVFS_REG39 … #define ixRTAVFS_REG40 … #define ixRTAVFS_REG41 … #define ixRTAVFS_REG42 … #define ixRTAVFS_REG43 … #define ixRTAVFS_REG44 … #define ixRTAVFS_REG45 … #define ixRTAVFS_REG46 … #define ixRTAVFS_REG47 … #define ixRTAVFS_REG48 … #define ixRTAVFS_REG49 … #define ixRTAVFS_REG50 … #define ixRTAVFS_REG51 … #define ixRTAVFS_REG52 … #define ixRTAVFS_REG53 … #define ixRTAVFS_REG54 … #define ixRTAVFS_REG55 … #define ixRTAVFS_REG56 … #define ixRTAVFS_REG57 … #define ixRTAVFS_REG58 … #define ixRTAVFS_REG59 … #define ixRTAVFS_REG60 … #define ixRTAVFS_REG61 … #define ixRTAVFS_REG62 … #define ixRTAVFS_REG63 … #define ixRTAVFS_REG64 … #define ixRTAVFS_REG65 … #define ixRTAVFS_REG66 … #define ixRTAVFS_REG67 … #define ixRTAVFS_REG68 … #define ixRTAVFS_REG69 … #define ixRTAVFS_REG70 … #define ixRTAVFS_REG71 … #define ixRTAVFS_REG72 … #define ixRTAVFS_REG73 … #define ixRTAVFS_REG74 … #define ixRTAVFS_REG75 … #define ixRTAVFS_REG76 … #define ixRTAVFS_REG77 … #define ixRTAVFS_REG78 … #define ixRTAVFS_REG79 … #define ixRTAVFS_REG80 … #define ixRTAVFS_REG81 … #define ixRTAVFS_REG82 … #define ixRTAVFS_REG83 … #define ixRTAVFS_REG84 … #define ixRTAVFS_REG85 … #define ixRTAVFS_REG86 … #define ixRTAVFS_REG87 … #define ixRTAVFS_REG88 … #define ixRTAVFS_REG89 … #define ixRTAVFS_REG90 … #define ixRTAVFS_REG91 … #define ixRTAVFS_REG92 … #define ixRTAVFS_REG93 … #define ixRTAVFS_REG94 … #define ixRTAVFS_REG95 … #define ixRTAVFS_REG96 … #define ixRTAVFS_REG97 … #define ixRTAVFS_REG98 … #define ixRTAVFS_REG99 … #define ixRTAVFS_REG100 … #define ixRTAVFS_REG101 … #define ixRTAVFS_REG102 … #define ixRTAVFS_REG103 … #define ixRTAVFS_REG104 … #define ixRTAVFS_REG105 … #define ixRTAVFS_REG106 … #define ixRTAVFS_REG107 … #define ixRTAVFS_REG108 … #define ixRTAVFS_REG109 … #define ixRTAVFS_REG110 … #define ixRTAVFS_REG111 … #define ixRTAVFS_REG112 … #define ixRTAVFS_REG113 … #define ixRTAVFS_REG114 … #define ixRTAVFS_REG115 … #define ixRTAVFS_REG116 … #define ixRTAVFS_REG117 … #define ixRTAVFS_REG118 … #define ixRTAVFS_REG119 … #define ixRTAVFS_REG120 … #define ixRTAVFS_REG121 … #define ixRTAVFS_REG122 … #define ixRTAVFS_REG123 … #define ixRTAVFS_REG124 … #define ixRTAVFS_REG125 … #define ixRTAVFS_REG126 … #define ixRTAVFS_REG127 … #define ixRTAVFS_REG128 … #define ixRTAVFS_REG129 … #define ixRTAVFS_REG130 … #define ixRTAVFS_REG131 … #define ixRTAVFS_REG132 … #define ixRTAVFS_REG133 … #define ixRTAVFS_REG134 … #define ixRTAVFS_REG135 … #define ixRTAVFS_REG136 … #define ixRTAVFS_REG137 … #define ixRTAVFS_REG138 … #define ixRTAVFS_REG139 … #define ixRTAVFS_REG140 … #define ixRTAVFS_REG141 … #define ixRTAVFS_REG142 … #define ixRTAVFS_REG143 … #define ixRTAVFS_REG144 … #define ixRTAVFS_REG145 … #define ixRTAVFS_REG146 … #define ixRTAVFS_REG147 … #define ixRTAVFS_REG148 … #define ixRTAVFS_REG149 … #define ixRTAVFS_REG150 … #define ixRTAVFS_REG151 … #define ixRTAVFS_REG152 … #define ixRTAVFS_REG153 … #define ixRTAVFS_REG154 … #define ixRTAVFS_REG155 … #define ixRTAVFS_REG156 … #define ixRTAVFS_REG157 … #define ixRTAVFS_REG158 … #define ixRTAVFS_REG159 … #define ixRTAVFS_REG160 … #define ixRTAVFS_REG161 … #define ixRTAVFS_REG162 … #define ixRTAVFS_REG163 … #define ixRTAVFS_REG164 … #define ixRTAVFS_REG165 … #define ixRTAVFS_REG166 … #define ixRTAVFS_REG167 … #define ixRTAVFS_REG168 … #define ixRTAVFS_REG169 … #define ixRTAVFS_REG170 … #define ixRTAVFS_REG171 … #define ixRTAVFS_REG172 … #define ixRTAVFS_REG173 … #define ixRTAVFS_REG174 … #define ixRTAVFS_REG175 … #define ixRTAVFS_REG176 … #define ixRTAVFS_REG177 … #define ixRTAVFS_REG178 … #define ixRTAVFS_REG179 … #define ixRTAVFS_REG180 … #define ixRTAVFS_REG181 … #define ixRTAVFS_REG182 … #define ixRTAVFS_REG183 … #define ixRTAVFS_REG184 … #define ixRTAVFS_REG185 … #define ixRTAVFS_REG186 … #define ixRTAVFS_REG187 … #define ixRTAVFS_REG188 … #define ixRTAVFS_REG189 … #define ixRTAVFS_REG190 … #define ixRTAVFS_REG191 … #define ixRTAVFS_REG192 … #define ixRTAVFS_REG193 … #define ixRTAVFS_REG194 … // addressBlock: dbgu_gfx_ports_blk // base address: 0x0 #define ixPACKER_CONTROL … // addressBlock: gfx_se_sqind // base address: 0x0 #define ixSQ_DEBUG_STS_LOCAL … #define ixSQ_DEBUG_CTRL_LOCAL … #define ixSQ_WAVE_ACTIVE … #define ixSQ_WAVE_VALID_AND_IDLE … #define ixSQ_WAVE_MODE … #define ixSQ_WAVE_STATUS … #define ixSQ_WAVE_STATE_PRIV … #define ixSQ_WAVE_GPR_ALLOC … #define ixSQ_WAVE_LDS_ALLOC … #define ixSQ_WAVE_IB_STS … #define ixSQ_PERF_SNAPSHOT_DATA … #define ixSQ_PERF_SNAPSHOT_PC_LO … #define ixSQ_PERF_SNAPSHOT_PC_HI … #define ixSQ_WAVE_IB_DBG1 … #define ixSQ_WAVE_FLUSH_IB … #define ixSQ_PERF_SNAPSHOT_DATA1 … #define ixSQ_PERF_SNAPSHOT_DATA2 … #define ixSQ_WAVE_EXCP_FLAG_PRIV … #define ixSQ_WAVE_EXCP_FLAG_USER … #define ixSQ_WAVE_TRAP_CTRL … #define ixSQ_WAVE_SCRATCH_BASE_LO … #define ixSQ_WAVE_SCRATCH_BASE_HI … #define ixSQ_WAVE_HW_ID1 … #define ixSQ_WAVE_HW_ID2 … #define ixSQ_WAVE_SCHED_MODE … #define ixSQ_WAVE_IB_STS2 … #define ixSQ_SHADER_CYCLES_LO … #define ixSQ_SHADER_CYCLES_HI … #define ixSQ_WAVE_DVGPR_ALLOC_LO … #define ixSQ_WAVE_DVGPR_ALLOC_HI … #define ixSQ_WAVE_PC_LO … #define ixSQ_WAVE_PC_HI … #define ixSQ_WAVE_TTMP0 … #define ixSQ_WAVE_TTMP1 … #define ixSQ_WAVE_TTMP2 … #define ixSQ_WAVE_TTMP3 … #define ixSQ_WAVE_TTMP4 … #define ixSQ_WAVE_TTMP5 … #define ixSQ_WAVE_TTMP6 … #define ixSQ_WAVE_TTMP7 … #define ixSQ_WAVE_TTMP8 … #define ixSQ_WAVE_TTMP9 … #define ixSQ_WAVE_TTMP10 … #define ixSQ_WAVE_TTMP11 … #define ixSQ_WAVE_TTMP12 … #define ixSQ_WAVE_TTMP13 … #define ixSQ_WAVE_TTMP14 … #define ixSQ_WAVE_TTMP15 … #define ixSQ_WAVE_M0 … #define ixSQ_WAVE_EXEC_LO … #define ixSQ_WAVE_EXEC_HI … // addressBlock: gfx_se_secacind // base address: 0x0 #define ixSE_CAC_ID … #define ixSE_CAC_CNTL … #endif
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