// SPDX-License-Identifier: MIT /* * Copyright © 2021-2024 Intel Corporation */ #include <linux/pci.h> #include <drm/drm_managed.h> #include <drm/drm_print.h> #include "regs/xe_bars.h" #include "regs/xe_gt_regs.h" #include "regs/xe_regs.h" #include "xe_assert.h" #include "xe_device.h" #include "xe_force_wake.h" #include "xe_gt_mcr.h" #include "xe_gt_sriov_vf.h" #include "xe_mmio.h" #include "xe_module.h" #include "xe_sriov.h" #include "xe_vram.h" #define BAR_SIZE_SHIFT … static void _resize_bar(struct xe_device *xe, int resno, resource_size_t size) { … } /* * if force_vram_bar_size is set, attempt to set to the requested size * else set to maximum possible size */ static void resize_vram_bar(struct xe_device *xe) { … } static bool resource_is_valid(struct pci_dev *pdev, int bar) { … } static int determine_lmem_bar_size(struct xe_device *xe) { … } static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size) { … } /* * tile_vram_size() - Collect vram size and offset information * @tile: tile to get info for * @vram_size: available vram (size - device reserved portions) * @tile_size: actual vram size * @tile_offset: physical start point in the vram address space * * There are 4 places for size information: * - io size (from pci_resource_len of LMEM bar) (only used for small bar and DG1) * - TILEx size (actual vram size) * - GSMBASE offset (TILEx - "stolen") * - CSSBASE offset (TILEx - CSS space necessary) * * CSSBASE is always a lower/smaller offset then GSMBASE. * * The actual available size of memory is to the CCS or GSM base. * NOTE: multi-tile bases will include the tile offset. * */ static int tile_vram_size(struct xe_tile *tile, u64 *vram_size, u64 *tile_size, u64 *tile_offset) { … } static void vram_fini(void *arg) { … } /** * xe_vram_probe() - Probe VRAM configuration * @xe: the &xe_device * * Collect VRAM size and offset information for all tiles. * * Return: 0 on success, error code on failure */ int xe_vram_probe(struct xe_device *xe) { … }